DE112016006634T5 - CONCERNING BODY CONTACT FOR SOI TRANSISTOR - Google Patents

Abstract

Systems, methods, and devices for improved body connection construction are described. The improved body connection design is configured to have a low resistance body connection when the transistor is "off" (Vg approximately 0 volts). If the transistor is "on"(Vg> Vt), then the resistance for the body connection is much higher, reducing the power loss associated with the presence of a body connection. Space efficient body connection constructions suitable for cascode configurations are also described.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is filed with November 18, 2015 U.S. Application No. 14 / 945,323 used, the disclosure of which is incorporated herein by reference in its entirety.

TECHNICAL AREA

Various embodiments described herein generally relate to systems, methods, and devices for suppressing floating body (non-attached body) effects in semiconductor devices.

BACKGROUND

Floating Body Silicon-on-insulator (SOI) transistors are limited in their operating voltage and power due to accumulated hot carriers that can increase the electrical potential of the body region of the SOI transistors. Body-connected SOI transistors have been demonstrated to increase voltage and power handling capabilities as compared to floating body SOI transistors.

It has been demonstrated that floating body SOI transistors have a drift of non-conducting hot carriers for a drain-source voltage (Vds) greater than about 3.2 volts (eg, reducing the magnitude of the threshold voltage and increasing the drain current in the non-conducting state). , It has been demonstrated that body-connected devices do not suffer from this mechanism.

When a floating body conducts transistor, a corresponding floating body effect can cause the abrupt reduction of the output impedance of the transistor at moderate bias at different levels of the drain-source voltage of the transistor, which in turn reduces the analog gain of the transistor and the complexity of corresponding device modeling can be increased. Body-connected devices (transistors) suppress the reduction in output impedance and extend the higher output impedance range to higher drain-to-source voltages.

Body connections for wide (large gate width) transistors with conventional (H-gate, T-gate) body interconnect structures are less effective in suppressing device degradation due to high resistance and parasitic capacitance, which attenuate the ability to control floating body effects , In particular, conventional body-connected devices (eg, H-gate, T-gate) are less effective at suppressing such large transistor width degradation, and the additional drain-source capacitance associated with conventional body-connected devices can improve performance in applications where such transistors are used, for example in radio frequency (RF) amplifier applications.

Although body connections can improve transistor voltage performance, the on-line conduction performance of the transistor can be degraded.

OVERVIEW

It may be desirable to extend the voltage and power handling capability for semiconductor devices, for example, integrated RF circuits, by providing an improved body interconnect design. Such semiconductor devices may include metal oxide semiconductor (MOS) field effect transistors (FETs), complementary metal oxide semiconductor (CMOS) FETs, and particularly MOSFETs and CMOSFETs having silicon on insulator (SOI) and silicon on sapphire and silicon on sapphire (SOS) substrates, respectively. Such semiconductor devices that are equipped with the improved body interconnection construction according to the various teachings of the present disclosure can be used, for example, in radio frequency (RF) amplifiers including, but not limited to, RF power amplifiers and RF cellular power amplifiers. which operate in various classes of operation having, but not limited to, the switching classes D, E and F, the saturated classes B and C, and the linear classes A and A / B.

According to a first aspect of the present disclosure, there is provided a semiconductor structure, the semiconductor structure comprising: a first gate polysilicon structure defining a first body region, the first body region having a first conductivity type; a second gate polysilicon structure defining a second body region, the second body region having the first conductivity type; a first drain region adjacent to the first body region having a second conductivity type; a first source region adjacent to the first body region having the second conductivity type; a second source region adjacent to the second body region having the second conductivity type; a second Drain region adjacent to the second body region having the second conductivity type, the first source region and the second drain region defining a first common source / drain region having the second conductivity type; a first non-conductive isolation region configured to form an interruption in the second body region to separate the second body region into two separate body regions; at least one first body contact region of the first conductivity type formed in the first common source / drain region separate from the first and second body regions and abutting the first non-conductive isolation region; and at least one first body stripe of the first conductivity type extending over the first common source / drain region in contact with the first body region and the at least one first body contact region, wherein the first nonconductive isolation region comprises at least a first body contact region and the at least one first body stripes define a first fitting body connection structure.

According to a second aspect of the present disclosure, there is described a semiconductor structure comprising a plurality of transistors, the semiconductor structure comprising: an insulating layer; a silicon layer overlying the insulating layer; active regions formed in the silicon layer, the active regions extending through the silicon layer to contact the insulating layer, the active regions having body regions, source regions, and drain regions of one or more fingers of each transistor of the plurality of transistors formed as cascode stacks for each two consecutive transistors of the cascode stack, a source region of a finger of an upper transistor and the drain region of a finger of a lower transistor of each two consecutive transistors in a common source / drain region of the silicon layer are trained; and at least one adjacent body connection structure associated with the upper finger and comprising: i) a non-conductive isolation region; ii) a body contact region formed in the common source / drain region of the fingers of two consecutive transistors separate from the body regions of the fingers and abutting an isolation region of the non-conductive isolation region; and iii) a body stripe region formed in the silicon layer in contact with the body region of the finger of the upper transistor and the body contact region, the at least one non-conductive isolation region being configured to: form an interruption in a region of the silicon layer that covers the body region of the finger of the lower transistor to divide the body region into separate body regions, and extending the break into a region of the silicon layer defining body regions and common source / drain regions of fingers of one or more consecutive transistors adjacent to the lower transistor to divide the areas into separate areas.

According to a third aspect of the present disclosure there is provided a method of providing a body connection for transistors arranged in a cascode configuration, the cascode configuration comprising: a first gate polysilicon structure defining a first body region, wherein the first body region comprises a first body region Conductivity type has; a second gate polysilicon structure defining a second body region, the second body region having the first conductivity type; a first drain region adjacent to the first body region having a second conductivity type; a first source region adjacent to the first body region having the second conductivity type; a second source region adjacent to the second body region having the second conductivity type; a second drain region adjacent to the second body region having the second conductivity type, and wherein the first source region and the second drain region define a first common source / drain region having the second conductivity type; the method comprising: forming, by means of a first non-conductive isolation region, an interruption in the second body region to separate the second body region into two separate body regions; Forming at least one first body contact region of the first conductivity type in the first common source / drain region separated from the first and second body regions applied to the first non-conductive isolation region; and forming at least one first body stripe of the first conductivity type extending over the first common source / drain region in contact with the first body region and the at least one first body contact region, wherein the first non-conductive isolation region, the at least one first body contact region and the at least one a first body strip defining a first fitting body connection structure.

list of figures

• 1A zeigt eine Draufsicht auf eine MOSFET-Transistorvorrichtung vom N-Typ.
• 1B zeigt eine Querschnittsansicht entlang der Linie A der Transistorvorrichtung in 1A.
• 1C zeigt eine schematische Darstellung der Transistorvorrichtung von 1A.
• 2A zeigt eine Draufsicht auf eine MOSFET-Transistorvorrichtung vom N-Typ mit einer T-Gate Body-Verbindung gemäß einer Ausführungsform des Stands der Technik.
• 2B zeigt eine schematische Darstellung der Transistorvorrichtung von 2A.
• 2C zeigt eine Draufsicht auf eine MOSFET-Transistorvorrichtung vom N-Typ mit einer H-Gate Body-Verbindung gemäß einer Ausführungsform des Stands der Technik.
• 3A zeigt eine Draufsicht auf eine MOSFET-Transistorvorrichtung vom N-Typ mit einer Source-Body-Verbindung gemäß einer Ausführungsform des Stands der Technik.
• 3B zeigt eine schematische Darstellung der Transistorvorrichtung von 3A.
• 4A zeigt eine Draufsicht auf einen MOSFET-Transistor vom N-Typ mit einem anliegenden Bodykontakt gemäß einer Ausführungsform der vorliegenden Offenbarung.
• 4B zeigt eine Querschnittsansicht entlang der Linie B der Transistorvorrichtung in 4A.
• 5A zeigt eine Draufsicht auf einen MOSFET-Transistor vom N-Typ mit einem anliegenden Bodykontakt gemäß einer anderen Ausführungsform der vorliegenden Offenbarung.
• 5B zeigt eine Querschnittsansicht entlang der Linie C der Transistorvorrichtung in 5A.
• 5C zeigt eine schematische Darstellung der Transistorvorrichtung von 4A und 5A.
• 6 zeigt eine Draufsicht auf einen MOSFET-Transistor vom N-Typ mit einem anliegenden Bodykontakt gemäß einer anderen Ausführungsform der vorliegenden Offenbarung, wobei der Bodykontakt über eine Vielzahl einzelner Body-Streifen hergestellt wird.
• 7A und 7B zeigen Draufsichten auf andere Ausführungsformen der in 6 gezeigten Ausführungsform.
• 8A zeigt eine Draufsicht auf zwei benachbarte Finger einer Transistorvorrichtung mit einem anliegenden Bodykontakt gemäß einer Ausführungsform der vorliegenden Offenbarung, wobei entsprechende Polysilizium-Streifen in einem gemeinsamen Sourcebereich hergestellt sind.
• 8B zeigt eine andere Ausführungsform der in 8A gezeigten Ausführungsform, wobei die entsprechenden Polysilizium-Streifen verbunden sind.
• 8C-8H zeigen Draufsichten auf gestapelte Transistoren mit anliegenden Bodykontakten gemäß verschiedenen Ausführungsformen der vorliegenden Offenbarung.
• 8I stellt die gestapelten Transistoren von 8C und 8D schematisch dar.
• 8J stellt die gestapelten Transistoren von 8E schematisch dar.
• 8K stellt die gestapelten Transistoren von 8F schematisch dar.
• 9A zeigt eine Draufsicht auf einen Transistor mit einem isolierten anliegenden Bodykontakt.
• 9B zeigt eine Querschnittsansicht entlang der Linie F der Transistorvorrichtung in 9A.
• 9C zeigt eine Draufsicht auf zwei benachbarte Finger einer Transistorvorrichtung mit isolierten anliegenden Bodykontakten.
• 9D zeigt eine schematische Darstellung der Transistorvorrichtung von 9A-9B.
• 10A stellt eine Grafik des Widerstands einer/s anliegenden Body-Verbindung (Kontakt) gegenüber Gate-Vorspannung und Body-Streifenbreite dar.
• 10B zeigt Diagramme, die den Drain-Source-Strom im ausgeschalteten Zustand von zwei Floating Body Transistoren und zwei Transistoren mit der anliegenden Body-Verbindung gemäß den verschiedenen Ausführungsformen der vorliegenden Offenbarung vergleichen.
• 11A und 11B zeigen Diagramme des Drain-Source-Stroms gegenüber der Drain-Source-Spannung von ansonsten identischen Transistorvorrichtungen mit der anliegenden Body-Verbindung gemäß den Ausführungsformen der vorliegenden Offenbarung und ohne Body-Verbindung.
• 12A-12C zeigen Diagramme, die den Einfluss der Anzahl von Body-Streifen eines Transistors mit anliegender Body-Verbindung gemäß der vorliegenden Erfindung auf das Ansprechen von Drain-Source-Strom gegenüber Drain-Source-Spannung einer identischen Transistorvorrichtung darstellen.
• 12D zeigt Diagramme, die die Ausgangskonduktanz gegenüber der Anzahl von Body-Streifen einer Transistorvorrichtung mit anliegender Body-Verbindung gemäß verschiedenen Ausführungsformen der vorliegenden Offenbarung darstellen.
• 13 zeigt eine Grafik, die den Einfluss der Injektion heißer Ladungsträger auf einen Floating Body Transistor darstellt.
• 14 zeigt eine Grafik, die den Einfluss der anliegenden Body-Verbindung gemäß der vorliegenden Erfindung in Bezug auf die Injektion heißer Ladungsträger darstellt.
• 15A und 15B zeigen Vergleichsdiagramme, die die Gate-Gesamtkapazität und die Drain-Gate-Kapazität eines identischen Transistors mit verschiedenen Body-Verbindungen und ohne Body-Verbindung darstellen.
• 16A-16B zeigen Vergleichsdiagramme, die den Einfluss der anliegenden Body-Verbindung gemäß der vorliegenden Erfindung auf die f_T und f_max Frequenzen eines Transistors darstellen.
• 17 zeigt Vergleichsdiagramme, die den Einfluss der anliegenden Body-Verbindung gemäß der vorliegenden Erfindung auf eine Nachbarkanal-Leckverhältnis-Leistung eines RF-Leistungsverstärkers darstellen.
• 18 zeigt Vergleichsdiagramme, die den Einfluss der anliegenden Body-Verbindung gemäß der vorliegenden Erfindung auf Verstärkung gegenüber Ausgangsleistung (Pout) für Transistoren bei identischer Vorspannung, mit relativ hoher Vorspannung, darstellen.
• 19 zeigt Vergleichsdiagramme, die den Einfluss der anliegenden Body-Verbindung gemäß der vorliegenden Erfindung auf Vorspannungsstrom (Ibias) für eine gegebene Ausgangsleistung eines RF-Leistungsverstärkers darstellen.
• 20A zeigt eine schematische Darstellung einer Kaskodenkonfiguration, die zwei gestapelte Transistoren aufweist.
• 20B zeigt eine schematische Darstellung einer Kaskodenkonfiguration, die drei gestapelte Transistoren aufweist.
• 21A zeigt eine anliegende Body-Verbindung gemäß einer Ausführungsform der vorliegenden Offenbarung, die an einem oberen Transistor T_B der in 20A dargestellten Kaskodenkonfiguration bereitgestellt ist, für einen Fall, bei dem die Transistoren der Kaskodenkonfiguration einen Finger haben.
• 21B und 21D zeigen raumeffiziente anliegende Body-Verbindungen gemäß Ausführungsformen der vorliegenden Offenbarung, die an einem oberen Transistor T_B der in 20A dargestellten Kaskodenkonfiguration vorgesehen sind, für einen Fall, bei dem die Transistoren der Kaskodenkonfiguration jeweils einen Finger haben.
• 21C und 21E zeigen Verfahren zum Herstellen eines Bodykontaktbereichs für die in 21B bzw. 21D abgebildeten anliegenden B ody-Verbindungen.
• 22 zeigt raumeffiziente anliegende Body-Verbindungen gemäß einer Ausführungsform der vorliegenden Offenbarung, die an dem oberen Transistor T_B der in 20A dargestellten Kaskodenkonfiguration vorgesehen sind, für einen Fall, bei dem die Transistoren der Kaskodenkonfiguration jeweils zwei Finger haben. 22 zeigt eine solche raumeffiziente anliegende Body-Verbindung, die an jedem Finger des oberen Transistors T_B vorgesehen ist.
• 23 zeigt raumeffiziente anliegende Body-Verbindungen gemäß einer Ausführungsform der vorliegenden Offenbarung, die an dem oberen Transistor T_E der in 20B dargestellten Kaskodenkonfiguration vorgesehen sind, für einen Fall, bei dem die Transistoren der Kaskodenkonfiguration jeweils zwei Finger haben. 23 zeigt eine solche raumeffiziente anliegende Body-Verbindung, die an jedem Finger des oberen Transistors T_E vorgesehen ist.
• 24 zeigt anliegende Body-Verbindungen gemäß einer Ausführungsform der vorliegenden Offenbarung, die an Fingern des oberen Transistors T_E der in 20B dargestellten Kaskodenkonfiguration vorgesehen ist, für einen Fall, bei dem die Transistoren der Kaskodenkonfiguration jeweils zwei Finger haben.
• 25 zeigt einen Abschnitt der in 20A dargestellten Kaskodenkonfiguration, wobei anliegende Body-Verbindungen gemäß 8B und 22 an den verschiedenen Fingern der Transistoren der Kaskodenkonfiguration vorgesehen sind.
• 26 zeigt einen Abschnitt der in 20B dargestellten Kaskodenkonfiguration, wobei anliegende Body-Verbindungen gemäß 8B, 22 und 23 an den verschiedenen Fingern der Transistoren der Kaskodenkonfiguration vorgesehen sind.
• 27 zeigt die Gesamtbreite der Struktur der in 20B dargestellten Kaskodenkonfiguration, wobei anliegende Body-Verbindungen gemäß 8B, 22, 23 und 24 an den verschiedenen Fingern der Transistoren der Kaskodenkonfiguration vorgesehen sind.
• 28 zeigt die Gesamtbreite der Struktur der in 20B dargestellten Kaskodenkonfiguration, wobei anliegende Body-Verbindungen gemäß 8B, 22, 23 an den verschiedenen Fingern der Transistoren der Kaskodenkonfiguration vorgesehen sind.
• 29A zeigt eine schematische Darstellung einer Kaskodenkonfiguration, die vier gestapelte Transistoren aufweist.
• 29B zeigt die Gesamtbreite der Struktur der in 29A dargestellten Kaskodenkonfiguration mit anliegenden Body-Verbindungen gemäß 8B, 22, 23 und 24, wobei die anliegenden Body-Verbindungen an dem obersten Transistor T_E der Kaskodenkonfiguration nur in Übereinstimmung mit der anliegenden Body-Verbindung von 24 sind.

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate one or more embodiments of the present disclosure and, together with the description of exemplary embodiments, serve to explain the principles and implementations of the disclosure.

• 1A shows a plan view of an N-type MOSFET transistor device.
• 1B shows a cross-sectional view along the line A of the transistor device in 1A ,
• 1C shows a schematic representation of the transistor device of 1A ,
• 2A FIG. 12 shows a top view of an N-type MOSFET transistor device having a T-gate body connection according to an embodiment of the prior art. FIG.
• 2 B shows a schematic representation of the transistor device of 2A ,
• 2C FIG. 12 shows a top view of an N-type MOSFET transistor device having an H-gate body connection according to an embodiment of the prior art. FIG.
• 3A FIG. 12 shows a plan view of an N-type MOSFET transistor device having a source-body connection according to an embodiment of the prior art. FIG.
• 3B shows a schematic representation of the transistor device of 3A ,
• 4A FIG. 12 shows a top view of an N-type MOSFET transistor having an applied body contact according to an embodiment of the present disclosure. FIG.
• 4B shows a cross-sectional view along the line B of the transistor device in 4A ,
• 5A FIG. 12 shows a top view of an N-type MOSFET transistor having an applied body contact according to another embodiment of the present disclosure. FIG.
• 5B shows a cross-sectional view along the line C of the transistor device in 5A ,
• 5C shows a schematic representation of the transistor device of 4A and 5A ,
• 6 FIG. 12 shows a plan view of an N-type MOSFET transistor having an applied body contact according to another embodiment of the present disclosure, wherein the body contact is made via a plurality of individual body stripes.
• 7A and 7B show plan views of other embodiments of in 6 shown embodiment.
• 8A FIG. 12 shows a top view of two adjacent fingers of a body contact type transistor device according to an embodiment of the present disclosure, wherein respective polysilicon strips are fabricated in a common source region. FIG.
• 8B shows another embodiment of the in 8A shown embodiment, wherein the corresponding polysilicon strips are connected.
• 8C-8H 12 show plan views of stacked transistors with adjacent body contacts in accordance with various embodiments of the present disclosure.
• 8I represents the stacked transistors of 8C and 8D schematically.
• 8J represents the stacked transistors of 8E schematically.
• 8K represents the stacked transistors of 8F schematically.
• 9A shows a plan view of a transistor with an isolated fitting body contact.
• 9B shows a cross-sectional view along the line F of the transistor device in 9A ,
• 9C shows a plan view of two adjacent fingers of a transistor device with isolated adjacent body contacts.
• 9D shows a schematic representation of the transistor device of 9A-9B ,
• 10A FIG. 4 illustrates a graph of the resistance of an attached body connection (contact) to gate bias and body stripe width. FIG.
• 10B 12 shows diagrams comparing the drain-source current in the off state of two floating body transistors and two transistors with the adjacent body connection according to the various embodiments of the present disclosure.
• 11A and 11B 12 show graphs of drain-source current versus drain-source voltage of otherwise identical transistor devices with the adjacent body connection in accordance with the embodiments of the present disclosure and without body connection.
• 12A-12C 12 are diagrams illustrating the influence of the number of body stripes of a body-connected transistor according to the present invention on the drain-source current vs. drain-source voltage response of an identical transistor device.
• 12D 12 shows diagrams illustrating the output conductance versus the number of body stripes of a body-connected transistor device according to various embodiments of the present disclosure.
• 13 shows a graph illustrating the influence of the injection of hot carriers on a floating body transistor.
• 14 FIG. 10 is a graph illustrating the influence of the applied body connection according to the present invention with respect to hot carrier injection. FIG.
• 15A and 15B Figure 9 shows comparison diagrams illustrating the total gate capacitance and the drain-gate capacitance of an identical transistor with different body connections and no body connection.
• 16A-16B Figure 9 shows comparison diagrams illustrating the influence of the applied body connection according to the present invention on the f _T and f _max frequencies of a transistor.
• 17 FIG. 10 shows comparison diagrams illustrating the influence of the applied body connection according to the present invention on adjacent channel leakage power of an RF power amplifier. FIG.
• 18 Figure 9 shows comparison diagrams illustrating the influence of the applied body connection according to the present invention on gain versus output power (Pout) for identical bias transistors, with relatively high bias voltage.
• 19 FIG. 11 shows comparison diagrams illustrating the influence of the applied body connection according to the present invention on bias current (Ibias) for a given output power of an RF power amplifier.
• 20A shows a schematic representation of a cascode configuration having two stacked transistors.
• 20B shows a schematic representation of a cascode configuration having three stacked transistors.
• 21A FIG. 12 shows an abutting body connection according to an embodiment of the present disclosure applied to an upper transistor T _B of FIG 20A cascode configuration is provided for a case where the transistors of the cascode configuration have a finger.
• 21B and 21D show space-efficient abutting body connections according to embodiments of the present disclosure which are connected to an upper transistor T _B of FIG 20A shown cascode configuration are provided for a case in which the transistors of the cascode configuration each have a finger.
• 21C and 21E show methods of making a body contact area for the in 21B respectively. 21D pictured adjacent B ody connections.
• 22 FIG. 12 shows space efficient abutting body connections according to an embodiment of the present disclosure applied to the upper transistor T _B of FIG 20A cascode configuration are provided for a case in which the transistors of the cascode configuration each have two fingers. 22 shows such a space-efficient fitting body connection, which is provided on each finger of the upper transistor T _B.
• 23 FIG. 10 shows space-efficient abutting body connections according to an embodiment of the present disclosure, which are connected to the upper transistor T _E of FIG 20B cascode configuration are provided for a case in which the transistors of the cascode configuration each have two fingers. 23 shows such a space-efficient fitting body connection, which is provided on each finger of the upper transistor T _E.
• 24 FIG. 12 shows abutting body connections according to an embodiment of the present disclosure applied to fingers of the upper transistor T _E of FIG 20B cascode configuration is provided for a case in which the transistors of the cascode configuration each have two fingers.
• 25 shows a section of in 20A illustrated cascode configuration, wherein fitting Body connections according to 8B and 22 are provided on the various fingers of the transistors of the cascode configuration.
• 26 shows a section of in 20B illustrated cascode configuration, wherein fitting Body connections according to 8B . 22 and 23 are provided on the various fingers of the transistors of the cascode configuration.
• 27 shows the overall width of the structure of 20B illustrated cascode configuration, wherein fitting Body connections according to 8B . 22 . 23 and 24 are provided on the various fingers of the transistors of the cascode configuration.
• 28 shows the overall width of the structure of 20B illustrated cascode configuration, wherein fitting Body connections according to 8B . 22 . 23 are provided on the various fingers of the transistors of the cascode configuration.
• 29A shows a schematic representation of a cascode configuration having four stacked transistors.
• 29B shows the overall width of the structure of 29A shown cascode configuration with adjacent body connections according to 8B . 22 . 23 and 24 , wherein the adjacent body connections to the uppermost transistor T _{E of} the cascode configuration only in accordance with the adjacent body connection of 24 are.

DETAILED DESCRIPTION

Throughout this description, embodiments and variations are described for the purpose of illustrating uses and implementations of the inventive concept. The illustrative description should be construed as representing examples of the inventive concept rather than as limiting the scope of the presently disclosed concept.

The present disclosure describes devices that provide all the advantages of conventional body-connected semiconductor devices, such as H-gate and L-gate MOSFET devices, without the limitations and degradation associated with these designs. Methods of making and using such devices are also described.

An abutting body contact in a semiconductor device, according to various embodiments of the present disclosure, may improve the performance of the semiconductor device. As used herein, the terms "in-body contact," "on-body connection," and "on-body-on-body" terms are equivalent and refer to the various methods and apparatus for providing a body connection for a semiconductor device according to the present disclosure, which are described in the following paragraphs with the assistance of the various corresponding figures. In an exemplary case of a transistor device, such an applied body connection may be provided by connecting, via a conduction path of a desired conductivity (e.g., resistivity), a body region of the transistor device to a source region of the transistor device. Alternatively, the adjacent body connection may be provided as an open contact to connect the body region of the transistor device to any desired external potential provided at the open contact, wherein the open contact becomes resistive to the body region of the transistor via a conduction path of desired conductivity Transistor device is connected.

An abutting body connection according to various embodiments of the present disclosure may be implemented by providing some additional structures for the semiconductor device, such as a body-strip, denoted by the reference numeral (FIG. 512 ) from 5B is illustrated, a "polysilicon strip" by the reference symbol ( 510 ) from 5A and a "body contact area" represented by the reference numeral ( 540 ) from 5A and 5B is illustrated. Such structures, and any others relating to the implementation of the adjacent body connection in accordance with the present disclosure, are further described in the following paragraphs.

In the present application, a body strip (eg, reference numeral 512 ) from 5B ) a region that has the same doping type as a body region (eg reference symbol ( 112 ) from 5B under a gate polysilicon structure (eg reference symbol ( 110 ) from 5A-5B ) of a semiconductor device (ie, transistor body, transistor channel, transistor conduction channel) branched from and contiguous with the body region under the gate polysilicon structure of the semiconductor device, and extending to or through a source region (eg, reference numeral 120 ) in 5A-5B ) or a drain region of the semiconductor device. In an exemplary embodiment of the present disclosure, such a body strip may be provided with a corresponding polysilicon stripe (eg, reference numeral 510 ) from 5A ), which branches off from the gate polysilicon structure of the device, and may therefore be an integral part of the gate polysilicon structure. The polysilicon stripe is used as a mask to prevent doping of a semiconductor region below the polysilicon stripe and therefore to create the body stripe.

In the present application, a body contact area (eg, reference numeral 540 ) in 5A-5B ) an area with the same doping type as the body area (eg reference symbols ( 112 ) from 5B ) used to provide a low resistivity conductive path to a desired potential to be applied to the body region of the device. Therefore, the body strip (eg reference numeral 512 ) from 5B ) a conduction path between the body region and the body contact region with a first resistivity (eg R1 of 5C ), and the body contact region provides a conduction path to a desired body connection potential with a second resistivity (eg, R2 of 5C ) ready.

As illustrated in the following sections of the present disclosure, an abutting body contact according to various embodiments of the present disclosure be provided by one or more body strips are connected to a body portion of the device. According to various embodiments of the present disclosure, which will be described later, such a body strip makes contact with a body contact region having the same doping type as the body region under the gate polysilicon structure. According to various embodiments of the present disclosure, the doping of the body contact region may have an associated concentration that is similar to, lower, or higher than an associated doping concentration of the body region. According to various embodiments of the present disclosure, which will be described later, the body contact region may be fabricated in the source region adjacent to the gate polysilicon structure, or may be fabricated in regions adjacent to the source region adjacent to the gate polysilicon structure. Other implementations where the body contact region is in a drain region of the semiconductor device are also possible.

The presently described embodiments are illustrated by an N-type MOSFET device. Persons of ordinary skill in the art will readily apply the presently disclosed inventive concepts to other types of semiconductor devices, such as a P-type MOSFET device, by using other types of doping, if desired. The embodiments according to the present invention may also be applied to extended drain devices, such as laterally diffused metal oxide semiconductor (LDMOS) devices and other gate transistors or devices.

Semiconductor-applied-body contact devices according to various embodiments of the present disclosure may include semiconductor devices formed on silicon-on-insulator (SOI) including field effect transistors (FET). The FET devices may include Complementary Metal Oxide Semiconductor (CMOS), Metal Oxide Semiconductor Field Effect Transistor (MOSFET), and other types of field effect transistor (FET) devices. The silicone-on-insulator (SOI), in one embodiment, may include silicone-on-sapphire (SOS).

As used herein, MOSFET p-body (eg, reference numeral 112 ) from 5B ), P-body, P-body region and body region on the P-doped silicon under the gate polysilicon structure (eg reference symbol ( 110 ) from 5A-5B ), which in operation provides a duct to the MOSFET. The body area and the body strip (eg reference symbol ( 512 ) from 5B ) generate a contiguous P-doped region under the gate polysilicon structure and the polysilicon stripe (eg, reference symbols ( 510 ) from 5A-5B ).

In one embodiment according to the present disclosure, the P-doped silicon is under a distal end of the polysilicon strap (body remote from the gate polysilicon structure) with a P + doped region of the semiconductor device (body contact region) in contact. As mentioned above, such is one P + doped region defining the body contact region, a region of the same doping type as the body region under the gate polysilicon structure and may have any doping concentration and is not one P + Doping limited.

In an exemplary embodiment according to the present disclosure, the body contact region may be in square or rectangular shape. As will be described later in Sections of the present disclosure, the body contact region may provide a low resistivity conductive path to a desired body interconnect potential via a metal contact or via a low resistivity layer on top of the contact region, such as a silicide layer. Further, the body contact region may either be in contact with a source region of the semiconductor device to provide a source-body connection, or be isolated from each active region (eg, source / drain regions) of the device, to provide any potential for the body (decoupled from the source potential).

In an embodiment according to the present disclosure, a plurality of polysilicon strips may be provided for the same gate polysilicon structure (branching from the gate polysilicon), with a corresponding body strip (FIG. P- doped region below a polysilicon stripe) with another and separate body contact region (eg 7A , described later).

In another embodiment according to the present disclosure, a plurality of polysilicon strips are provided for the same gate polysilicon, and corresponding body strips may be connected to a same contiguous body contact region (eg 7B , described later).

In an embodiment according to the present disclosure, the body strip contacts the body contact area at the distal end of the body strip away from the body region of the gate.

In one embodiment in accordance with the present disclosure, the MOSFET transistor has a plurality of fingers with an associated plurality of gate polysilicon structures, wherein a corresponding polysilicon strip is connected to each gate polysilicon structure (eg 8A-8B , described later).

In yet another embodiment of the present disclosure, body stripes corresponding to polysilicon gates of adjacent fingers may be associated with a similar one P + doped area (eg 8B , described later).

In yet another embodiment of the present disclosure, polysilicon strips branching from polysilicon gates of adjacent fingers may be connected (eg 8B , described later).

According to some embodiments of the present disclosure, the body contact region, which is connected to the distal end of a body strip (away from the body region), is generated in a source region of the MOSFET transistor, whereby in the N + doped source region P + doped region is generated. In accordance with yet another embodiment of the present disclosure, such a body contact region is created in a region adjacent to and in contact with the source region of the MOSFET transistor. It should be noted that although the body contact area as P + doped region, this should not be considered as limiting the scope of what the inventors consider to be their invention, because different doping levels of the body contact region, including doping similar to doping of the body region, may also be used in the present body contact invention ,

Further specification of the above embodiments of the present disclosure will be made in the following sections of the present disclosure with reference to the accompanying drawings.

1A shows a top view of an SOI MOSFET device ( 100 ) of the N type. A gate finger ( 110 ) is located between a source area ( 120 ) and a drain region ( 130 ). The gate finger ( 110 ) has a length L _G and a width W _G , In one aspect, the gate finger may be over a polysilicon structure ( 110 ), which can block the implantation of dopant ions used to dope the adjacent source and drain regions of the MOSFET. It is well known to those of ordinary skill in the art that a multi-finger SOI device may have a plurality of such fingers, each finger having a corresponding gate polysilicon structure (FIG. 110 ), a drain region ( 130 ) with corresponding drain contacts ( 155 ) and a source area ( 120 ) with corresponding source contacts ( 145 ). In some embodiments, adjacent fingers may share a corresponding drain and / or source region.

1B FIG. 12 shows a cross-sectional view of the N-type SOI MOSFET device (FIG. 100 ) along the line A from 1A , In one aspect, the gate polysilicon structure ( 110 ) over an insulating gate silicon oxide layer ( 115 ) lying down. In one aspect, the body area ( 112 ) under the gate polysilicon structure ( 110 ) doped with a P-type dopant (P-body) and the source ( 120 ) and drain areas ( 130 ) are strongly doped with an N-type dopant ( N + ) implanted. As in the cross-sectional view of 1B shown are areas ( 112 . 120 . 130 ) of the SOI MOSFET device on top of a buried oxide (BOX) layer ( 150 ) prepared on a semiconductor substrate ( 160 ) is formed, and therefore is in the in 1A and 1B represented SOI MOSFET due to the insulating nature of the BOX layer ( 150 ) no conduction path between the areas ( 112 . 120 . 130 ) and the semiconductor substrate (body). Experts readily know that the areas ( 112 . 120 . 130 ) of the SOI MOSFET device ( 100 ) in a thin layer of silicon ( 180 ) can be formed above the insulating layer ( 150 ), whereby such areas ( 112 . 120 . 130 ) through the depth of the thin layer of silicon ( 180 ) to the insulating layer ( 150 ). Accordingly, and as known in the art, the SOI MOSFET device ( 100 ) are referred to as a thin-film SOI-MOSFET, wherein thin film is deposited on the thin layer of silicon ( 180 ). It should be noted that the various embodiments according to the present disclosure described below may be implemented in thin film SOI MOSFET devices.

In the 1A and 1B illustrated SOI MOSFET device ( 100 ) does not provide a body connection which, as is known to those skilled in the art, is a connection between the P-body and a (fixed) reference potential, for example the source region of the device. Such an SOI device used in 1C is a floating body device and is therefore susceptible to the disadvantages discussed in the above sections of the present disclosure.

2A shows a plan view of an N-type MOSFET transistor ( 200 ) having a T-gate body connection structure according to a Embodiment of the prior art. At the in 2A In the illustrated embodiment of the prior art, the gate polysilicon structure ( 110 ) so that it has a structure ( 210 ) having the conventional structure ( 110 ), which is used to connect a conduit (ie body region, channel region) of the device ( 200 ). Accordingly, the T-shaped polysilicon structure ( 110 . 210 ) the formation of a corresponding P-body region below the polysilicon, with a P + Area ( 240 ) is in contact, wherein the P + Area ( 240 ) a contact with low resistivity with the P- Area under the polysilicon widening area ( 210 ) and thus with the transistor body below the polysilicon region ( 110 ). The P-body region below the polysilicon region ( 210 ) also allows the isolation of the source area ( 120 ) and the drain region ( 130 ) with regard to the highly-doped area ( 240 ). Those skilled in the art will appreciate that the T-gate body interconnect structure of the transistor with body connection ( 200 ) of the prior art allows the P + region ( 240 ) is in electrical contact with a constant voltage node to provide a floating charge conduction path in the channel region of the transistor ( 200 ). According to some implementations, the P + Area ( 240 ) may be in contact with an overlying metal layer which may be connected to a constant voltage. Such a constant voltage may be a voltage applied to a source of the transistor, or a reference potential such as ground, or a fixed (negative) voltage. Professionals will understand that in 2A illustrated plan view of a simplified plan view of the transistor ( 200 ), because only the structures / elements relevant to the description of the embodiment (prior art) are shown. Those skilled in the art will understand that other structures / elements, such as drain / source contacts, have been omitted from the figure for clarity. In general, this approach also applies to the reproduction of the various figures which are part of the present invention.

Those in the N-type transistor ( 200 ) used T-gate body connection structure in the transistor ( 100 ) from 1A reduce existing floating body effects. However, the T-gate body connection allows, via the extended polysilicon structure ( 210 ) adjacent to the drain and source regions ( 130 . 120 ), additional parasitic capacity ( C _SG ) between the gate and the source of the transistor ( 200 ), as well as additional parasitic capacity ( C _DG ) between the gate and the drain of the transistor ( 200 ). Such parasitic capacities ( C _SG . C _DG ) have no constant capacitance value because their value may change depending on the voltage applied to the transistor terminals. The said parasitic capacities ( C _SG . C _DG ) are in 2 B (as variable capacities). 2 B schematically shows the transistor ( 200 ) including the body contact that allows connection to a desired potential. Those skilled in the art will readily recognize the adverse effects of such parasitic capacitances on the performance of the transistor ( 200 ), which among other things reduce the switching speed of the transistor and the characteristic operating frequencies f _T and f _max of the transistor ( 200 ) using the T-Gate Body connection. Due to the non-constant nature of parasitic capacitances ( C _SG . C _DG ), such capacitances can also increase the linearity of the transistor ( 200 ) of the prior art adversely affect.

Alternative implementations of the T-Gate Body connection, which are known to those skilled in the art, for example, the H-gate body connection, which in 2C also provide the advantage of reducing floating body effects, but at the expense of additional parasitic capacitances that increase the RF performance of the device (eg, lower parasitic capacitance) f _T and f _max ) can worsen. The embodiment of the prior art H-gate body interconnect disclosed in U.S. Pat 2C has the advantage, in cases where the transistor has a large width ( W _G ) to provide a more efficient (eg symmetric) body connection at the expense of additional parasitic capacitances ( C _SG . C _DG ) and the associated negative influence, as explained for the case of the T-Gate Body connection. However, for large transistor widths, neither the H-gate nor the T-gate can provide efficient body connection for the transistor because providing body connections at the distal ends of the transistor channel will result in higher resistance in the middle of the channel width.

3A shows a plan view of an N-type MOSFET transistor ( 300 ) with a source-body connection according to an embodiment of the prior art. At the in 3A illustrated embodiment of the prior art, a body contact by adding a P + Area ( 340 ) in the source area ( 120 ) providing the P-body region under the gate polysilicon structure ( 110 ) with the source area ( 120 ) connects. In other words, the P + range ( 340 ) has a low resistance path between the source region ( 120 ) and the P-body region under the gate polysilicon structure ( 110 ), as shown schematically in 3B is shown.

As in the case of the T-Gate Body connection structure of 2A may be that in the N-type transistor ( 300 ) from 3A used source-body connection structure in the transistor ( 100 ) from 1A existing floating body effects to reduce. Moreover, the fact that the gate polysilicon structure ( 110 ) is not expanded, as provided in the T-gate (and H-gate) structure, by the source-body connection structure of 3A no additional parasitic capacitance provided.

The area ( 340 ) in 3A must the source area ( 120 ) with the P-body region leading to the gate polysilicon structure ( 110 ), and therefore the area ( 340 ) have a non-zero overlap (Δ) with the P-body region (see the document entitled "MITTL Low-Power FDSOI CMOS Process", revision 2006: June 1) 2006 from MIT Lincoln Laboratory, which is hereby incorporated by reference in its entirety). Such an overlap may affect the characteristics of the conduction channel of the transistor ( 300 ) locally change in the region in which the overlap takes place and can therefore adversely affect the power of the transistor, for example non-linear response (eg IV characteristic) of the transistor ( 300 ).

The construction of the source-body connection, as used in the embodiment of the prior art 3A may also result in additional manufacturing complexity, including the adaptation of the P + Area ( 340 ) with respect to the gate polysilicon region ( 110 ). Precision associated with the latter adjustment step can directly affect the linearity of the transistor as well as the IV characteristic of the transistor as a result of possible matching variations and also affect the cost and result of manufacturing such a transistor.

4A shows a plan view of an N-type MOSFET transistor ( 400 ) with an attached body contact according to an embodiment of the present disclosure. According to an embodiment of the present disclosure, the MOSFET transistor device (FIG. 400 ) may be a thin-film SOI device having active regions (eg 120 . 130 ) formed in a thin layer of silicon ( 180 in 4B ) are formed over an insulating layer ( 150 in 4B ), wherein the active regions extend through the depth of the thin layer of silicon to the insulating layer. The transistor ( 400 ) has a polysilicon strip ( 410 ) derived from the gate polysilicon structure ( 110 ) through the source region ( 120 ) branches off and over the source region ( 120 ) to a body contact area ( 440 ) adjacent to the source region ( 120 ). Because the polysilicon strip ( 410 ) one with the gate polysilicon structure ( 110 ) is contiguous structure (eg forming a single structure), a corresponding body strip is formed underneath the polysilicon strip ( 410 ) having the same type (doping) as the P-body region below the gate polysilicon structure ( 110 ) (since the polysilicon strip ( 410 ) prevents the implantation of N + into the P-body during an implantation phase which, for example, with the doping of the adjacent drain ( 130 ) and source areas ( 120 )). As in 4B is shown, such a body strip connects the P-body region below the gate polysilicon structure (FIG. 110 ) with the body contact area ( 440 ) (in 4A-4B when P + Area) adjacent to the source area ( 120 ). According to various embodiments of the present disclosure, the body contact region has the same type of doping as the P body region, either at the same concentration (eg P- ) or a higher concentration (eg P + ) compared to the concentration of the P-body area.

With further reference to 4A-4B can during the operation of the transistor ( 400 ) the body contact area ( 440 ) and the body strip ( 412 ) a conduction path for carriers between the transistor body ( 112 ) and the N + Source area ( 120 ) which provides the termination extraction node for the previously in the transistor body ( 112 ) provides potential-free charge.

4B 3 shows a cross-sectional view of the N-type MOSFET transistor (device) (FIG. 400 ) with adjacent body contact according to the in 4A shown embodiment of the present invention, along the line B of 4A , As in the cross-sectional view of 4B is shown, the transistor body region ( 112 ) below the gate polysilicon structure ( 110 ) with the P-body area ( 412 ), which is referred to herein as a body strip and is formed below the polysilicon strip, contiguous. A cross-sectional view of the transistor ( 400 ) along the line A from 4A is in the previously explained 1B to see.

5A shows a plan view of an N-type MOSFET transistor ( 500 ) with adjacent body contact according to another embodiment of the present disclosure. The transistor ( 500 ) has a polysilicon strip ( 510 ) derived from the gate polysilicon structure ( 110 ) into the source area ( 210 ) branches off and into one P + Area ( 540 ), the body contact region extending in the source region ( 120 ) is trained. Because the polysilicon strip ( 510 ) one with the gate polysilicon structure ( 110 ) is a contiguous structure, a corresponding body stripe below the polysilicon stripe ( 510 ) having the same type (doping) as the P-body region below the gate polysilicon structure ( 110 ). As in 4B is shown, such a body strip connects the P-body region below the gate polysilicon structure (FIG. 110 ) with the in the source area ( 120 ) trained body contact area ( 540 ).

5B FIG. 12 shows a cross-sectional view of the N-type MOSFET transistor (device) with body contact applied in accordance with FIG 5A shown embodiment of the present disclosure, along the line C from 5A , As in the cross-sectional view of 5B is apparent, the body area ( 112 ) below the gate polysilicon structure ( 110 ) with the underneath the polysilicon strip ( 510 ) trained P-body area ( 512 ) (Body stripes) connected. Furthermore, the body strip ( 512 ) at a distal end of the body strip ( 512 ) in the source area ( 120 ) trained body contact area ( 540 ). A cross-sectional view of the transistor ( 500 ) along the line A from 5A is in the above-explained 1B seen.

As is known to those skilled in the art, at the top of exposed silicon regions of a semiconductor device, a low resistivity layer, such as a silicide layer, may exist. Such a low resistivity layer may provide a low resistance conduction path between all points of the underlying silicon region. With reference to 5B For example, a continuous silicide layer (not shown) may be placed on top of the areas (FIG. 120 ) and ( 540 ), a conduction path with low resistivity between arbitrary points of the two adjacent regions ( 120 ) and ( 540 ) provide.

With further reference to 4A-5B can the body strip ( 412 . 512 ) of transistors ( 400 . 500 ) according to the in 4A and 5A 1, a first resistive (conduction) path between the body region (FIG. 112 ) and the body contact area ( 440 . 540 ), and a low resistivity continuous layer, such as a silicide layer, on top of the body contact area (FIG. 440 . 540 ) and the source area ( 120 ) may deposit a second resistive path between the body strip ( 412 . 512 ) and the source area ( 120 ) provide. Those skilled in the art will readily understand that based on the type of doping and the concentration of these regions, a resistance ( R1 ), which belongs to the first resistive path, can be substantially larger than a resistance ( R2 ) belonging to the second resistive path. 5C is a schematic representation of the N-type MOSFET transistor ( 400 . 500 ), whereby the body strip ( 412 . 512 ) and the body contact area ( 440 . 540 ) a resistive compound (first and second resistive paths with equivalent resistance R1 respectively. R2 ) between the body and the source of the transistor. Such a resistive compound is characterized by the resistance R (= R1 + R2) of 5C shown connecting the source S and the body of the transistor.

The second resistive path between the body stripe ( 412 . 512 ) and the source area ( 120 ) can be provided by a method other than the above-mentioned conductive (silicide layer). In accordance with one embodiment of the present disclosure, metal contacts associated with the various regions may be used to provide the second resistive path. A metal contact on top of the body area ( 440 . 540 ) can, for example, via a metal to a metal contact ( 145 ) on top of the source area ( 120 ), thereby creating the second path with low resistivity.

With further reference to 5C In some cases, it may be desirable to have a different value of resistance R provide for a desired effect of the provided body connection. Because the resistance R2 provided by the second resistive path compared to the resistance provided by the first resistive path R1 is very small (essentially zero), it can not be used to resist the resistance R to change significantly. According to various embodiments of the present disclosure, different resistance values of the resistor R be provided by adding a value of resistance R1 via parameters of the body strip ( 412 . 512 ) is set.

According to an embodiment of the present disclosure, the resistance value of the resistor R1 in 5C , and thus the resistance R , across the width and / or the length of the polysilicon strip ( 410 . 510 ) leading to the body strip ( 412 . 512 ) can be adjusted. Those skilled in the art will understand how to change the width and / or length of the polysilicon strip ( 410 . 510 ), whereby accordingly also the width and / or the length of the body strip ( 412 . 512 ), the resistance is modified R1 and thus the resistivity of the first resistive path (between the area ( 112 ) and the area ( 540 ) can change.

According to another embodiment of the present disclosure, the number of polysilicon strips ( 410 . 510 ) are greater than one for a given gate polysilicon structure, for example two, three, four or more (eg 6-7B , described later). The relative spacing of the polysilicon strips may be combined with the width and / or length of the polysilicon strips (FIG. 410 . 510 ) can be used to calculate the resistance value R1 the resistive path between the body area ( 112 ) and the body contact area ( 440 . 540 ) and thus the resistance of the resistor R adjust.

According to another exemplary embodiment of the present disclosure the polysilicon strips ( 410 . 510 ) are produced in a manufacturing step different from that used for producing the gate polysilicon structure ( 110 ) is used. While such an exemplary embodiment may make the overall manufacturing process complex, this is one possible alternative embodiment for providing the abutting body contact of the present invention.

With further reference to 4A and 5A Those skilled in the art will appreciate the reduction in parasitic capacitance achieved by the embodiments of the present disclosure as compared to the prior art embodiments of FIG 2A provided. In contrast to such an embodiment of the prior art, the embodiments of the present disclosure do not introduce a parasitic gate-drain capacitance C _DG one. In addition, due to the relatively small dimensions (width and / or length) of the polysilicon strip ( 410 . 510 ) compared to the polysilicon region ( 210 ) of the embodiment of the prior art of 2A , the parasitic gate-source capacitance C _SG the embodiments according to the present disclosure, which are incorporated in 4A and 5A shown are smaller than that C _SG the embodiment of the prior art of 2A ,

According to some embodiments of the present disclosure, the polysilicon strip ( 410 . 510 ) an integral element of the gate polysilicon structure ( 110 ) and using the same mask. Since the polysilicon strip is an integral element of the gate polysilicon structure ( 110 ), fitting problems in producing the polysilicon strip ( 410 . 510 ) and associated body strips ( 412 . 512 ) with respect to the gate polysilicon ( 110 ) and the associated P-Bodys ( 112 ), as is the case for the 3A shown in the prior art transistor is eliminated. Those skilled in the art will appreciate the elimination of such an adjustment step and the simpler manufacturing process that the presently described method of applied body connection with respect to the prior art embodiment of prior art discussed above 3A providing, appreciate.

As noted in the above paragraphs of the present disclosure, the abutting body connection according to the various embodiments of the present disclosure, as disclosed in, for example, US Pat 4A-5C the advantages of a simpler manufacturing process, adjustable body connection impedance (eg, resistance) and reduced parasitic capacitance compared to embodiments of a prior art body connection (eg 2A . 3A ). As a result, integrated circuits employing transistor devices with the adjacent body connection according to the present invention may outperform integrated circuits having similar functions using transistor devices without body connection or body connections according to embodiments of the prior art. Comparative data graphs showing further performance advantages of the abutting body contact (joint) according to the present invention are shown in FIG 10A-19 shown later.

As noted in the above paragraphs, in accordance with some embodiments of the present disclosure, the adjacent body connection may be provided over more than one polysilicon strip with a gate polysilicon of a transistor. Such an embodiment according to the present disclosure is in 6 shown which an extension of in 4A shown embodiment. As in 6 is shown, a plurality of polysilicon strips ( 610 ) of the gate polysilicon structure ( 110 ) through the source region ( 120 ) to form a single polysilicon structure and extends across the source region (FIG. 120 ) to the body contact area ( 440 ), which is in 6 is indicated as P + region, adjacent to the source region ( 120 ). Such individual polysilicon strips ( 610 ) in turn allow the formation of respective single body stripes that provide a resistive conduction path between the P-body under the gate polysilicon structure (FIG. 110 ) and the body contact area ( 440 ), and therefore to the source area ( 110 ), provide. The cross-sectional view of the N-type MOSFET transistor ( 600 ) along the in 6 shown lines A and B is in the 1B respectively. 4B shown. When the transistor width W _G is large, then multiple polysilicon strips ( 610 ) be desired. Although at the in 6 In accordance with an exemplary embodiment of the present disclosure, the individual polysilicon strips have a common contiguous body contact area (FIG. 440 ), according to alternative embodiments of the present disclosure, such a body contact region may include one or more individual and separate ones P + Have areas, each such P + Area the source area ( 120 ) is adjacent. Those skilled in the art will readily understand how such alternative embodiments are based on the principles of the art 6 shown exemplary embodiment of the structural design can be derived. It should be noted that the polysilicon strips ( 610 ) along the width of the body area (as through W _G defined) in accordance with desired design goals of the transistor with applied body connection ( 600 ) from 6 can be positioned. According to an exemplary embodiment of the present disclosure, the polysilicon strips ( 610 ) is placed symmetrically along the width of the body region, as in 6 with the polysilicon strips ( 610 ) with respect to a center line (in 6 denoted by B) of the width of the body region are arranged symmetrically. According to another exemplary embodiment of the present disclosure, the polysilicon strips ( 610 ) are equally spaced along the width of the body region, as in FIG 6 wherein the distance between any two arbitrary successive polysilicon strips ( 610 ) along the width W _G is constant.

Similar to the in 6 The embodiment shown in FIG 5A shown embodiment of the present body connection according to the present disclosure to more than one polysilicon strip ( 510 ) provided by the gate polysilicon structure ( 110 ) branches off. As in 7A can be shown, each such polysilicon strip ( 510 ) an area in the source area ( 120 ), the one P + Contains a region which leads to a body contact region ( 540 ) belongs. According to the in 7A Illustrated exemplary embodiments of the present disclosure may include such body contact areas (FIGS. 540 ) individually and separately and in a one-to-one relationship with each polysilicon strip ( 510 ) are present. According to other embodiments of the present disclosure, the P + Areas that belong to the individual body contact areas ( 540 ) belong to one or more larger ones P + Areas ( 540 ), each as body contact area for more than one polysilicon strip ( 510 ) can be used as in 7B is shown.

As already mentioned, the gate polysilicon ( 100 ) May be part of a finger of a larger device, such device having a plurality of such fingers. Each such finger may be part of a separate transistor that forms the larger device in combination with other transistors. The larger device may include a plurality of transistors connected in series or in parallel, or a combination thereof. As is known to those skilled in the art, in some cases adjacent fingers may have the same contiguous source region. According to an embodiment of the present disclosure, one, more than one, or all of the fingers of the larger device may have an adjacent body connection structure per structural configuration 4A-7B to have.

8A 1 shows an embodiment according to the present disclosure in which two adjacent fingers of a transistor device form a common source region (FIG. 120 ) share. Each finger has a corresponding gate polysilicon structure ( 110 ) with an associated length of L _G1 respectively. L _G2 that may be equal to each other in some embodiments. Each gate polysilicon structure ( 110 ) can form a corresponding polysilicon strip ( 510 ) derived from the gate polysilicon structure ( 110 ) into the common source area ( 120 ) branches off and becomes a body contact area ( 540 ), wherein said body contact area in some example embodiments P + Area is. In the 8A An exemplary embodiment shown in accordance with the present disclosure shows a polysilicon strip (FIG. 510 ) per gate polysilicon structure ( 110 ) located at a distal end of the polysilicon strip ( 510 ) into the body contact area ( 540 ) passes over. Such limitation should not be construed as limiting what the present inventors consider to be their invention, but rather as an exemplary embodiment of the invention. As in the paragraphs above and in relation to 4A-7B In accordance with the present disclosure, many different structural arrangements for on-contact body contact are possible and will be apparent to those skilled in the art based on the teachings of the present disclosure. In one embodiment, for example, the body contact areas ( 540 ) at the same distance from a corresponding gate polysilicon structure ( 110 ) are located. In another embodiment, the body contact areas ( 540 ) with respect to corresponding gate polysilicon structures ( 110 ) be arranged at different distances.

It may be desirable to use the gate polysilicon structures ( 110 ) from two adjacent fingers. This is typically done by extending and connecting the gate polysilicon structures outside the active region of the device (eg, regions that are separate from the drain and source regions of the device). According to an embodiment of the present disclosure, two adjacent gate polysilicon structures may be connected via a common polysilicon stripe between the two adjacent polysilicon structures, as in FIG 8B is shown. At the in 8B In the embodiment shown, the two gate polysilicon structures ( 110 ), each of which has associated gate lengths, with L _G1 and L _G2 over a polysilicon strip ( 510 ), the two structures ( 110 ) is common. This may enable, for example, a gate voltage provided at a gate contact belonging to a gate polysilicon structure to be supplied to an adjacent gate, and thus allows a simpler and smaller gate-polysilicon overall structure.

The common polysilicon strip ( 510 ) according to the in 8B illustrated exemplary embodiment of the present disclosure may, via its connection to the body contact area ( 540 ), an appealing body connection for both in 8B provide transistor devices while the corresponding gate polysilicon structures (FIG. 110 ) as described above. The mechanism for providing the adjacent body connection in the in 8B The illustrated embodiment is similar to one with reference to 4A-7B described mechanism in which a body stripe leading to the polysilicon strip ( 510 ), the P -Bodybereich underneath the gate polysilicon with the common source region ( 120 ) via the body contact area ( 540 resistively connects, the latter region, as described above, a (second) conduction path with low resistivity to the source region ( 540 ). It should be noted that although the P + Area ( 540 ) in 8B centrally between the two gate polysilicon structures ( 110 ), the location of such an area may vary depending on the desired body connection performance requirement for each of the two 8B shown devices can be varied. Similarly, the width of a segment of the polysilicon strip may be between the body contact region (FIG. 540 ) belonging to a gate polysilicon structure may be different in width from one segment belonging to the other gate polysilicon structure.

At the in 8A-8B 1, according to the present disclosure, the adjacent fingers may be associated with their respective gate lengths L _G1 and L _G2 Be part of the same device or of two separate devices. According to another embodiment of the present disclosure, the adjacent fingers may correspond to fingers of separate devices that are electrically connected, for example, in a cascode configuration. In such a cascode configuration as in 8C-8K As shown, the source of a first device is electrically connected to the drain of a second (last) device. Although the in 8C-8E and 8I-8J For example, although the illustrated configuration of the present disclosure uses two cascode transistor devices, it will be understood by those skilled in the art that stack sizes greater than two, such as three, four, five,..., ten or more stacked devices, are possible as well 8F and 8K is shown.

8C FIG. 12 is a top view of the cascode configuration with body connection (800C) in accordance with the present disclosure incorporated in FIG 8I is shown schematically. It should be noted that the in 8I schematically illustrated upper transistor of in 8C corresponds to the first device represented by the associated gate length L _G1 is identified while in the 8I schematically illustrated lower transistor of in 8C represented second device, by the associated gate length L _G2 is identified. How out 8C shows that the source area ( 120 ) of the first device, by the associated gate length L _G1 is represented with the drain region ( 130 ) of the second device, by the associated gate length L _G2 is represented in common, whereby these source and drain regions are electrically connected.

As in 8C shown, an adjacent body connection with the second device by a polysilicon strip ( 510 ) provided with the polysilicon structure ( 110 ) of the second device (identified by L _G2 ) and via the source area ( 120 ) of the second device to a body contact area ( 540 ) (for example P + doped), which in the source region ( 120 ) of the second device is formed. As related to 4A-7B such a polysilicon strip ( 510 ) can be used to form a corresponding body strip underneath the polysilicon strip ( 510 ) having an adjustable resistive conduction path between the body region of the second device and the body contact region ( 540 ). Characterized in that the first transistor (identified by L _G1 ) has no body connection, it is a three-terminal transistor, as in 8I is shown (upper transistor in the figure).

According to a in 8D shown further exemplary embodiment of the present disclosure, an abutting body connection with the second device (identified by L _G2 ), in the 8D represented over two polysilicon strips ( 510 ) provided with the gate polysilicon structure ( 110 ) of the second device and are connected via the source region ( 120 ) of the second device and in addition to a body contact area ( 440 ) (for example P + doped) adjacent to the source region ( 120 ) of the second device. Such polysilicon strips ( 510 ) can therefore provide corresponding body strips to resist the body region of the second device resistively with the body contact region (FIG. 440 ), as described above. The schematic representation of the cascode configuration with adjoining body connection of 8D is also in 8I shown, wherein the first transistor (identified by L _G1 ) is a transistor with three outputs, as in 8I is shown (upper transistor in the figure).

According to some embodiments of the present disclosure, one or more adjacent body connections may also be used for the first device (identified by L _G1 ) of the 8C-8D be provided as in 8E is shown. As in 8E can be shown, an adjoining body connection for the first device via a first polysilicon strip ( 510 ) provided with the gate polysilicon structure ( 110 ) of the first device (identified by L _G1 ) and via the common drain / source regions ( 130 / 120 ) of the two cascode devices to a body contact area ( 540 ) (for example, P + doped) located in the common drain / source regions (FIG. 130 / 120 ) is trained. As related to 4A-7B such a polysilicon strip ( 510 ) can be used to form a corresponding body strip underneath the polysilicon strip ( 510 ) having an adjustable resistive conduction path between the body region of the first device and the body contact region ( 540 ). The schematic representation of the cascode configuration with adjoining body connection of 8E is in 8J shown, wherein both transistors (identified by L _G1 and L _G2 ) Are four-terminal transistors, each having an adjacent body connection.

Those skilled in the art will understand that various combinations are made with reference to 4A-7B structures are possible to provide for an abovementioned abutting body connection for one of the first and second (or more at higher stack size) devices of the cascode configuration in accordance with the present disclosure. For example, the first device with an attached body connection according to any of 4A-5A and 7A-7B can be provided, and the second (last) device, regardless of an adjacent body connection for the first device, with an abutting body connection according to any in 4A-7B be provided structure shown.

8F and 8K represent an extension of the 8C and 8E 1, wherein the cascode configuration comprises n transistor devices electrically connected in series, the source (FIG. 120 ) and the drain ( 130 ) of two adjacent devices as in the case of 8C shown embodiment are united. It should be noted that it is possible that in the cascode configuration according to the present disclosure, those disclosed in U.S. Pat 8C-8K is shown, only the last device (eg the second device of 8C and the nth device of 8F ) with an adjacent body connection according to the in 6 shown structure is provided.

According to another embodiment of the present disclosure, a desired performance of the stack (eg 8C-8K ) can be optimized by providing different or equal body connection structures for different devices of the stack, thereby providing resistors with different or equal values between the body and the contacts for each of the devices of the stack. The performance of individual devices with respect to a body connection structure are in 10A-19 and will be described later.

According to some embodiments, not all of the devices of the stack are provided with an adjacent body connection structure, and therefore the stack may comprise a combination of three port and four port devices, such as in FIG 8C-8D and 8I-8J is shown. 8G and 8H show further such exemplary embodiments in which some (four-port) devices of the stack are provided with an abutting body interconnect structure in accordance with the present teachings and other devices (three-ported) are not provided with an abutting body interconnect. According to the in 8G Illustrated exemplary cascode configuration is only the last device (identified by L _Gn ) with an abutting body connection according to the present teachings, and according to the in 8H The exemplary cascode configuration shown is only the second device (identified by L _G2 ) and the last device (identified by L _Gn ) with an adjacent body connection according to the present teachings. Of course, such exemplary embodiments should not be construed to limit the scope of the present invention, as variants of such interfaced-body stacked-device embodiments in accordance with the present disclosure are well within the skill of the artisan in light of the present teachings.

The above embodiments of the present body connection according to the present disclosure describe electrical connections of the body (channel) region of a transistor device to the corresponding source region, and thereby to the potential applied to the source terminal of the device. According to another embodiment of the present disclosure, an applied body connection may be provided that is decoupled from the potential at the corresponding source terminal. Such an embodiment allows the coupling of the adjacent body connection to a potential independent of the potential at the source terminal of the corresponding device. An appropriate structure is in 9A and in 9B and a corresponding schematic representation is shown in FIG 9D shown.

9A shows a plan view of a device with adjacent body connection ( 900A ) according to an embodiment of the present invention Disclosure that can be used to resistively connect the body region of the device to any potential. The transistor device ( 900 ) (eg, a thin film SOI device) has a similar structure for providing the abutting body connection as described with reference to FIG 5A described with the difference that the body contact area ( 540 ) now from the source area ( 120 ) over one P Insulating region which is below the polysilicon structure ( 910 ) formed with the polysilicon strip ( 510 ) connected is. Similar to the polysilicon strip ( 510 ), the polysilicon structure ( 910 ) the training of a corresponding P - isolation area ( 912 ) below the polysilicon structure ( 910 ), which is contiguous with the body stripe that extends across the polysilicon strip ( 510 ), and therefore with the body region below the gate polysilicon structure ( 110 ) is electrically connected. Of the P- Isolation area ( 912 ) surrounds the body contact area ( 540 ) in the source area ( 120 ) such that no contact between the areas ( 540 ) and ( 120 ), as in the cross-sectional view of FIG 9B is shown. It is noted that the same numbers (reference numerals) in the figures represent like objects and therefore may be used to describe the other figures of the present disclosure.

9B shows a cross-sectional view of the device with adjoining body connection ( 900A ) along the line F of 9A , How out 9B shows that the source area ( 120 ) of the body contact area ( 540 ) on the P- Isolation area ( 912 ) isolated to the polysilicon structure ( 910 ) and the BOX layer ( 150 ), which forms a common basis for all active areas of the device, including the areas ( 120 . 912 . 540 ), which in the cross-sectional view of 9B are shown.

Those skilled in the art will understand that the body contact area ( 540 ), because it is from the source area ( 120 ) is isolated during operation of the device with body connection ( 900A ) of the present invention can be connected to any desired potential while providing a resistivity adjustable conductive path to the body region of the device. Such a connection of the isolated body contact area ( 540 ) with a desired potential can take place, for example, via a metal contact which is located on top of the area ( 540 ) is attached.

According to further embodiments of the present disclosure, the teachings that may appear 9A and 9B to be extended to adjacent fingers, as in 9C represented by ( L _G1 . L _G2 ) identified fingers that share a common source region ( 120 ), in the common source area ( 120 ) may be provided with an isolated adjacent body connection to allow body contact with any desired potential. It will be understood by those skilled in the art that, due to the insulation relative to the adjacent areas, the body contact area (FIG. 540 ) in each active area of the device ( 900C ) that is different from the body region, including in the drain region (FIG. 130 ).

It should be noted that each of the adjacent body connection source configurations in accordance with the present invention as shown in the figures described above (eg 4A-8H ), with an equivalent isolated-fitting body compound as shown in 9A-9D is illustrated can be provided. Accordingly, the in 8C-8K If necessary, stacked transistor structures shown can also be provided with isolated body connection structures. Those skilled in the art may further extend the teachings of the present disclosure to configurations that include a combination of isolated adjacent body compounds and adjacent body compounds for the source.

The abutting body joint set forth above according to the various embodiments may have a lower resistance (first resistor described above) between the transistor channel and the body contact region (eg, regions (FIG. 440 . 540 )) when the transistor is in a non-conducting state (as opposed to the conducting state of the transistor). When the gate voltage Vg of a transistor with the applied body connection according to various embodiments of the present disclosure is close to or below the voltage of the transistor (threshold voltage Vt), thereby putting the transistor in the off / non-conducting state, then the doping in the Body strip provides a resistive conduction path from the body contact region to the transistor body region under the gate polysilicon. The body stripe is conductive from the surface of the silicon through its entire depth. If the gate voltage Vg of such a transistor is near or above the transistor threshold voltage Vt, thereby placing the transistor in the on / off state, then there exists in the body strip a region depleted of mobile charge. This region begins at the upper surface of the active silicon layer and extends into the silicon. This depletion region becomes non-conductive, thereby reducing the cross section of conductive silicon in the body stripe (thereby increasing resistivity). Accordingly, when the transistor is in a conductive state (Vg> Vt), the abutting body connection may be in accordance with the various embodiments of the present invention Revelation provide a higher resistance between the transistor channel and the body connection (which is provided on the body contact region), as compared to the case where the transistor is not conducting. Such a higher resistance enables the loss reduction in the characteristic RF power of the transistor due to the provision of the body connection. Those skilled in the art will appreciate the loss in characteristic RF power of a transistor associated with providing a body connection for the transistor, and will therefore appreciate the benefits of the applied body connection in accordance with the present invention.

10A shows a graph of the (effective) resistance Reff of the applied body connection to the gate bias voltage Vg and the body stripe width (in microns). As from the graph in 10A For example, for a given body stripe width (width along the gate width), the resistance of the body interconnect increases as a function of the gate bias voltage Vg. Specifically, for a case where the gate bias voltage Vg = -0.3 V (transistor is nonconductive), the effective resistance of the body junction is 1 MΩ, and in a case where the gate bias voltage Vg = 1 V (transistor is conductive), the effective resistance of the body junction is greater than 1000 MΩ. As from the graph of 10A Likewise, for a given gate bias Vg, the effective resistance decreases as the width of the body stripe increases.

A transistor with the applied body connection according to the various embodiments of the present disclosure may have advantages in comparison with a transistor without body connection (Floating Body) or to a transistor with conventional (H-gate, T-gate) body connection Show performance. Such advantages in performance include, but are not limited to, improved control of majority carriers and electrical potential in the body region of the transistor without the disadvantage of conventional (H-gate, T-gate) body-connected transistors.

In comparison to a floating body transistor, the applied body connection according to the present invention provides a higher breakdown voltage, a lower drain-source current (Ids) in the off state (non-conducting state) with increased drain-source voltages (Vds), lower Decrease in output impedance with increased on-state Vds (conductive state) and improved HCI (hot carrier injection) performance for RF applications.

In comparison to a conventional body-connected (H-gate, T-gate) transistor, the on-body connection in accordance with the present invention provides a lower overall parasitic gate capacitance (sum of all capacitances applied to the gate), a smaller one Drain-gate capacitance (no increase over floating body transistor), higher f _max (due to reduced drain-gate capacitance) and no channel width limitation to maintain the properties of body-connected devices. Compared to the in 3A In the illustrated prior art source-body interconnect structure, the present invention of the attached body interconnect also provides for a simpler manufacturing process, lower manufacturing cost, and higher process yield.

The above-mentioned characteristic of the present body connection according to the present invention, in addition to all other applications that benefit from improved output impedance and breakdown voltage, allow for higher Peak Power Added Efficiency (PAE) for RF power amplifier applications.

10B shows diagrams showing the drain-source current (Ids) in the off state (eg gate-source voltage Vgs = 0) of two floating body transistors ( T _1A . T _1B ) and two transistors with the adjacent body connection ( T _2A . T _2B ) according to the various embodiments of the present disclosure. The transistor T _1A is identical (eg same gate length) with the transistor T _2A , and the transistor T _1B is identical (eg same gate length) with the transistor T _2B , The diagrams of 10B clearly show that the current Ids in the off state (leakage current) at increased values of the drain-source voltage Vds in the case of the transistors with the adjacent body connection ( T _2A . T _2B ) is lower. Also, based on the diagrams of 10B It is also clear that the effective breakdown voltage (voltage Vds at which the current Ids reaches a certain level) in the case of the transistors with the adjacent body connection ( T _2A . T _2B ) is higher because at all points of the curve the Ids currents for ( T _2A . T _2B ) are lower than the Ids streams for ( T _1A . T _1B ).

11A and 11B 12 show diagrams of Ids versus Vds of identical transistor devices with body connection or without body connection, wherein the gate-source voltage Vgs is stepped (varied) in steps of 25 mV. As can be seen from these diagrams, the transistor with the applied body connection exhibits a smooth Ids Vds curve independent of the Vgs voltage and does not have the known kink characteristic of a floating body transistor, as in 11B you can see. The position of in 11B apparent knicks depends on the voltage applied to the floating body transistor Vgs voltage from. As known to those skilled in the art, such kinking represents an abrupt decrease in the output impedance of the transistor (Vds / Ids) and is undesirable in many RF applications as well as in low frequency analog applications. How out 11B As can be seen, depending on the applied Vgs voltage, the kink occurs at a Vds voltage of 0.6V to 0.8V.

12A-12C 10 are diagrams showing the influence of the number of body stripes of a body-connected transistor according to the present invention on the Ids / Vds response of the same transistor device (eg, same channel length and channel width). The device with adjoining body connection (whose graphic in 12A has a polysilicon strip (which branches off from a corresponding gate polysilicon structure), the body-connected device in FIG 12B has 4 polysilicon strips and the device with adjoining body connection in 12C has 7 polysilicon strips, each connected to a corresponding body contact area. As from the diagrams of 12A-12C As can be seen, the output conductance and the breakdown voltage are improved by a larger number of polysilicon strips of the body-connected device. 12D shows diagrams for the output conductance g _ds versus the number of body stripes of an attached body connection device with a fixed gate width W _G are representative of a fixed gate bias Vg = 0.6V.

13 and 14 Figure 12 shows diagrams illustrating the influence of the applied body connection on the same transistor with body connection with respect to the injection of hot carriers during the service life of the transistor when used in an RF application. This is measured by monitoring the change in bias current at fixed input bias for identical transistors, with and without the applied body connection operating as amplifier output transistors under RF power loading. 13 FIG. 12 is a graph representative of a reduction of the bias current with time due to hot carrier injection in the case of the floating body transistor. FIG. As from the graph of 13 As can be seen, the injection of hot carriers causes the bias current to gradually drift and fall over time. This in turn can lead to unwanted power of the RF amplifier using such a transistor device. In contrast, the graph of 14 in that the same body-connected transistor (identical transistor), when operated under the same conditions, shows no change in the bias current over time. This result shows that the on-body connection of the present invention provides an effective output for the minority carrier charges generated in the transistor channel over time due to the hot carrier injection phenomenon. Those skilled in the art will appreciate the better performance of the abutting body connection in accordance with the present disclosure as well 14 and will appreciate the importance of such a curve in terms of the reliability and configurability of the on-body transistor.

15A 2 shows diagrams showing the measured standardized total gate capacitance Cgg for a transistor (FIG. T2 ) with an adjacent body connection opposite an identical transistor ( T1 ) without body connection (floating body) for a gate bias voltage Vg = 0.5 volts and one transistor width W _G = 10μm. 15B shows diagrams showing the measured normalized Cdg for the same transistors / conditions as in the diagrams of 15A represent. As from the diagrams of 15A and 15C As can be seen, the total capacity with added body connection is only moderately increased and the measured Cdg is even lower.

16A-16B FIG. 3 shows comparison diagrams illustrating the influence of the applied body connection according to the present disclosure on the frequencies. FIG f _T and f _max represent a transistor. 16 shows f _T Data diagrams for a floating body transistor (top graphic) and f _T Data diagrams for three different configurations of a transistor with an applied body connection, wherein the floating body transistor and the transistors with body connection are otherwise identical (eg same channel length and width). As from the diagrams of 16A is apparent, is a moderate decrease in frequency f _T to observe. This may be due to the increased C _GS capacity provided by the attached body connection configuration, as in 15D can be seen, is obtained. 16B show the f _max Data diagrams that use the same transistors / conditions as the data diagrams of 16A correspond. Like from the data diagrams of 16B is apparent follows f _max the in the diagrams of 16A apparent f _T Reduction without further deterioration.

17 FIG. 3 shows comparison diagrams illustrating the influence of the applied body connection according to the present invention on an application as an RF power amplifier. FIG. As known to those skilled in the art, Peak Power Added Efficiency (PAE) for a given adjacent channel Adjacent Channel Power Ratio (ACPR), also known as Adjacent Channel Leakage Ratio (ACLR), a feature of RF power amplifiers. The linearity and frequency requirements in RF applications do not allow the use of conventional T-gate or H-gate transistors. However, the on-body connection configuration according to the present invention may be used because it has no drain-gate capacitance C _DG adds and also less total gate capacity C _GG adds, as can be seen from the previous diagrams. Therefore, as the graph of 17 As can be seen, the ACLR for the transistor with body connection close enough before the ACLR increases because the transistor reaches the compression point. A typical diagram for ACLR is for identical floating body devices and devices with adjacent body connection in 17 shown. It is noted that both transistors have an ACLR of less than -40 dBc before rapidly increasing due to compression. For a wide range of device sizes and bias conditions, both the floating body configuration and the body-connected configuration provide an ACLR of less than -40 dBc (dB relative to a corresponding RF carrier).

A higher bias voltage may allow a transistor to operate at a higher output Pout until the transistor reaches the compression point. Thus, the higher breakdown voltage provided by a body-connected transistor may allow the transistor to operate at a higher bias and therefore higher Pout. 18 Figure 12 shows data plots representative of gain versus Pout for identical floating body transistors and adjacent-body-connected transistors at identical bias, with relatively high bias. Like from the data diagrams of 18 As can be seen, the on-body device may operate at higher power prior to entering the compression point, the compression point being represented by a reduction (decrease) in gain.

As is known to those skilled in the art, a lower bias current (Ibias) reduces the power dissipated in a transistor, which is wasted power and therefore reduces the efficiency of the transistor. When operating with high bias and high RF power, the voltage of the body region of the transistor may increase due to generated carriers. For a floating body device, the body potential increases as evidenced by the kink in the above discussed 11B is apparent. In the case of a body-connected device of the present invention, these generated carriers are routed out over the provided body-stripe conduit. For RF applications, the bias current may increase with increasing power due to the increase in the body potential of the floating body transistor, particularly under operating conditions that cause transient operation in the areas affected by increased body potential (kink), while for the transistor adjacent Body connection the bias current remains adequate. This is in 19 shown.

Exemplary and non-limiting applications for transistor devices employing the abutting body interconnect in accordance with various embodiments of the present disclosure may include general analog circuits including body interconnects, power amplifiers, low noise amplifiers, analog-to-digital converters, voltage controlled oscillators, and voltage reference circuits at frequencies. which range from DC to 100 GHz and above.

In the teachings of the present disclosure, the gate length can be further optimized (the gate length can be shortened). Such as from the previously described 10B As can be seen, a larger breakdown voltage can be achieved with a body-connected transistor in accordance with the present disclosure as compared to a floating body transistor. Therefore, the transistors with attached body connection ( T _{2, A} . T _{2, B} ) from 10B compared to the floating body transistors ( T _{1, A} . T _{1, B} ) with higher V _DS Strains run safely, because the higher I _ds Currents belonging to the latter transistors, the transistors at higher V _DS Can break tensions. As is known to those skilled in the art, such breakdown of the transistors ( T _{1, A} . T _{1, B} ) are controlled by changing the gate length of the transistors, with larger gate lengths having a higher breakdown voltage and therefore a higher one V _DS Operating voltage of the transistor can enable. In other words, a desired breakdown voltage for the floating body transistor ( T _{1, A} . T _{1, B} ) over a larger gate length compared to the transistors with applied body connection ( T _{2, A} . T _{2, B} ) provided. Also compared to the in 3A The prior art body connection illustrated may require the overlap area between the areas (FIG. 110 ) and ( 340 ) prescribe a longer gate length.

As above with reference to 8C-8F The present body connection of the present invention may be provided for a cascode configuration having a plurality of stacked transistors. 20A provides schematically a cascode configuration ( 2000A ) of two stacked transistors ( T _A . T _B ), and 20B schematically shows a cascode configuration ( 2000B ) of three stacked transistors ( T _C . T _D . T _E ). As explained above, an adjacent body connection for a transistor (eg T _B . T _D . T _E ) may be provided by a body contact region disposed in a source region of the transistor common to a drain region of an adjacent transistor of the cascode configuration. Throughout this document, these definitions of T _A - T _E used to mean transistors in the circuit arrangements, which are for example in 20A respectively. 20B are shown. This is in 21A 3, which depicts an abutting body connection according to the present disclosure for the transistor T _B from 20A shows.

As in 21A is shown extends a polysilicon strip ( 510B ) associated with the gate polysilicon structure ( 110B ) of the transistor T _B connected via the common source / drain regions ( 120B / 130A ) of the transistors ( T _B . T _A ) to a body contact area ( 540B ) (for example, P + doped) located in the common source / drain regions ( 120B / 130A ) is trained. In some cases, due to a desired physical size of the polysilicon strip ( 510B ) and the body contact area ( 540B ) the distance between corresponding gate polysilicon structures ( 110A . 110B ) of the transistors ( T _A . T _B ) and therefore the corresponding body regions defined by these gate polysilicon structures. This is in 21A where the common source / drain regions have a further common region compared to the drain region (FIG. 130B ) of the transistor T _B and the source region of the transistor T _A form a distance for the fitting body connection ( 510B . 540B ). Such a further region causes a larger distance between the gate polysilicon structures ( 110A . 110B ) of the two transistors ( T _A . T _B ), which therefore leads to an overall increase in the overall physical size of the cascode configuration ( 2000A ) from 20A can lead. According to one embodiment of the present disclosure, the overall physical size of the cascode configuration ( 2000A ) while an adjacent body connection of the same desired physical size discussed above (eg, the desired physical size of the structures ( 510B . 540B )) provided. It should be noted that in 21A and in the following figures, the various structures used to implement the various body-connected configurations of the present disclosure are represented by corresponding plan-top structures, with corresponding alternative views of such various structures by those skilled in the art, given the above explanation, focusing on the 1-9D relates, can be understood without further notice.

According to one embodiment of the present disclosure, the overall physical size of the cascode configuration ( 2000A ) with adjacent body connection for the upper transistor T _B can be reduced by breaking a fraction in the gate polysilicon structure ( 110A ) of the lower transistor T _A is trained as in 21B is shown. For the attached body connection ( 2100B ) from 21B the presence of the fracture region allows the polysilicon strip ( 510B ) through the fracture region over a region that normally defines the gate polysilicon structure ( 510B ) and therefore allows a smaller distance between the two gate polysilicon structures (FIG. 110A ) and ( 110B ) while the desired physical size of the polysilicon strip ( 510B ) and the contact area ( 540B ) preserved. In particular, to the source area ( 120A ) from the common source / drain regions ( 120B / 130A ) to isolate an isolation area ( 2090 ) is formed around the fracture region that extends into the common source / drain regions ( 120B / 130A ) of the transistors ( T _B . T _A ) and in the source area ( 120A ) of the transistor T _A extends. According to in 21D In other embodiments of the present disclosure, the isolation area (FIG. 2090 ) completely through the source region ( 120A ) to a limit ( 2090 ) of this area, thereby dividing the source area ( 120A ) into two separate (separate left and right) source regions ( 120A ), each from the common source / drain regions ( 120B / 130A ) are isolated. The isolation area ( 2090 ) from 21B . 21D can be formed by removing (eg, etching, oxidizing, etc.) the silicon from the region, thereby creating a non-conductive region.

With further reference to the adjacent body connections ( 2100B . 2100D ) from 21B . 21D is the fraction in the gate polysilicon structure ( 110A ) a distance to the extension of the polysilicon strip ( 510B ) beyond a path which is a distance between the gate polysilicon structures ( 110A ) and ( 110B ), and the fraction in the source region ( 120A ) passing through the isolation area ( 2090 ) provides a conduction channel for a body stripe that passes through the polysilicon strip ( 510B ), and which extends over a silicon region that is normally connected to the source region (FIG. 120A ) would belong. Besides, as in 21B . 21D is shown, a body contact area ( 540B ) is formed in a region which is located at the isolation region ( 2090 ) is applied to a fitting body connection ( 2100B ) according to the present teachings for the transistor T _B (defined by 110B, 120B, 130B). The body contact area ( 540B ) contacts the through the polysilicon strip ( 510B ) defined body strips at a distal end of the body strip of the body region of the gate of the transistor T _B removed by the polysilicon structure ( 110B ) is defined. The silicon region and the polysilicon (gate and body stripe) of in 21B illustrated embodiment according to the present disclosure are shaped so that the silicon region, the drain ( 130A ) of the transistor T _A and the source ( 120B ) of the transistor T _B forms, from the source ( 120A ) of the transistor T _A but has a continuous silicon region to the body stripe of the transistor T _B and provides to the area where the body strip of the transistor T _B into the body contact area ( 540B ).

21C . 21E show exemplary methods according to the present disclosure for generating the (P + doped) body contact region (FIG. 540B ) using a target ( 2120 ) for implantation of a dopant of P -Type. That the polysilicon strip ( 510B ) forms a barrier for the implantation of the dopant and the isolation region is free of silicon, means that only the common region between the regions 120B / 130A and the target ( 2120 ), whereby the in 21B illustrated body contact areas ( 540B ) be generated. Any other methods known to those skilled in the art may be used to determine the body contact areas (FIG. 540 ) according to the present teachings.

22 shows an attached body connection implementation ( 2200 ) according to another embodiment of the present disclosure for a case where the transistors T _A and T _B the cascode configuration ( 2000A ) each more than one finger (eg two fingers, as for example by corresponding gate polysilicon structures ( 110A . 110B ) from 22 are defined). Professionals will understand that in 22 illustrated configuration with attached body connection ( 2200 ) according to the present disclosure, an extension of the teachings according to the in FIG. ( 21B . 21D ) embodiment ( 2100B . 2100D )) is for a case where each of the transistors ( T _A . T _B ) has more than one finger. 22 shows the two fingers of each of the two transistors ( T _A . T _B ) of the cascode configuration ( 2000A ) around a midline C _L the source ( 120A ) of the transistor T _A mirrored, which is a common source for both fingers of the transistor. As in 22 can be seen, the transistor has T _A two fingers around the midline C _L mirrored (each by a separate non-contiguous area ( 110A ), each separate non-contiguous area ( 110A ) is broken at an area that passes through the isolation area ( 2090 ), each finger having similar areas ( 110A . 120A . 130A ), which are mirrored about the centerline C _{L of} the stack, with the centerline C _L through the middle of the area ( 120A ) runs. Next from the center line C _L removed and mirrored around the center line are fingers of the transistor T _B arranged, each finger similar areas ( 110B . 120B . 130B ), the areas ( 120B ) with the areas ( 130A ) of the transistor T _A are common. The areas ( 130E ) of the transistor T _B ends at areas that are aligned with the line ( 2095 ) are marked.

According to the in 22 illustrated embodiment ( 2200 ), the total physical size of the cascode configuration ( 2000A ) with an adjacent body connection for the upper transistor T _B can be reduced by using in the gate polysilicon structure ( 110A ) each of the fingers of the lower transistor T _A a fracture area is formed as in 22 is shown. The fracture region allows a polysilicon strip ( 510B ) each of the fingers of the transistor T _B through the fracture region beyond a region that normally defines the gate polysilicon structure ( 110A ) of an adjacent finger of the transistor T _A and thus the rupture area allows for a smaller spacing between the two gate polysilicon structures (FIG. 110A ) and ( 110B ) of adjacent fingers while the desired physical size of the polysilicon strip ( 510B ) and the contact area ( 540B ) which is used to apply the fitting body connection to each of the fingers of the transistor T _B provide. Therefore, as in 22 is shown, each of the fingers (defined by the gate polysilicon structures ( 110B )) of the upper transistor T _B provided with an adjacent body connection through the structures ( 510B . 540B ), which, according to one embodiment of the present disclosure, is symmetrical about the centerline C _L the structure ( 2200 ) can be arranged. It should be noted that 22 only fitting body connections for fingers of the upper transistor T _B the cascode configuration ( 2000A ) shows. Pending body connections for fingers of transistors of a cascode stack which differ from the upper transistor are, for example, in 25-29B seen.

With further reference to the attached body connection ( 2200 ) from 22 becomes the source area ( 120A ) (which is common to both fingers) each of the fingers ( 110A ) of the lower transistor T _A the cascode configuration (schematic in 20A shown) of each of the common source / drain regions ( 120B / 130A ) to isolate an isolation area ( 2090 ) around the two fracture areas surrounding the source region ( 120A ), of the both fingers ( 110A ) of the transistor T _A is common, into two separate (separate) source regions ( 120A ), each from both of the common source / drain regions ( 120B / 130A ) are isolated. The isolation area ( 2090 ) can be formed by removing (eg, etching, oxidizing, etc.) the silicon from the region, thereby creating a non-conductive region.

With further reference to 22 represent the fractions in the gate polysilicon structures ( 110A ) a distance to the extent of the polysilicon strips ( 510B ) over a distance equal to a distance between adjacent gate polysilicon structures ( 110A ) and ( 110B ), ready, and the break in the source area ( 120B ) passing through the isolation area ( 2090 ), provides a conduit for a body strip ( 120A prepared by the polysilicon strip ( 510B ) is defined and extends over a silicon region that normally leads to the source region ( 120A ) would belong. In addition, in an area adjacent to the isolation area ( 2090 ), a body contact area ( 540B ) to form an abutting body connection in accordance with the present teachings for each finger of the transistor T _B provide. The body contact area ( 540B ) contacts the body strips that pass through the two polysilicon strips ( 510B ) at a distal end of the body strips away from the body regions of the gates of the transistor T _B generated by the gate polysilicon structures ( 110B ) are defined.

As in the configuration ( 2200 ) from 22 can be seen, the silicon region and the polysilicon structures (gates and body stripes) of in 22 according to the present disclosure shaped so that for each finger of the transistor T _A and a corresponding adjacent finger of the transistor T _B the silicon region surrounding the drain ( 130A ) of the finger of the transistor T _A and the source ( 120B ) of the adjacent finger of the transistor T _B forms, from the source ( 120A ) of the transistor T _A (the two fingers of T _A is common) but at the same time provide a contiguous silicon region for the body stripe of the finger of the transistor T _B and for the area where the body stripe goes into the body contact area ( 540B ) ready.

In the 21B and 22 illustrated fitting body connection ( 2100B . 2200 ) according to the present teachings may be extended to cascode configurations with more than two stacks, for example with three, four and more stacks, wherein breaks in gate polysilicon structures arranged with isolation regions ( 2090 ), as explained above, may be used to provide abutting body connections for the transistors / fingers of the cascode stack.

23 shows an attached body connection implementation ( 2300 ) according to another embodiment of the present disclosure for the in 20B illustrated cascode configuration ( 2000B ) with three transistors ( T _C . T _D . T _E ), each transistor having at least two fingers. 23 shows two fingers of each of the three transistors ( T _C . T _D . T _E ) of the cascode configuration ( 2000B ), which are around a midline C _L the source ( 120C ) of the (lower) transistor Tc which is a common source for both fingers of the transistor Tc, the common source region ( 120C ) through an isolation area ( 2090 ) in a central region of the source ( 120C ) is interrupted. How out 23 can be seen, the transistor has T _C two fingers around the midline C _L mirrored (each by a separate non-contiguous area ( 110C ), each separate non-contiguous area ( 110C ) at an area that passes through the isolation area ( 2090 ) is defined), each finger having similar areas ( 110C . 120C . 130C ), which is around the midline C _L of the stack are mirrored (with the center line C _L through the middle of the area ( 120C ) runs along the width of the area). Next from the center line C _L away and around the midline C _L mirrored are fingers of the (middle) transistor T _D (each finger being separated by a separate non-contiguous area ( 110D ), each separate non-contiguous area ( 110D ) is broken at an area that passes through the isolation area ( 2092 ) between the fingers of the transistors (below) T _C and (above) T _E arranged, each finger similar areas ( 110D . 120D . 130D ), the areas ( 120D ) with the areas ( 130C ) of the transistor Tc are common. Also, at the furthest from the midline C _L distant ends and mirrored around the center line fingers of the (upper) transistor T _E , (each finger through a separate contiguous area ( 110E ) identifies adjacent to the fingers of the transistor T _D arranged, each finger similar areas ( 110E . 120E . 130E ), the areas ( 120E ) with the areas ( 130D ) of the transistor T _D are common and the areas ( 130E ) end up in areas that coincide with the lines ( 2095 ) Marked are.

According to the in 23 illustrated embodiment of the adjacent body connection ( 2300 ), the total physical size of the cascode configuration ( 2000B ) with an adjacent body connection for the upper transistor T _E can be reduced by using in the gate polysilicon structure ( 110C . 110D ) each of the fingers of the transistors T _C and T _D a fracture area is formed as in 23 is shown. The fracture areas in the fingers of the transistor T _D allow the polysilicon strips ( 510E ) the finger of the transistor T _E through the fracture regions beyond an area that normally defines the gate polysilicon structures (FIG. 110D ) of the adjacent fingers of the transistor T _D would extend. The fracture regions allow a smaller distance between the two gate polysilicon structures ( 110E ) and ( 110D ) of adjacent fingers while the desired physical size of the polysilicon strips ( 510E ) and the contact area ( 540E ) which is used to apply the fitting body connection to each of the fingers of the transistor T _E provide. As in 23 can be seen, the fracture regions are in the gate polysilicon structures ( 110D ) and ( 110C ) are substantially at the same position along the width of the fingers and have substantially the same size along the width.

With further reference to 23 is to the source area ( 120C ) (the two fingers of T _C common) each of the fingers ( 110C ) of the lower transistor T _C from each of the common source / drain regions ( 120E / 130D ) and ( 120D . 130C ) to isolate an isolation area ( 2090 ) is formed in regions around the (four) fracture regions, whereby the source region ( 120C ) and the common source / drain regions ( 120D / 130C ) to get broken. This is in 23 can be seen where the isolation area ( 2090 ) each of the common source / drain regions ( 120D / 130C ) and the common source area ( 120C ) into two separate (and isolated) areas (one on each side of the isolation area ( 2090 )), each individual area being isolated from all other source and / or drain areas of the other fingers in the stack. Although it is in 23 not shown, those skilled in the art will recognize that, if necessary, continuity between the passages passing through the isolation area (FIG. 2090 ) broken areas by means of contacts (for example, by the contacts 154 . 155 from 6 shown) in the fractured areas and by metal layers used to bridge such contacts. It should also be noted that current leakage through fractured regions that are not to be connected to external signals, such as the fractured common source / drain region (FIG. 120D / 130D ) (referring to the cascode configuration of 20B ), because the current flow over the length of corresponding fingers through the broken areas is not prevented.

With further reference to 23 represent the fractions in the gate polysilicon structures ( 110D ) a distance to the extent of the polysilicon strips ( 510E ) over a distance equal to a distance between adjacent gate polysilicon structures ( 110E ) and ( 110D ), and the fractions in the common source / drain regions ( 120D / 130C ) and in the common source area ( 120C ) passing through the isolation area ( 2090 ) provide a conduction channel for a body stripe that passes through each of the polysilicon strips ( 510E ) defined to each of the fingers of the transistor T _E with the body stripe extending over a silicon region that is normally adjacent to the common source / drain regions (FIG. 120D / 130C ) would belong. Finally, in an area adjacent to the isolation area ( 2090 ), a body contact area ( 540E ) formed by the areas ( 120D / 130C ) and ( 120C ) to provide an abutting body connection according to the present teachings for each finger of the transistor T _E provide. The body contact area ( 540E ) contacts the body strips that pass through the two polysilicon strips ( 510E ) at a distal end of the body strips away from the body regions of the gates of the transistor T _E generated by the gate polysilicon structures ( 110E ) are defined.

Like the configuration with attached body connection ( 2300 ) from 23 For example, the silicon region and the polysilicon structures (gates and body stripes) are those in FIG 23 illustrated embodiment according to the present disclosure shaped so that for fingers of the transistors T _C . T _D and T _E on the same side of the midline C _L the configuration ( 2300 ) the silicon region covering the drain region ( 130D ) of the finger of the transistor T _D and the source area ( 120E ) of the finger of the transistor T _E forms, the silicon region, the drain region ( 130C ) of the finger of the transistor T _C and the source area ( 120D ) of the finger of the transistor T _D forms and the silicon region, the source region ( 120C ) of the transistor T _C (the two fingers of T _C together), but at the same time a contiguous silicon region for the body strip of the finger of the transistor T _E (defined by the polysilicon strip ( 510E )) and for the area where the body strip is in the body contact area ( 540E ) form.

With further reference to 23 because the fractures in the gate polysilicon structures ( 110C ) form isolated gate body regions, vertical polysilicon structures ( 2320 ) can be used to form adjacent gate polysilicon structures on each side of the fractions and within the isolation region (FIG. 2090 ) connect to. According to some embodiments of the present disclosure, such vertical polysilicon structures (FIGS. 2320 ) are made sufficiently wide so that they can be provided with contacts on metal layers (not shown in the figure) which are used to restore the passage to the broken gate polysilicon structure (eg by bridging the contacts) and thereby one continuous gate channel for the transistor T _C restore. Those skilled in the art will appreciate the various methods and structures used to make such contacts for metal layers.

24 shows an attached body connection implementation ( 2400 ) according to another embodiment of the present disclosure for the upper transistor T _E the in 20B cascode configuration ( 2000B ) with three transistors ( T _C . T _D . T _E ). 24 shows two fingers of each of the three transistors ( T _C . T _D . T _E ) of the cascode configuration ( 2000B ), which are around a midline C _L of the drain region ( 130E ) of the (upper) transistor T _E which is for both fingers of the transistor T _E , a common drain area is mirrored. How out 24 shows, the transistor has T _E two fingers (each with a corresponding area ( 110E ), each finger having similar areas ( 110E . 120E . 130E ), which is around the midline C _L are mirrored (with the centerline passing through the middle of the area ( 130E ) runs along the width of the area). Farther away from the center line C _L and around the midline C _L mirrored are fingers of the (middle) transistor T _D between the fingers of the transistors (below) Tc and (top) T _E arranged, each finger similar areas ( 110D . 120D . 130D ), the areas ( 130D ) with the areas ( 120E ) of the transistor T _E are common. Finally, at the furthest from the midline C _L distal ends and mirrored about the center line fingers of the (lower) transistor Tc, adjacent to the fingers of the transistor T _D arranged, each finger having similar areas ( 110C . 120C . 130C ), the areas ( 130C ) with the areas ( 120D ) of the transistor T _D are common, and areas ( 120C ), which end at areas, with the lines ( 2095 ) Marked are. It should be noted that 24 only fitting body connections for fingers of the upper transistor T _E the cascode configuration ( 2000B ) shows. Enclosed body connections for fingers of transistors of a cascode configuration that differ from an upper transistor are, for example, those described above 21A-21E . 22 and 25-29B seen.

In the 24 attached fitting body connection ( 2400 ) according to the present disclosure provides for the body regions of the fingers of the transistor T _E a common contact area ( 2450 ) (eg P + doped) ready. How out 24 can be seen extending the two gate polysilicon structures ( 110E ) not through the silicon region and over the boundary of the silicon region (defined by the outline ( 2095 )) in the area ( 2490 but rather are in a region of the silicon region through a vertical polysilicon structure ( 2410 ), which have an underlying common body area for the two through the structures ( 110E ) defines defined body areas. A horizontal polysilicon strip ( 2420 ) is then at a midpoint (or approximately at a midpoint) of the structure ( 2410 ) and extends horizontally toward the edge of the silicon region (region which is within the outline (FIG. 2095 ) is included) to form an underlying region having a doping of the same type as the body regions. Similar to the body strips discussed above, the horizontal polysilicon strip ( 2420 ) has a low resistivity (eg, body stripe) conduction path between the body regions below the gate polysilicon regions (eg, body stripes). 110E ) and a body contact area ( 2450 ) ready. According to an exemplary embodiment of the present disclosure, the silicon region comprising the horizontal polysilicon strip ( 2420 ) near the boundary of the silicon region through the outline ( 2095 ) is defined, surrounds, extends to an extension area ( 2460 ) in which a body contact area ( 2450 ) is formed. How out 24 is apparent, the body contact area ( 2450 ) at a distal end of the extension area (FIG. 2460 ) and abuts against the non-silicon region that is defined by the outline ( 2095 ) while contacting the body strip which passes through the horizontal polysilicon strip (FIG. 2420 ) is defined. The dotted line on one side of the extension area in 24 defines a normal boundary of the silicon area without the extension area (FIG. 2460 ).

Although it has been described that the abutting body interconnects discussed above in accordance with the present teachings have an adjacent body connection for (fingers of) an upper transistor of a cascode configuration of stacked transistors, for example the transistor T _B from 20A and the transistor T _E from 20B Together, such adjacent body connections may also be used together in a same cascode configuration of stacked transistors having two, three, four or more stacked transistors (eg 8I-8K and 20A-20B ) to apply body connections for fingers of the bottom transistors of the stack, as with reference to FIG 25-29B below. In cases where the transistors of the cascode stack have more than one finger, one or more fingers of the same transistor may be provided with such adjacent body connections and / or one or more fingers of the same transistor may be provided without a body connection present. Teachings of the present disclosure provide methods and structures for forming such abutting body compounds by standard manufacturing steps known in the art, which may be used by those skilled in the art to obtain their To meet design requirements. In cases where space efficiency is a requirement, adjacent body connections ( 2100B . 2200 . 2300 . 2400 ) according to the present disclosure, which in 21B-24 are used to reduce the distance between adjacent fingers.

25 shows a section of a cascode stack with two transistors (eg 20A ) with adjacent body connections according to the present teachings described above. 25 shows two fingers of each of the transistors T _A and T _B around a centerline of a source region of the (lower) transistor T _A are mirrored. How out 25 can be seen, an adjoining body connection ( 2200 ) according to the above-described 22 for the fingers of the upper transistor T _B (defined by the gate polysilicon structures ( 110B )), wherein the adjacent body connection through the structures ( 510B . 540B . 2090 ) is formed. As described above, the structures define ( 510B ) underneath conductive regions (with low resistivity) with the same doping as the body regions of the fingers electrically connecting the body regions of the fingers to the body contact region ( 540B ) connect. Attached body connections ( 800B ) according to the above-described 8B be for the lower transistor T _A of the cascode stack, wherein the adjacent body connections through the structures ( 510A . 540A ) To be defined.

26 shows a section of a cascode stack with three transistors (eg 20B ) with adjacent body connections according to the present teachings described above. 26 shows two fingers of each of the transistors T _C . T _D and T _E which are mirrored about a centerline of a source region of the (lower) transistor Tc. How out 26 can be seen, an adjoining body connection ( 2300 ) according to the above-described 23 for the fingers of the upper transistor T _E (defined by the gate polysilicon structures ( 110E )), wherein the fitting body connection ( 2300 ) through the structures ( 510E . 540E . 2090 ) is formed. As described above, the structures define ( 510E ) underneath conductive regions (with low resistivity) with the same doping as the body regions of the fingers electrically connecting the body regions of the fingers to the body contact region ( 540E ) connect. Attached body connections ( 2200 ) according to the above-described 22 become for the fingers of the middle transistor T _D provided, wherein the adjacent body connections ( 2200 ) through the structures ( 510D . 540D . 2090 ) are formed. Finally, fitting body connections ( 800B ) according to the above-described 8B provided for the lower transistor Tc of the cascode stack of three transistors, wherein the adjacent body connection ( 800B ) through the structures ( 510C . 540C ) is defined.

27 shows the total width of the structure ( 2700 ) of the cascode stack with three transistors of 20B , which is equipped with adjacent body connections according to the various teachings of the present disclosure for the purpose of reducing the physical size of the cascode stack. 27 shows four fingers of each of the transistors T _C . T _D and T _E around a centerline of a drain region of the (upper) transistor T _E mirrored with the upper transistor through gate polysilicon regions ( 110E ) is defined. How out 27 As can be seen, the upper two fingers are the transistors T _C . T _D and T _E further around a centerline of a source region of a lower transistor T _C mirrored, wherein the source region is contained in a region which is represented by the two gate polysilicon structures ( 110C ) of the lower transistor T _C is defined, and the lower two fingers of the transistors T _C . T _D and T _E are further around a centerline of a source region of the lower transistor T _C mirrored, wherein the source region is contained in a region which is represented by the two gate polysilicon structures ( 110C ) of the lower transistor T _C is defined.

With further reference to 27 is every finger (defined by the structure 110E ) of the upper transistor T _E of the cascode stack with an adjacent body connection structure ( 2300 ), each finger (defined by the structure 110D ) of the middle transistor T _D with two adjacent body connection structures ( 2200 ), and each finger (defined by the structure 110C ) of the lower transistor T _C with four adjacent body connection structures ( 800B ), wherein details of the adjacent body connection structures ( 800B . 2200 . 2300 above with reference to 26 are set out.

With further reference to 27 become fitting body connections ( 2400 ) according to the teachings of the present disclosure, above with reference to 24 were discussed for the fingers of the upper transistor T _E provided the centerline drain region of the (cascode) structure of 27 define. Such an attached body connection ( 2400 ) has structures ( 2410 . 2420 . 2450 . 2460 ), referring to above 24 have been described. The fingers of the upper transistor T _E that define the centerline drain region therefore have an abutting body connection structure ( 2300 ) at a midpoint of the width of the structure ( 2700 ) and two adjacent body connection structures ( 2400 ) at the opposite ends of the width.

28 shows the same overall width of the structure of 27 with the exception that the adjacent body connection structures ( 2400 ) have been removed, eliminating the fingers of the upper transistor T _E only one single attached body connection structure ( 2300 ) to have.

29B shows the total width of the structure ( 2900B ) of the four-transistor cascode stack ( 2900A ) from 29A which is equipped with body connections for a reduced physical size of the cascode stack according to the various teachings of the present disclosure. 29B shows four fingers of each of the transistors T _B . T _C . T _D and T _E around a midline C _L a drain region of the (upper) transistor T _E mirrored with the upper transistor through gate polysilicon regions ( 110E ) is defined. How out 29B As can be seen, the upper two fingers are the transistors T _B . T _C . T _D and T _E further around a centerline of a source region of the lower transistor T _B mirrored, wherein the source region is contained in a region which is represented by the two gate polysilicon structures ( 110B ) of the lower transistor T _B is defined, and the lower two fingers of the transistors T _B . T _C . T _D and T _E are further around a centerline of a source region of the lower transistor T _B mirrored, wherein the source region is contained in a region which is represented by the two gate polysilicon structures ( 110B ) of the lower transistor T _B is defined.

With further reference to 29B is every finger (defined by the structure 110E ) of the upper transistor T _E of the cascode stack with an adjacent body connection structure ( 2400 ), each finger (defined by the structure 110D ) of the transistor T _D with adjacent body connection structure ( 2300 ), each finger (defined by the structure 110C ) of the transistor Tc with two adjacent body connection structures ( 2200 ), and each finger (defined by the structure 110B ) of the lower transistor T _B with four adjacent body connection structures ( 800B ), wherein details of the adjacent body connection structures ( 800B . 2200 . 2300 . 2400 ) above with reference to 26 and 24 are set out. Unlike the in 27 represented and described above overall width of the structure ( 2700 ), represents the overall width of the structure ( 2900B ), in the 29B only one type of abutting body-connection structure is shown (structure 2400 ) for the upper transistor of the cascode stack, in contrast to the two adjacent body connection structures ( 2300 . 2400 ) corresponding to the structure of the upper transistor of the stack ( 2700 ) to be provided.

How out 27 . 28 and 29B can be seen, a body strip of an adjacent body connection structure (eg the body strips ( 510B . 510E ) of the body connection structures ( 2200 . 2300 ) as in 22-23 shown) for a finger of a transistor (eg T _E . T _D by forming a break in a gate polysilicon structure of an adjacent finger of a next (lower) transistor (eg T _D . T _C ) provided. Again, a body strip (eg 510D) of an adjacent body connection for the next transistor (eg T _D by forming a break in a gate polysilicon structure of an adjacent finger of a next (lower) transistor (eg T _C ), and so on. Thus, starting from a topmost transistor of a cascode stack of a plurality of transistors and down to the bottommost transistor of the cascode stack, the number of body stripes in a finger of a transistor of the cascode stack doubles as each segment of a refracted gate polysilicon structure (FIG. 110D ..., 111C ) may be provided with a body stripe (an adjacent body interconnect), which may require a break in an adjacent gate polysilicon structure. This is in 28 exemplified where a finger of the top transistor T _E with an attached body connection structure ( 2300 ) whose body stripes ( 510E ) in a fracture region of the gate polysilicon structure ( 110D ) of a finger of a next lower transistor T _D is formed, whereby two individual gate polysilicon structures ( 110D ) are formed on each side of the fracture, which in turn each have an adjacent body connection structure ( 2200 ) to have. The two adjacent body connections ( 2200 ) of the finger of the middle transistor T _D in turn cause fractures in the gate polysilicon structures ( 110C ), which in connection with the body strip ( 510E ) formed four individual (broken) gate polysilicon structures ( 110C ) are formed for the finger of the lower transistor Tc. Those skilled in the art will recognize that in cases of large cascade stack height, there can be a large difference between the number of breaks in gate polysilicon patterns of lower transistor fingers and higher transistors in the stack. If desired, such a large difference can be achieved by inserting adjacent body junctions without breaks into adjacent gate polysilicon structures, such as described above with reference to FIG 21A can be reduced, effectively resetting the above-described doubling of the number of body stripes at each transistor level.

Finally, those skilled in the art will appreciate that the various semiconductor structures shown in the above figures can be designed in a variety of patterns, some of which have symmetries with respect to different axes, as discussed, for example, with respect to the centerline C _L from 22-24 . 27 . 28 and 29B , can have. According to some example embodiments of the present disclosure, such may be Semiconductor structures (also) symmetrical with respect to a center line C ' _L , which runs through the middle regions of the fingers of the cascode transistors along the length of the fingers, as in 29B is shown.

Those skilled in the art will appreciate the cost advantages of the reduced physical size of the cascode configurations that result from the smaller spacing that results from the different ones discussed above with reference to FIG 20A-28 described adjacent body connections results. Such physical size reduction can also provide performance benefits for RF circuits. For an application that requires a large number of transistor fingers, the closer proximity of the fingers allows shorter connection lengths to connect them. Excessive connection lengths needed to connect a large number of transistor fingers can introduce parasitic capacitance, resistance, and inductance, which can degrade RF performance.

Such semiconductor devices, including the cascode configuration discussed above, which are provided with the improved body interconnect construction according to the various teachings of the present disclosure may be used, for example, in radio frequency (RF) amplifiers having RF power amplifiers and RF mobile power amplifiers. but are not limited thereto, which operate in different classes of operation, which include, but are not limited to, the switching classes D, E and F, the saturated classes B and C, and the linear classes A and A / B.

It should be noted that while the various exemplary embodiments according to the present disclosure have been provided by way of an exemplary case of an N-type SOI MOSFET, such an exemplary case has been provided for purposes of illustration only. The various embodiments of the adjacent body interconnect of the present invention may equally be applied to other types of transistors and other transistor technologies, particularly where the source and / or drain regions extend to an insulating layer such as a BOX layer of an SOI device extend down.

The term "MOSFET" refers specifically to metal oxide semiconductors; a synonym for MOSFET is "MISFET" for metal-insulator-semiconductor or metal-insulator-semiconductor FET. However, "MOSFET" has become commonplace for most types of insulated gate FETs ("IGFETs") and insulated gate field effect transistors, respectively. Nevertheless, it is known that the term "metal" in the terms MOSFET and MISFET is nowadays often a misnomer because the former metal gate material is now often a layer of polysilicon (polycrystalline silicon). Similarly, "oxide" in the term MOSFET may be a misnomer because various dielectric materials are used with the goal of obtaining strong channels with smaller applied voltages. Accordingly, the term "MOSFET" in the present application is not to be construed as being literally limited to metal oxide semiconductors, but instead includes IGFETs in general.

It will be readily apparent to those skilled in the art that various embodiments of the invention may be implemented to meet a wide variety of specifications. Unless otherwise stated above, the selection of suitable component values will depend on design choice, and various embodiments of the invention may be implemented in any suitable IC technology (including, but not limited to, MOSFET and IGFET structures). Integrated circuit embodiments may be fabricated using any suitable substrates and processes, including standard "bulk" silicon, silicon on insulator (SOI), silicon on sapphire, and silicon on sapphire (U.S. SOS), GaAs pHEMT and MESFET technologies, but not limited thereto. However, the inventive concepts described above are particularly useful in an SOI-based manufacturing process (including SOS) and in manufacturing processes with similar properties. Manufacture in CMOS on SOI or SOS enables low power consumption, the ability to withstand high power signals in operation due to FET stacking, good linearity and high frequency operation (above about 10 GHz, and especially above about 20 GHz). Monolithic IC implementation is particularly useful because parasitic capacitances can generally be kept low through careful design.

Depending on a particular specification and / or implementation technique (eg NMOS, PMOS or CMOS and transistor devices with enhanced mode or depletion mode) voltage levels may be set or voltage and / or logic signal polarities reversed. Component voltage, current, and power handling capabilities can be adjusted as needed, for example, by adjusting device sizes, by serially "stacking" components (especially FETs) to withstand greater voltages, and / or by using multiple components in parallel to larger ones Handle flows. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and / or to provide additional functions, without significantly altering the functionality of the disclosed circuits.

Applications that may include the novel device and systems of various embodiments include electronic circuits used in high-speed computing, communications and signal processing circuitry, modems, single or multi-processor modules, single or multiple embedded processors, data switches, and application-specific ones Modules, including multi-layer and multi-chip modules. Such devices and systems may further be included as subcomponents in a variety of electronic systems, such as televisions, cell phones, personal computers (eg, laptops, desktops, handheld computers, tablets, etc.), workstations, radios, video players, audio players (eg, Mp3 players ), Vehicles, medical devices (eg cardiac monitor, blood pressure monitor, etc.) and others. Some embodiments may include a number of methods.

It may be possible to perform the acts described herein in a different order than that described. Various acts described with respect to the methods identified herein may be repeated, sequential, or parallel.

The accompanying drawings, which form a part hereof, by way of illustration and not limitation, show specific embodiments in which the subject matter may be implemented. The illustrated examples are described in sufficient detail to enable those skilled in the art to practice the teachings disclosed herein. Other embodiments may be used and derived therefrom so that structural and logical substitutions and changes may be made without departing from the scope of the present disclosure. The present detailed description is therefore not to be considered in a limiting sense, and the scope of various embodiments is defined only by the appended claims, along with the full scope of equivalents to which these claims are entitled.

Such embodiments of the subject invention may be used herein for convenience, alone or in conjunction with the term "invention," without intending to deliberately limit the scope of the present application to a single invention or concept alone, when more than one disclosed is. Although specific embodiments have been illustrated and described herein, any arrangement that is believed to achieve the same purpose may be substituted for the specific embodiments shown. It is intended that the present disclosure include all adaptations or variations of various embodiments. Combinations of the above embodiments and other embodiments not specifically described herein will become apparent to those skilled in the art upon reading the above description.

The abstract of the present disclosure is provided to teach 37 C.F.R. §1.72 (b) where it is required that a summary allows the reader to quickly determine the nature of the technical disclosure. It is presented with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In the foregoing detailed description, various features are grouped together in a single embodiment to streamline the disclosure. This disclosure process should not be construed as requiring more features than are expressly recited in each claim. Rather, an inventive subject matter may be found in less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the detailed description, with each claim being separate as a separate embodiment.

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited patent literature

• US 14945323 [0001]

Claims (55)

Semiconductor structure comprising: a first gate polysilicon structure defining a first body region, the first body region having a first conductivity type; a second gate polysilicon structure defining a second body region, the second body region having the first conductivity type; a first drain region adjacent to the first body region having a second conductivity type; a first source region adjacent to the first body region having the second conductivity type; a second source region adjacent to the second body region having the second conductivity type; a second drain region adjacent to the second body region having the second conductivity type, wherein the first source region and the second drain region define a first common source / drain region having the second conductivity type; a first non-conductive isolation region configured to form an interruption in the second body region to separate the second body region into two separate body regions; at least one first body contact region of the first conductivity type formed in the first common source / drain region separate from the first and second body regions and abutting the first non-conductive isolation region; and at least one first body stripe of the first conductivity type extending over the first common source / drain region in contact with the first body region and the at least one first body contact region, wherein the first nonconductive isolation region, the at least one first body contact region, and the at least one first body stripe define a first adjacent body interconnect structure. Semiconductor structure after Claim 1 wherein the first non-conductive isolation region is further configured to expand a silicon region of the first common source / drain region to provide a region of contiguous silicon for the at least one first body contact region and the at least one first body strip. Semiconductor structure after Claim 1 or Claim 2 wherein the first non-conductive isolation region is further configured to form an interrupt in the second source region to divide the source region into two separate second source regions. Semiconductor structure after Claim 1 or Claim 2 wherein the length of the at least one first body strip is greater than the length defined by a distance between the first body region and the second body region. Semiconductor structure after Claim 1 wherein the first body strip extends in a direction perpendicular to a direction defined by the first and second body regions along the width of the body regions. Semiconductor structure after Claim 1 , further comprising: at least one second body contact region of the first conductivity type separated from the first and second body regions; and at least one second body stripe of the first conductivity type extending into the second source region and in contact with one of the two separate second body regions and the at least one second body contact. Semiconductor structure after Claim 6 , further comprising: an additional second body contact region of the first conductivity type separate from the first and second body regions; and an additional second body stripe of the first conductivity type extending into the second source region and in contact with the other of the two separate body regions. Semiconductor structure after Claim 6 or Claim 7 wherein the at least one second body contact region is formed in the second source region such that it is laterally surrounded by the second source region. Semiconductor structure after Claim 6 or Claim 7 wherein the at least one second body contact region is applied to the second source region. Semiconductor structure after Claim 9 wherein the at least one second body contact region and the additional second body contact region form a contiguous silicon region. Semiconductor structure according to one of Claims 1 . 2 or 6 wherein the first and second gate polysilicon structures each define fingers of a first and a second transistor arranged in a cascode configuration. Semiconductor structure after Claim 11 further comprising: an additional first finger of the first transistor; an additional second finger of the second transistor; and an additional first adjacent body connection structure, comprising: i) an additional first body contact region; ii) an additional first body strip; and iii) the first nonconductive isolation region, wherein the additional first finger, the additional second finger, and the additional first adjacent body interconnect structure are mirrored about a centerline of the semiconductor structure with respect to the first finger, the second finger, and the first adjacent body interconnect structure is defined by a center region of the second source region along the width of the second source region, wherein the second source region is a common source region for the second finger and the additional second finger. Semiconductor structure after Claim 1 further comprising: a third gate polysilicon structure defining a third body region of the first conductivity type; a third drain region adjacent to the third body region having the second conductivity type, the third drain region and the second source region defining a second common drain / source region having the second conductivity type; and a third source region adjacent to the third body region having the second conductivity type; wherein the first non-conductive isolation region is further configured to form an interruption in the third body region and the second common source / drain region to form the third body region and the second common source / drain region, respectively, into two separate third body regions and two separate ones separate second common source / drain regions. Semiconductor structure after Claim 13 10, further comprising a second adjacent body connection configuration, the second adjacent body connection configuration comprising: a second non-conductive isolation region configured to form an interruption in one of the two separate third body regions; a second body contact region of the first conductivity type formed in a region of the second common source / drain region separate from the second and third body regions and abutting the second non-conductive isolation region; and a second body stripe of the first conductivity type extending over a portion of the second common source / drain region in contact with one of the two separate second body regions and the second body contact region, wherein the region of the second common source / drain region is one of the two separate second common source / drain regions adjacent to the one of the two separate second body regions. Semiconductor structure after Claim 14 wherein the second nonconductive isolation region is further configured to expand a silicon region of the second common source / drain region to provide a region of contiguous silicon for the second body contact region and the second body stripe. Semiconductor structure after Claim 14 or Claim 15 wherein the second non-conductive isolation region is further configured to form an interrupt in the third source region to divide the source region into two separate third source regions. Semiconductor structure after Claim 14 or Claim 15 wherein the length of the at least one second body strap is greater than the length defined by a distance between the second body region and the third body region. Semiconductor structure after Claim 14 wherein the second body strip extends in a direction perpendicular to a direction defined by the second and third body regions. Semiconductor structure after Claim 14 further comprising an additional second adjacent body-connection configuration associated with the other of the two separate second body regions. Semiconductor structure after Claim 19 wherein the additional second adjacent body connection comprises: an additional second non-conductive isolation region configured to form an interruption in the other of the two separate third body regions; an additional second body contact region of the first conductivity type that is separate from the second and third body regions in a region of the second common source / drain region and abuts the additional second non-conductive isolation region; and an additional second body stripe of the first conductivity type extending over a portion of the second common source / drain region in contact with the other of the two separate second body regions and the additional second body contact region, the region of the second common source / drain region one of the two separate second common source / drain regions is adjacent to the other of the two separate second body regions. Semiconductor structure after Claim 20 wherein the additional second non-conductive isolation region is further configured to expand a silicon region of the second common source / drain region to provide a region of contiguous silicon for the additional second body contact region and the additional second body strip. Semiconductor structure after Claim 20 or Claim 21 wherein the additional second non-conductive isolation region is further configured to form an interrupt in the third source region to further divide the source region into further separate source regions. Semiconductor structure after Claim 20 or Claim 21 wherein the length of the additional second body strip is greater than the length defined by a distance between the second body region and the third body region. Semiconductor structure after Claim 20 wherein the additional second body strip extends in a direction perpendicular to a direction defined by the second and third body regions. Semiconductor structure after Claim 19 10, further comprising at least one third adjacent body connection structure associated with one of the separate third body regions, the at least one third adjacent body connection structure comprising: a third body contact region of the first conductivity type separate from the second and third body regions; and a third body stripe of the first conductivity type extending over the third source region and in contact with one of the separate third body regions and the third body contact region. Semiconductor structure after Claim 25 further comprising a plurality of third adjacent body interconnect structures each associated with a different third body region of the separate third body regions. Semiconductor structure after Claim 25 or Claim 26 wherein the third body contact region is formed in the third source region such that it is laterally surrounded by the third source region. Semiconductor structure after Claim 26 wherein the at least one third body contact region of the plurality of third adjacent body connection structures is applied to the third source region. Semiconductor structure after Claim 28 wherein two or more third body contact regions of the plurality of third adjacent body connection structures form a contiguous silicon region. Semiconductor structure according to one of Claims 14 . 19 . 25 and 26 wherein the first, second and third gate polysilicon structures each form fingers of a first, a second and a third transistor arranged in a cascode configuration. Semiconductor structure after Claim 30 further comprising: an additional first finger of the first transistor; an additional second finger of the second transistor; an additional third finger of the third transistor; at least one additional first adjacent body connection structure, comprising: i) an additional first body contact region; ii) an additional first body strip; and iii) the first non-conductive isolation region; and at least one additional second adjacent body interconnect structure, comprising: iv) an additional second body contact region; v) an additional second body strip; and vi) the second non-conductive isolation region; wherein the additional first finger, the additional second finger, the additional third finger, the additional first adjacent body connection structure, and the additional second adjacent body connection structure with respect to the first finger, the second finger, the third finger, the first adjacent body connection structure and the second adjacent body interconnect structure is mirrored about a centerline of the semiconductor structure defined by a center region of the third source region along the width of the third source region, the third source region being a common source region for the third finger and the additional third finger. A semiconductor structure comprising: at least two instantiations of the semiconductor structure Claim 12 which are mirrored about a centerline of the first drain regions of the first fingers of the at least two instantiations, the centerline being along a width of the first drain regions forming a common first drain region, the semiconductor structure further comprising: a first perpendicular polysilicon structure connecting the first gate polysilicon structures of the at least two instantiations at a first end of the first gate polysilicon structures, the first perpendicular polysilicon structure including one below lying common body area defined for the first body areas of the at least two instantiations; and a first horizontal polysilicon structure extending from a midpoint of the first perpendicular polysilicon structure through a first edge of a silicon region of the semiconductor structure, wherein the first horizontal polysilicon structure extends the underlying common body region to the first edge of the silicon region. Semiconductor structure after Claim 32 semiconductor device comprising: a second orthogonal polysilicon structure connecting the first gate polysilicon structures of the at least two instantiations at a second end of the first gate polysilicon structures, the second perpendicular polysilicon structure including an underlying common body region for the first body regions of the at least two instantiations Are defined; and a second horizontal polysilicon structure extending from a midpoint of the second perpendicular polysilicon structure through a second edge of the silicon region of the semiconductor structure opposite the first edge, wherein the second horizontal polysilicon structure extends the underlying common body region to the second edge of the silicon region. A semiconductor structure comprising: at least two instantiations of the semiconductor structure Claim 31 which are mirrored about a centerline of the first drain regions of the first fingers of the at least two instantiations, the centerline being along a width of the first drain regions forming a common first drain region, the semiconductor structure further comprising: a first perpendicular polysilicon structure connecting the first gate polysilicon structures of the at least two instantiations to a first end of the first gate polysilicon structures, the first perpendicular polysilicon structure defining an underlying common body region for the first body regions of the at least two instantiations; and a first horizontal polysilicon structure extending from a midpoint of the first perpendicular polysilicon structure through a first edge of a silicon region of the semiconductor structure, wherein the first horizontal polysilicon structure extends the underlying common body region to the first edge of the silicon region. Semiconductor structure after Claim 34 , further comprising: a second orthogonal polysilicon structure connecting the first gate polysilicon structures of the at least two instantiations at a second end of the first gate polysilicon structures, the second perpendicular polysilicon structure including an underlying common body region for the first body regions of the at least two instantiations Are defined; and a second horizontal polysilicon structure extending from a midpoint of the second perpendicular polysilicon structure through a second edge of the silicon region of the semiconductor structure opposite the first edge, the second horizontal poly-silicon structure extending from the underlying common body region to the second edge of the silicon region extended. Semiconductor structure after Claim 11 in which the transistors of the cascode configuration are metal-oxide-semiconductor field-effect transistors (MOSFETs). Semiconductor structure after Claim 36 wherein the transistors are produced by a technology according to one of: a) silicon on insulator or silicon-on-insulator (SOI) technology and b) silicon on sapphire or silicon-on-sapphire (SOS) technology. Semiconductor structure after Claim 30 , wherein the transistors are metal-oxide-semiconductor field effect transistors or metal-oxide-semiconductor field effect transistors (MOSFETs). Semiconductor structure after Claim 38 wherein the transistors are produced by a technology according to one of: a) silicon on insulator or silicon-on-insulator (SOI) technology and b) silicon on sapphire or silicon-on-sapphire (SOS) technology. Semiconductor structure after Claim 36 adapted for use as an amplifier in an application selected from a group consisting of: a) a radio frequency (RF) amplifier, b) an RF power amplifier, c) an RF mobile power amplifier, d) a RF switching power amplifier, e) a CMOS (Complementary Metal-Oxide-Semiconductor) RF power amplifier, and f) a CMOS RF mobile power amplifier. Semiconductor structure after Claim 40 wherein the operating class of the amplifier is one or more of: i) linear class A, ii) linear class A / B, iii) saturated class B, iv) saturated class C, v) class D, vi) class E, and vii ) Switching class F. Semiconductor structure after Claim 38 designed for use as an amplifier in an application selected from a group consisting of: a) a radio frequency (RF) Amplifier, b) an RF power amplifier, c) an RF mobile power amplifier, d) an RF switching power amplifier, e) a CMOS (Complementary Metal-Oxide-Semiconductor) RF power amplifier, and f) a CMOS RF mobile radio power amplifiers. Semiconductor structure after Claim 42 wherein the operating class of the amplifier is one or more of: i) linear class A, ii) linear class A / B, iii) saturated class B, iv) saturated class C, v) class D, vi) class E, and vii ) Switching class F. A semiconductor structure comprising a plurality of transistors, the semiconductor structure comprising: an insulating layer; a silicon layer overlying the insulating layer; active regions formed in the silicon layer, the active regions extending through the silicon layer to contact the insulating layer, the active regions having body regions, source regions, and drain regions of one or more fingers of each transistor of the plurality of transistors formed as cascode stacks for each two consecutive transistors of the cascode stack, a source region of a finger of an upper transistor and the drain region of a finger of a lower transistor of each two consecutive transistors in a common source / drain region of the silicon layer are trained; and at least one adjacent body connection structure associated with the upper finger and comprising: i) a non-conductive isolation region; ii) a body contact region formed in the common source / drain region of the fingers of two consecutive transistors separate from the body regions of the fingers and abutting an isolation region of the non-conductive isolation region; and iii) a body stripe region formed in the silicon layer in contact with the body region of the finger of the upper transistor and the body contact region, wherein the at least one non-conductive isolation region is configured to: Forming an interruption in a region of the silicon layer defining the body region of the finger of the lower transistor to divide the body region into separate body regions, and Expanding the interruption into a region of the silicon layer that defines body regions and common source / drain regions of fingers of one or more consecutive transistors adjacent to the bottom transistor to divide the regions into separate regions. Semiconductor structure after Claim 44 and further comprising: additional adjacent body interconnect structures associated with the lower finger, wherein the body stripe region of each of the additional adjacent body interconnect structures is in contact with a separate body region of the finger of the lower transistor. Semiconductor structure after Claim 45 wherein: each finger of a transistor of the plurality of transistors has a number of associated adjacent body interconnect structures equal to a number of separate body regions of the respective finger, and the body stripe region of each of the associated adjacent body interconnect structures having a separate body region of the respective finger is in contact. Semiconductor structure after Claim 44 or Claim 45 wherein: the cascode stack comprises a first upper transistor and a last lower transistor; each transistor of the plurality of transistors of the cascode stack has two or more fingers; and regions of any two fingers of the respective transistor are mirrored about a centerline defined by a center region of a common source region along a width of the common source region, the common source region being the source region of two fingers of the last bottom transistor. Semiconductor structure after Claim 47 wherein the semiconductor structure is symmetrical with respect to the centerline. Semiconductor structure after Claim 47 wherein each finger of the first upper transistor has one and only one associated adjacent body connection structure. Semiconductor structure after Claim 47 wherein each finger of a transistor adjacent to the first upper transistor has one and only one associated adjacent body connection structure. Semiconductor structure after Claim 50 wherein regions of any two fingers of the respective transistor are further mirrored about a centerline defined by a center region of a common drain region along a width of the common drain region, the common drain region being the drain region of two fingers of the first top transistor, wherein the two fingers comprise a first upper finger and a second upper finger, the semiconductor structure further comprising: a vertical polysilicon structure connecting the gate polysilicon structures of the first and second upper fingers, the vertical polysilicon structure defining an underlying common body region for the body regions of the first and second upper fingers; and a horizontal polysilicon structure extending from a midpoint of the perpendicular polysilicon structure through an edge of a silicon region of the semiconductor structure, wherein the horizontal polysilicon structure extends the underlying common body region to the edge of the silicon region. Semiconductor structure after Claim 51 wherein the semiconductor structure is symmetrical with respect to a centerline passing through the center of the one or more fingers of each transistor of the plurality of transistors along the length of the one or more fingers. Semiconductor structure after Claim 48 wherein the semiconductor structure is symmetrical with respect to a centerline passing through the center of the one or more fingers of each transistor of the plurality of transistors along the length of the one or more fingers. Semiconductor structure after Claim 49 wherein the semiconductor structure is symmetrical with respect to a centerline passing through the center of the one or more fingers of each transistor of the plurality of transistors along the length of the one or more fingers. A method of providing a body connection for transistors arranged in a cascode configuration comprising: a first gate polysilicon structure defining a first body region, the first body region having a first conductivity type; a second gate polysilicon structure defining a second body region, the second body region having the first conductivity type; a first drain region adjacent to the first body region having a second conductivity type; a first source region adjacent to the first body region having the second conductivity type; a second source region adjacent to the second body region having the second conductivity type; a second drain region adjacent to the second body region having the second conductivity type, and wherein the first source region and the second drain region define a first common source / drain region having the second conductivity type; the method comprising: Forming, by means of a first non-conductive isolation region, an interruption in the second body region to separate the second body region into two separate body regions; Forming at least one first body contact region of the first conductivity type in the first common source / drain region separated from the first and second body regions applied to the first non-conductive isolation region; and Forming at least a first body stripe of the first conductivity type extending over the first common source / drain region in contact with the first body region and the at least one first body contact region, wherein the first nonconductive isolation region, the at least one first body contact region, and the at least one first body stripe define a first adjacent body interconnect structure.

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