CN109314132A

CN109314132A - Docking body contacts for SOI transistor

Info

Publication number: CN109314132A
Application number: CN201680085521.9A
Authority: CN
Inventors: 西蒙·爱德华·威拉德
Original assignee: PIC
Current assignee: PIC; PSemi Corp
Priority date: 2016-03-23
Filing date: 2016-06-29
Publication date: 2019-02-05
Anticipated expiration: 2036-06-29
Also published as: CN109314132B; SG11201807808WA; WO2017164904A1; DE112016006634T5; CN114122141A

Abstract

Describe system, the method and apparatus for improved ontology connection construction.Improved ontology connection construction is configured at transistor " cut-off " (Vg is about 0 volt) that there are the connections of lower resistor main body.As transistor " conducting " (Vg > Vt), to ontology link resistance it is much higher, thus reduce with ontology connection there are associated performance loss.Also describe the effective ontology connection construction in space suitable for cascode configuration in FIG.

Description

Docking body contacts for SOI transistor

Cross reference to related applications

U. S. application the 14/945th, 323 submitted in the application and on November 18th, 2015 is related, in the disclosure of this application The full content of appearance is incorporated herein by reference.

Technical field

Various embodiments described herein relate generally to system for inhibiting the floater effect in semiconductor devices, Method and apparatus.

Background technique

Due to the hot carrier of accumulation --- the electricity of its body regions that can increase silicon-on-insulator (SOI) transistor Position --- floating body silicon-on-insulator (SOI) transistor is restricted in terms of operation voltage and power.With floating body SOI transistor phase Than ontology connection (tied) SOI transistor has been shown that voltage and power handling capability can be extended.

For being greater than about 3.2 volts of drain-source voltage (Vds), floating body SOI transistor has been shown non-conductive hot current-carrying Son drift (for example, in the non-conducting state when, the size of threshold voltage reduces, and drain current increases).Ontology connector Part has been shown not suffering from this mechanism.

It is corresponding floating under the appropriateness biasing of the drain-source voltage of the various levels of transistor when floating body transistor conduction The output impedance that bulk effect may cause transistor reduces suddenly, this then may be decreased the analog gain of transistor, and increase The complexity for adding corresponding device to model.Ontology coupler (transistor) inhibits the reduction of output impedance, and for higher Drain-source voltage extends the range of more high output impedance.

Ontology connection on width (big grid width) transistor with routine (H grid, T grid) ontology connecting structure Become to be less effective in terms of inhibiting the device degradation due to caused by high resistance and increased parasitic capacitance, the high resistance and increasing The parasitic capacitance added reduces the ability of control floater effect.Particularly, for big transistor width, conventional bulk connector Part (for example, H grid, T grid) is less effective in terms of inhibiting such deterioration, and in the application using such transistor Such as in the application of radio frequency (RF) amplifier, the increased drain-gate capacitance property of may be decreased associated with conventional bulk coupler Energy.

Although ontology links the voltage handling ability that transistor can be improved, the on state electric conductivity of the transistor It can may be decreased.

Summary of the invention

It may be desirable to extending semiconductor devices such as RF integrated circuit (IC) by providing improved ontology connection construction Voltage and power handling capability.Such semiconductor devices may include metal-oxide semiconductor (MOS) (MOS) field effect transistor Manage (FET), complementary metal oxide semiconductor (CMOS) FET, especially silicon (SOI) substrate and silicon on sapphire on insulator (SOS) MOSFET and CMOSFET manufactured on substrate.Connect equipped with the improved ontology of the various teachings according to present disclosure Such semiconductor devices that structure is made can for example be used for radio frequency (RF) amplifier, which includes but unlimited In the RF power amplifier and honeycomb RF power amplifier that are operated under various class of operations, the various class of operations include but It is not limited to switch classification D, E and F, saturation classification B and C and linear classification A and A/B.

According to present disclosure in a first aspect, proposing a kind of semiconductor structure, which includes: the first grid Pole polysilicon structure, limits the first noumenon region, and the first noumenon region has the first conduction type；Second grid polysilicon knot Structure, limits the second body regions, and the second body regions have the first conduction type；First drain region, with the first noumenon Region is adjacent, has the second conduction type；First source region, it is adjacent with the first noumenon region, there is the second conduction type； Second source region, it is adjacent with the second body regions, there is the second conduction type；Second drain region, with the second ontology Region is adjacent, has the second conduction type；First source region and the second drain region limit the first public source/drain region Domain, the first public source/drain region have the second conduction type；First non-conductive area of isolation, is configured to second It is formed and is interrupted in body regions, the second body regions are divided into two sseparated second body regions；With the first conductive-type At least one the first noumenon contact area of type, at least one described the first noumenon contact area is in the first public source/drain electrode It is formed in region, is separated with the first noumenon region and the second body regions and abut the first non-conductive area of isolation；And tool There is at least one the first noumenon protruding portion (tab) of the first conduction type, at least one described the first noumenon protruding portion is across first Public source/drain region extends, and contacts with the first noumenon region and at least one the first noumenon contact area, wherein first Non-conductive area of isolation, at least one the first noumenon contact area and at least one the first noumenon protruding portion limit the first docking (butted) ontology connecting structure.

According to the second aspect of the present disclosure, a kind of semiconductor structure including multiple transistors is described, this is partly led Body structure includes: insulating layer；Cover the silicon layer of insulating layer；The active region formed in a layer of silicon, active region extend through silicon For layer to contact with insulating layer, active region includes the sheet of one or more fingers of each transistor in multiple transistors Body region, source region and drain region, multiple transistors are configured as the cascade arranged from the top to the bottom stacking, In, for the successive transistor of every two that cascade stacks, the finger of the top transistor in the successive transistor of every two Source region and the drain region of finger of bottom transistor formed in public source/drain region of silicon layer；And At least one docking ontology connecting structure associated with top finger, comprising: i) non-conductive area of isolation；Ii) ontology connects Region is touched, is formed in public source/drain region of the finger of two successive transistors, the body regions with finger Separate and abut the area of isolation of non-conductive area of isolation；And iii) ontology protruding portion region, it is formed in a layer of silicon, with The body regions of the finger of top transistor and body contact region contact, wherein at least one non-conductive area of isolation quilt It is configured to: being formed and interrupted in the region of the body regions of the finger of the restriction bottom transistor of silicon layer, by the ontology Region is divided into separated body regions, and extends the restriction one or more successive crystalline substances adjacent with bottom transistor of silicon layer The region is divided into and separating by the interruption in the body regions and public source/drain region region of the finger of body pipe Region.

According to the third aspect of present disclosure, provide a kind of for being mentioned to the transistor arranged with cascode configuration in FIG For the method for ontology connection, which includes: first grid polysilicon structure, limits the first noumenon region, the One body regions have the first conduction type；Second grid polysilicon structure limits the second body regions, the second body regions With the first conduction type；First drain region, it is adjacent with the first noumenon region, there is the second conduction type；First source electrode Region, it is adjacent with the first noumenon region, there is the second conduction type；Second source region, it is adjacent with the second body regions, With the second conduction type；Second drain region, it is adjacent with the second body regions, there is the second conduction type, the first source electrode Region and the second drain region limit the first public source/drain region, and the first public source/drain region has the second conduction Type；This method comprises: interruption is formed in the second body regions by the first non-conductive area of isolation, by the second body zone Domain is divided into two sseparated second body regions；Being formed in the first public source/drain region has the first conduction type At least one the first noumenon contact area, at least one described the first noumenon contact area and the first noumenon region and the second ontology Region separates and abuts the first non-conductive area of isolation；And form at least one the first noumenon with the first conduction type Protruding portion, at least one described the first noumenon protruding portion extend across the first public source/drain region, with the first noumenon region and At least one the first noumenon contact area contact, wherein the first non-conductive area of isolation, at least one the first noumenon contact area And at least one the first noumenon protruding portion limits the first docking ontology connecting structure.

Detailed description of the invention

It is incorporated into and the attached drawing formed part of this specification shows one or more realities of present disclosure Mode is applied, and with the description of example embodiment together for illustrating the principle and implementation of present disclosure.

Figure 1A shows the top view of N-type mosfet transistor device.

Figure 1B shows the sectional view of the A along the line of the transistor device in Figure 1A.

Fig. 1 C shows schematically showing for the transistor device of Figure 1A.

Fig. 2A shows the N-type mosfet transistor device with the connection of T grid ontology according to prior art embodiment The top view of part.

Fig. 2 B shows schematically showing for the transistor device of Fig. 2A.

Fig. 2 C shows the N-type mosfet transistor device with the connection of H grid ontology according to prior art embodiment The top view of part.

Fig. 3 A shows the N-type mosfet transistor device with source-body connection according to prior art embodiment Top view.

Fig. 3 B shows schematically showing for the transistor device of Fig. 3 A.

Fig. 4 A shows the N-type mosfet transistor with docking body contacts according to the embodiment of the present disclosure Top view.

Fig. 4 B shows the sectional view of the B along the line of the transistor device in Fig. 4 A.

Fig. 5 A shows the N-type MOSFET crystalline substance with docking body contacts of the alternative embodiment according to present disclosure The top view of body pipe.

Fig. 5 B shows the sectional view of the C along the line of the transistor device in Fig. 5 A.

Fig. 5 C shows schematically showing for the transistor device of Fig. 4 A and Fig. 5 A.

Fig. 6 shows the N-type MOSFET crystalline substance with docking body contacts of the alternative embodiment according to present disclosure The top view of body pipe, wherein body contacts are provided via multiple and different ontology protruding portions.

Fig. 7 A and Fig. 7 B show the top view of the alternative embodiment of embodiment shown in Fig. 6.

Fig. 8 A shows the two of the transistor device with docking body contacts according to the embodiment of the present disclosure The top view of a adjacent finger part, wherein corresponding polysilicon protrusion creation is in public source region.

Fig. 8 B shows the alternative embodiment of embodiment shown in Fig. 8 A, wherein corresponding polysilicon protrusion It is engagement.

Fig. 8 C to Fig. 8 H shows the stacking with docking body contacts of the various embodiments according to present disclosure The top view of transistor.

Fig. 8 I schematically shows the stacked transistors of Fig. 8 C and Fig. 8 D.

Fig. 8 J schematically shows the stacked transistors of Fig. 8 E.

Fig. 8 K schematically shows the stacked transistors of Fig. 8 F.

Fig. 9 A shows the top view of the transistor of the docking body contacts with isolation.

Fig. 9 B shows the sectional view of the F along the line of the transistor device in Fig. 9 A.

Fig. 9 C shows the top view of two adjacent finger parts of the transistor device of the docking body contacts with isolation.

Fig. 9 D shows schematically showing for the transistor device of Fig. 9 A to Fig. 9 B.

Figure 10 A indicates the figure of docking ontology connection (contact) resistance and gate bias voltage and ontology protruding portion width.

Figure 10 B is shown to two floating body transistors and with the docking sheet according to the various embodiments of present disclosure The figure that drain-source current under the off state of two transistors of body connection is compared.

Figure 11 A and Figure 11 B show with docking ontology connection according to the embodiment of the present disclosure and do not have The drain-source current for the transistor device identical in other respects for thering is ontology to link and the figure of drain-source voltage.

Figure 12 A to figure 12 C shows the number for indicating the ontology protruding portion of docking ontology connection transistor according to the present invention The figure of influence of the mesh to drain-source current and the drain-source voltage response of identical transistor device.

Figure 12 D shows the output for indicating the ontology connection transistor device of docking according to various embodiments of the present invention The figure of conductance and the number of ontology protruding portion.

Figure 13 shows the figure for indicating influence of the hot carrier in jection to floating body transistor.

Figure 14 shows the figure for indicating influence of the docking ontology connection according to the present invention relative to hot carrier in jection.

Figure 15 A and Figure 15 B, which are shown, indicates to have the connection of various ontologies and the identical transistor without ontology connection Total grid capacitance and drain-gate capacitance comparison diagram.

Figure 16 A to Figure 16 B, which is shown, indicates docking ontology connection according to the present invention to the f of transistor_TFrequency and f_maxFrequently The comparison diagram of the influence of rate.

Figure 17 shows indicate docking ontology connection according to the present invention to the adjacency channel leakage ratio of RF power amplifier The comparison diagram of the influence of performance.

Figure 18, which is shown, indicates docking ontology according to the present invention connection to being in identical under relatively high voltage bias The comparison diagram of the influence of the gain and output power (Pout) of transistor under biasing.

Figure 19, which is shown, to be indicated to connect the docking ontology according to the present invention of the given output power of RF power amplifier The comparison diagram of the influence of peering bias current (Ibias).

Figure 20 A shows schematically showing for the cascode configuration in FIG including two stacked transistors.

Figure 20 B shows schematically showing for the cascode configuration in FIG including three stacked transistors.

Figure 21 A, which is shown, has being provided to by scheming of the case where finger for the transistor of cascode configuration in FIG The top transistor T for the cascode configuration in FIG that 20A is indicated_BAccording to the embodiment of the present disclosure docking ontology connection.

Figure 21 B and Figure 21 D, which are shown, respectively has the case where finger for the transistor of cascode configuration in FIG It is provided to by the top transistor T of Figure 20 A cascode configuration in FIG indicated_BSpace according to the embodiment of the present disclosure Effective docking ontology connection.

Figure 21 C and Figure 21 E are shown for creating respectively for the docking ontology connection described in Figure 21 B and Figure 21 D The method for building body contact region.

Figure 22 show the case where respectively having the transistor of cascode configuration in FIG there are two finger be provided to by The top transistor T for the cascode configuration in FIG that Figure 20 A is indicated_BSpace according to the embodiment of the present disclosure it is effectively right Connect ontology connection.Figure 22, which is shown, is provided to top transistor T_BSuch space of each finger effectively dock ontology Connection.

Figure 23 show the case where respectively having the transistor of cascode configuration in FIG there are two finger be provided to by The top transistor T for the cascode configuration in FIG that Figure 20 B is indicated_ESpace according to the embodiment of the present disclosure it is effectively right Connect ontology connection.Figure 23, which is shown, is provided to top transistor T_ESuch space of each finger effectively dock ontology Connection.

Figure 24 show the case where respectively having the transistor of cascode configuration in FIG there are two finger be provided to by The top transistor T for the cascode configuration in FIG that Figure 20 B is indicated_EFinger docking according to the embodiment of the present disclosure Ontology connection.

Figure 25 is shown by a part of Figure 20 A cascode configuration in FIG indicated, which has according to Fig. 8 B and Figure 22 The transistor for being provided to cascode configuration in FIG various fingers docking ontology connection.

Figure 26 is shown by a part of Figure 20 B cascode configuration in FIG indicated, the part have according to Fig. 8 B, Figure 22 with And the docking ontology connection of the various fingers of the transistor for being provided to cascode configuration in FIG of Figure 23.

Figure 27 is shown by the full duration structure of Figure 20 B cascode configuration in FIG indicated, which has root Docking ontology according to the various fingers of the transistor for being provided to cascode configuration in FIG of Fig. 8 B, Figure 22, Figure 23 and Figure 24 connects Knot.

Figure 28 is shown by the full duration structure of Figure 20 B cascode configuration in FIG indicated, which has root According to the docking ontology connection of the various fingers of the transistor for being provided to cascode configuration in FIG of Fig. 8 B, Figure 22 and Figure 23.

Figure 29 A shows schematically showing for the cascode configuration in FIG including four stacked transistors.

Figure 29 B show by Figure 29 A indicate have according to Fig. 8, Figure 22, Figure 23 and Figure 24 docking ontology connection The full duration structure of cascode configuration in FIG, wherein to the top transistor T of cascode configuration in FIG_EDocking ontology connection only 4 docking ontology connection according to fig. 2.

Specific embodiment

Embodiment and modification are described for the purpose for using and realizing for illustrating inventive concept through this specification. Illustrative description should be understood that the example of inventive concept is presented, rather than limit the range of concepts disclosed herein.

Following device is described in this disclosure, which provides conventional bulk and link semiconductor devices such as H grid Pole MOSFET element and T gate MOSFET device are benefited, without limitation associated with these constructions and deterioration.Also Describe the method for manufacturing and using such device.

According to the various embodiments of present disclosure, the docking body contacts in semiconductor devices can improve semiconductor The operating characteristics of device.As it is used herein, stating " docking body contacts ", " connection of docking ontology " and " docking ontology company Knot " it is equivalent, and these statements are related to according to present disclosure in following paragraph by means of various corresponding Attached drawing and describe for semiconductor devices provide ontology link various method and apparatus.In the exemplary of transistor device In the case of, such docking ontology connection can be provided in the following manner: via having desired conductivity (such as resistance Rate) conductive path by the body regions of transistor device " connected " to the source region of transistor device.Alternatively, it docks Ontology connection can be set to for the body regions of transistor device to be linked to any phase provided at open contact portion Opening (open) contact portion of the bulk potential of prestige, the opening contact portion is via the conductive path resistance-type with desired conductivity Ground is connected to the body regions of transistor device.

According to the connection of the docking ontology of the various embodiments of present disclosure one can be provided via to semiconductor devices A little additional structures realize, " ontology protruding portion " that the additional structure for example illustrates by the item (512) in Fig. 5 B, by Fig. 5 A Item (510) illustrate " polysilicon protrusion " and by Fig. 5 A and Fig. 5 B item (540) illustrate " body contact region ". To be further described in following paragraph such structure and with realization dock ontology and linking according to present disclosure Any other related structure.

As it is used herein, ontology protruding portion (for example, item (512) in Fig. 5 B) is more with the grid of semiconductor devices Below crystal silicon structure (for example, item (110) in Fig. 5 A to Fig. 5 B) body regions (for example, item (112) in Fig. 5 B) (that is, Transistor body, transistor channel, transistor conductivity channel) region with same type doping, the ontology protruding portion is from partly Body regions below the gate polysilicon structure of conductor device are branched off (branch out) and abut therewith, and extend To or extend through the source region (for example, item (120) in Fig. 5 A to Fig. 5 B) or drain region of semiconductor devices.? In one illustrative embodiments of present disclosure, such ontology protruding portion can use the grid polycrystalline silicon knot from device Corresponding polysilicon protrusion (for example, item (510) in Fig. 5 A) that structure is branched off creates, and therefore can be grid The component part of polysilicon structure.Polysilicon protrusion is used as mask, to prevent to the semiconductor below polysilicon protrusion The doping in region, to create ontology protruding portion.

As it is used herein, body contact region (for example, item (540) in Fig. 5 A to Fig. 5 B) is and body regions (for example, item (112) in Fig. 5 B) has region of same type doping, and the body contact region is for providing to being applied to The low resistivity conductive path of the expectation current potential of the body regions of device.Therefore, ontology protruding portion is (for example, the item in Fig. 5 B (512)) conductive path between body regions and body contact region with first resistor rate (for example, R1 in Fig. 5 C) is provided Diameter, and body contact region provides and links current potential to desired ontology with second resistance rate (for example, R2 in Fig. 5 C) Conductive path.

It, can be by the way that one or more ontology protruding portions be connected as presented in the following part of present disclosure The docking body contacts of various embodiments according to present disclosure are provided to the body regions of device.According to being described later on Present disclosure various embodiments, such ontology protruding portion contacts with body contact region, the body contact region With the doping with the body regions same type below gate polysilicon structure.According to the various embodiment party of present disclosure Formula, the doping of body contact region, which can have, to be similar to, is dense less than or greater than the association of the association doping concentration of body regions Degree.According to the various embodiments for the present disclosure being described later on, body contact region can with gate polysilicon structure It creates, or can be created in the region of the neighbouring source region adjacent with gate polysilicon structure in adjacent source region It builds.The alternative embodiment that body contact region is in the drain region of semiconductor devices is also possible.

Embodiment as described herein is illustrated by N-type MOSFET element.By optionally applying different type Doped scheme, invention disclosed herein design easily will be applied to other kinds of half by those of ordinary skill in the art Conductor device, such as p-type MOSFET element.Embodiment according to the present invention can also be applied to the drain device of extension, example Such as lateral diffusion metal oxide semiconductor (LDMOS) device and other grid controlled transistors or device.

According to the various embodiments of present disclosure, having the semiconductor devices of docking body contacts may include being formed The semiconductor devices including field effect transistor (FET) on silicon (SOI) on insulator.FET device may include complementary gold Belong to oxide semiconductor (CMOS), Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and other kinds of field-effect Transistor (FET) device.In embodiments, silicon-on-insulator (SOI) may include silicon on sapphire (SOS).

As it is used herein, MOSFET P ontology (for example, item (112) in Fig. 5 B), P ontology, P- body regions with And body regions refer to the P doped silicon below gate polysilicon structure (for example, item (110) in Fig. 5 A to Fig. 5 B), are grasping Conducting channel is provided to MOSFET during work.Body regions and ontology protruding portion (for example, item (512) in Fig. 5 B) are more in grid The lower section of crystal silicon structure and polysilicon protrusion (for example, item (510) in Fig. 5 A to Fig. 5 B) creates continuous P doped region.

In an embodiment according to present disclosure, the P doped silicon below the distal end of polysilicon protrusion is (remote Ontology from gate polysilicon structure) it is contacted with the P+ doped region (body contact region) of semiconductor devices.As noted above It arrives, the such P+ doped region for limiting body contact region is that have phase with the body regions below gate polysilicon structure The region of same type doping, and can have any doping concentration, and it is not limited to P+ doping.

In an illustrative embodiments according to present disclosure, body contact region can have square or square Shape shape.As by described in the aft section in present disclosure, body contact region can via Metal contacts or The low resistance of desired ontology connection current potential is provided via such as silicide layer of the low-resistivity layer on contact area top Rate conductive path.In addition, body contact region can be contacted with the source region of semiconductor devices to provide source-body connection, Or be isolated with any active region (for example, source region/drain region) of device, it enables to (with source potential Decoupling) any current potential of ontology offer.

In an embodiment according to present disclosure, it can be provided for identical gate polysilicon structure more A polysilicon protrusion (being branched off from grid polycrystalline silicon), wherein corresponding ontology protruding portion is (below polysilicon protrusion P doped region) it is connected to different and separated body contact region (for example, Fig. 7 A being described later on).

In another embodiment according to present disclosure, multiple polysilicons are provided for identical grid polycrystalline silicon Protruding portion, and corresponding ontology protruding portion can connect to identical continuous body contact region (for example, being described later on Fig. 7 B).

In an embodiment according to present disclosure, sheet of the ontology protruding portion in the separate grid of ontology protruding portion The far-end of body region is contacted with body contact region.

In an embodiment according to present disclosure, mosfet transistor includes associated multiple grids Multiple fingers of polysilicon structure, wherein corresponding polysilicon protrusion be connected to each gate polysilicon structure (for example, Fig. 8 A to Fig. 8 B being described later on).

In the another embodiment of present disclosure, ontology corresponding with the polysilicon gate of adjacent finger part is prominent Portion can connect to identical continuous P+ doped region (for example, Fig. 8 B being described later on).

In the another embodiment of present disclosure, the polysilicon that is branched off from the polysilicon gate of adjacent finger part Protruding portion can be engaged (for example, Fig. 8 B being described later on).

According to some embodiments of present disclosure, it is connected to (separate body regions) distal end of ontology protruding portion Body contact region creates in the source region of mosfet transistor, so that the interior creation P+ in N+ doped source region is adulterated Region.According to the another embodiment of present disclosure, such body contact region is in the source area with mosfet transistor Domain it is neighbouring and contact region in create.It should be noted that although body contact region is described as P+ doped region, It is that this is not construed as the range that limitation inventor thinks its invention, because this also can be used in docking body contacts invention The various doped levels in body contact zone domain, including the doping similar with the doping of body regions.

It will be provided in the subsequent section of present disclosure referring to associated drawings to the above implementation according to present disclosure The further explanation of mode.

Figure 1A shows the top view of N-type SOI MOSFET element (100).Gate finger part (110) is shown at Between source region (120) and drain region (130).Gate finger part (110) has length L_GWith width W_G.On the one hand, grid Pole finger can be made via gate polysilicon structure (110), and gate polysilicon structure (110) can stop for adulterating The injection of the dopant ion in the adjacent source region and drain region of MOSFET.It will be readily appreciated by those skilled in the art that Refer to that SOI device can have multiple such fingers, wherein each finger may include corresponding grid polycrystalline silicon knot more Structure (110), the drain region (130) with corresponding drain contact (155) and have corresponding source contact portion (145) Source region (120).In some embodiments, adjacent finger can share corresponding drain region and/or source electrode Region.

Figure 1B shows the sectional view of the A along the line of the N-type SOI MOSFET element (100) of Figure 1A.On the one hand, grid is more Crystal silicon structure (110) is shown as being laid in insulation grid silicon oxide layer (115).On the one hand, gate polysilicon structure (110) The body regions (112) of lower section are doped with P-type dopant (P ontology), and source region (120) and drain region (130) quilt A large amount of injections N type dopant (N+).As shown in the sectional view of Figure 1B, the region (112,120,130) of SOI MOSFET element is It is created on the top of buried oxide (BOX) layer (150) formed on semiconductor substrate (160), therefore, because BOX layer (150) insulating property (properties), in Figure 1A and Figure 1B in discribed SOI MOSFET without provide region (112,120,130) with Conductive path between semiconductor substrate (ontology).Those skilled in the art are readily apparent that, the area of SOI MOSFET element (100) Domain (112,120,130) can be formed in the thin silicone layer (180) of covering insulating layer (150), such region (112,120, 130) depth of thin silicone layer (180) is extended through to reach insulating layer (150).And as it is known in the art, SOI therefore, MOSFET element (100) can be referred to as thin film SOI MOSFET, which refers to thin silicone layer (180).It should be noted that The various embodiments according to present disclosure being described below can be realized in thin film SOI MOSFET element.

The SOI MOSFET element (100) described in Figure 1A and Figure 1B does not provide ontology connection, such as those skilled in the art Known, ontology connection is the connection between P ontology and the source region of benchmark (fixation) current potential such as device.In Fig. 1 C schematically The such SOI device indicated is floating body device, and is therefore easy by discussing in the above section of present disclosure The influence of disadvantage.

Fig. 2A indicates the N-type mosfet transistor with T grid ontology connecting structure according to prior art embodiment (200) top view.In the prior art embodiment indicated by Fig. 2A, gate polysilicon structure (110) is extended with packet It includes structure (210), conducting channel (that is, body regions, channel region) of structure (210) supplement for creating device (200) Traditional structure (110).Therefore, T conformal polysilicon structure (110,210) makes it possible to be formed corresponding P ontology below polysilicon Region, the P body regions are contacted with the region P+ (240), under the region the latter P+ (240) permission and polysilicon elongated area (210) The region the P- low resistance contact of side, and therefore allow and the transistor body low resistance contact below polysilicon region (110) Contact.P body regions below polysilicon region (210) also allow that source region is isolated relative to heavily doped region (240) (120) with drain region (130).The skilled person will understand that the T grid ontology of ontology connection transistor (200) of the prior art Connecting structure allows the region P+ (240) and constant voltage node to be in electrical contact, for floating in the channel region of transistor (200) Charge (floating charge) is moved to provide conductive path.According to some implementations, the region P+ (240) can with above cover Metal layer contact, metal-clad can connect to constant voltage on this.Such constant voltage can be applied to transistor The voltage or reference potential of source terminal are for example or fixed (negative) voltage.It will be understood by those skilled in the art that in Fig. 2A The top view of description is the simplification top view of transistor (200), retouches because illustrating only with (prior art) embodiment State relevant structure/element.It is for example leaked it will be understood by those skilled in the art that other structures/element is omitted from such figure Pole/source contact portion, so that becoming apparent from.In general, being used when the various attached drawings for constituting a part of present disclosure are presented Identical method.

The T grid ontology connecting structure used in N-type transistor (200) can be reduced in the transistor (100) of Figure 1A Existing floater effect.However, via the polysilicon structure of the extension adjacent with drain region and source region (130,120) (210), T grid ontology is attached between the grid and source electrode of transistor (200) and provides increased parasitic capacitance (C_SG), and Increased parasitic capacitance (C is provided between the grid and drain electrode of transistor (200)_DG).Such parasitic capacitance (C_SG, C_DG) Without constant capacitance, because their value can change according to the voltage for being applied to transistor terminal.The latter is parasitic Capacitor (C_SG, C_DG) shown in fig. 2b (as variable capacitance), Fig. 2 B schematically shows transistor (200), the transistor It (200) include that the body contacts of the connection of expectation current potential are provided.Those skilled in the art are readily apparent that such parasitic capacitance pair The adverse effect of the performance of transistor (200) can especially reduce the switching speed of transistor and reduce using T grid sheet The characteristic manipulation frequency f of the transistor (200) of body connection_TAnd f_max.Due to parasitic capacitance (C_SG, C_DG) non-constant property, in this way Capacitor be also possible to negatively affect the linearity of prior art transistor (200).

The alternative of T grid ontology connection well known by persons skilled in the art is realized, such as the H grid ontology described in Fig. 2 C Connection additionally provides the benefit for reducing floater effect, but to increase parasitic capacitance as cost, parasitic capacitance may make device RF performance deteriorates (for example, lower f_TAnd f_max).The prior art embodiment tool for the H grid ontology connection described in Fig. 2 C Having the advantage that has big width (W in transistor_G) in the case where, with what is discussed for the case where T grid ontology connection Increased parasitic capacitance (C_SG, C_DG) and related negative effect be cost, the ontology connection of more effective (such as symmetrical) is provided. However, H grid or T grid provide effective ontology without normal direction transistor and link, because in crystal for big transistor width The far-end in pipe trench road, which provides ontology connection, will lead to the higher resistance for the centre of channel width.

Fig. 3 A indicates the N-type mosfet transistor with source-body connecting structure according to prior art embodiment (300) top view.In the prior art embodiment indicated by Fig. 3 A, by increasing the area P+ in source region (120) Domain (340) provides body contacts, and the P body regions below gate polysilicon structure (110) are connected to source by the region P+ (340) Polar region domain (120).In other words, the P sheet of the region P+ (340) below source region (120) and gate polysilicon structure (110) Low resistance path is provided between body region, is described to meaning property as shown in Figure 3B.

As the case where the T grid ontology connecting structure of Fig. 2A, source electrode used in the N-type transistor (300) of Fig. 3 A Ontology connecting structure can reduce floater effect present in the transistor (100) of Figure 1A.For example exist further, since not extending The gate polysilicon structure (110) being arranged in T grid (and H grid) structure, so the source-body connecting structure of Fig. 3 A does not mention For increased parasitic capacitance.

Region (340) in Fig. 3 A must link to source region (120) associated with gate polysilicon structure (110) P body regions, therefore, region (340) must with the P body regions have non-zero Chong Die (Δ) (referring to Massachusetts science and engineering Institute's Lincoln laboratory, in June, 2006 revised edition 2006:1, entitled " MITTL Low-Power FDSOI CMOS Process's " Document, entire contents are incorporated herein by reference).This overlapping may locally change crystal in the region to overlap Manage the characteristic of the conducting channel of (300), it is thus possible to the performance of transistor is negatively affected, for example, causing transistor (300) Nonlinear response (for example, I-V characteristic curve).

The construction of the source-body connection such as provided by the prior art embodiment of Fig. 3 A may also result in increased Complexity is manufactured, including is directed at the region P+ (340) relative to gate polysilicon region (110).It is related to latter alignment procedures The precision of connection can directly affect the linearity of transistor and the I-V characteristic curve of transistor due to any variation of alignment Consistency, and have an effect on the cost and yield for manufacturing this transistor.

Fig. 4 A indicates the N-type mosfet transistor with docking body contacts according to the embodiment of the present disclosure (400) top view.According to the embodiment of the present disclosure, mosfet transistor device (400) can be thin film SOI device Part comprising be formed in covering insulating layer (150 in Fig. 4 B) thin silicone layer (180 in Fig. 4 B) in active region (such as 120,130), active region extends through the depth of thin silicone layer to reach insulating layer.Transistor (400) includes polysilicon protrusion (410), which is branched off, by source region (120) from gate polysilicon structure (110), and More than the body contact region (440) that source region (120) extend adjacent to source region (120).Due to polysilicon protrusion It (410) is the structure adjacent with gate polysilicon structure (110) (for example, forming single structure), therefore in polysilicon protrusion (410) corresponding ontology protruding portion is created below, which has the P sheet with gate polysilicon structure (110) below The identical type of body region (doping) (because polysilicon protrusion (410) with such as adjacent drain region (130) and source area N+ is prevented to be injected into P ontology during the associated injection stage of doping in domain (120)).By Fig. 4 B as it can be seen that such ontology is dashed forward The P body regions of gate polysilicon structure (110) below are connected to and source region (120) neighbouring body contact region by portion out Domain (440) (is shown as the region P+) in Fig. 4 A to Fig. 4 B.According to the various embodiments of present disclosure, body contact region With the doping with P body regions same type, compared with the concentration of P body regions, body contact region can have identical Concentration (such as P-) or higher concentration (such as P+).

With further reference to Fig. 4 A to Fig. 4 B, during the operation of transistor (400), body contact region (440) and ontology Protruding portion (412) can provide conductive path for the carrier between transistor body (112) and the source region N+ (120), Fluctuating charge to be previously contained in transistor body (112) provides final extraction node.

Fig. 4 B shows the N-type with docking body contacts of embodiment according to the present invention shown in Fig. 4 A The sectional view of the line B along Fig. 4 A of mosfet transistor (device) (400).By the sectional view of Fig. 4 B as it can be seen that grid polycrystalline silicon knot The transistor body region (112) of structure (110) below and P body regions (412) are adjacent, and P body regions (412) are prominent in polysilicon It is formed below portion (410) out, referred to herein as ontology protruding portion.The section of the line A in Fig. 4 A of transistor (400) Figure can be seen in previously discussed Figure 1B.

Fig. 5 A shows the N-type MOSFET crystalline substance with docking body contacts of another embodiment according to present disclosure The top view of body pipe (500).Transistor (500) includes polysilicon protrusion (510), and the polysilicon protrusion (510) is from grid Polysilicon structure (110) is branched off in source region (120), and extends to the P+ created in source region (120) Region (540), i.e. body contact region.Since polysilicon protrusion (510) is the knot adjacent with gate polysilicon structure (110) Structure, therefore corresponding ontology protruding portion is created below in polysilicon protrusion (510), which has and gate polycrystalline The identical type of P body regions (doping) of silicon structure (110) below.By Fig. 4 B as it can be seen that such ontology protruding portion is by grid The P body regions of polysilicon structure (110) below are connected to the body contact region (540) formed in source region (120).

Fig. 5 B shows the N-type with docking body contacts of embodiment according to the present invention shown in Fig. 5 A The sectional view of the line C along Fig. 5 A of mosfet transistor (device).By the sectional view of Fig. 5 B as it can be seen that gate polysilicon structure (110) below (ontology is prominent with the P body regions (512) formed below in polysilicon protrusion (510) for body regions (112) Portion out) it is adjacent.In addition, far-end of the ontology protruding portion (512) in ontology protruding portion (512) and the wound in source region (120) Body contact region (540) contact built.The sectional view of the line A in Fig. 5 A of transistor (500) can be previously discussed See in Figure 1B.

As it is known to the person skilled in the art, low-resistivity layer such as silicide layer can reside in the sudden and violent of semiconductor devices The top of the silicon area of dew.Such low-resistivity layer can provide low resistance conductive between all the points of following silicon area Path.For example, referring to Fig. 5 B, the continuous silicide layer (not shown) of the deposited on top of region (120) and region (540) can To provide low resistivity conductive path between two adjacent areas (120) and any point of region (540).

With further reference to Fig. 4 A to Fig. 5 B, the crystal according to the embodiment of the present disclosure described in Fig. 4 A and Fig. 5 A Manage (400,500) ontology protruding portion (412,512) can body regions (112) and body contact region (440,540) it Between first resistor (conduction) path is provided, and deposited on the top of body contact region (440,540) and source region (120) Continuous low-resistivity layer such as silicide layer can be provided between ontology protruding portion (412,512) and source region (120) Second resistance path.The person skilled in the art will easily understand doping types and concentration based on these regions, with first resistor Path associated resistance (R1) can be substantially greater than resistance (R2) associated with second resistance path.Fig. 5 C is N-type Mosfet transistor (400,500) are schematically shown, wherein ontology protruding portion (412,512) and body contact region (440, 540) resistance connection is provided between the ontology of transistor and source electrode and (is respectively provided with the first resistor path of equivalent resistance R1 and R2 With second resistance path).This resistance connection is by the source S for connecting transistor of Fig. 5 C and the resistor R (=R1+R2) of ontology It indicates.

Can be provided via the alternative method of conductive (silicide layer) discussed above is used ontology protruding portion (412, 512) the second resistance path between source region (120).According to the embodiment of the present disclosure, related to different zones The Metal contacts of connection may be used to provide second resistance path.For example, can via metal by body contact region (440, 540) Metal contacts on top bridge to the Metal contacts (145) on source region (120) top, thus the second low electricity of creation Resistance rate path.

With further reference to Fig. 5 C, in some cases, it can be possible to different resistance R values is intended to provide, provided by obtaining The desired effect of ontology connection.Due to being provided by second resistance path compared with the resistance R1 provided by first resistor path Resistance R2 very small (being substantially zero), therefore resistance R2 cannot be used for the resistance for substantially modifying resistor R.According to the disclosure The various embodiments of content can adjust the value of resistance R1 by the parameter via ontology protruding portion (412,512) to provide The different resistance values of resistor R.

According to the embodiment of the present disclosure, the resistance value of the resistor R1 in Fig. 5 C, thus the resistance of resistor R Value, can be via the width and/or length with ontology protruding portion (412,512) associated polysilicon protrusion (410,510) To adjust.It will be understood by those skilled in the art that the width and/or length of polysilicon protrusion (410,510) how are modified, thus The width and/or length for correspondingly modifying ontology protruding portion (412,512) can modify resistance R1 and therefore modify (region (112) between region (440,540)) resistivity in first resistor path.

According to the another embodiment of present disclosure, give gate polysilicon structure polysilicon protrusion (510, 410) number can be more than one, such as two, three, four, or more (for example, the Fig. 6 to Fig. 7 B described below). The width and/or length of the relative spacing and polysilicon protrusion (410,510) of polysilicon protrusion can be used for adjusting this The resistance value R1 of resistor path between body region (112) and body contact region (440,540), so as to adjust resistor R's Resistance value.

According to the another exemplary embodiment of present disclosure, can with for manufacturing gate polysilicon structure (110) polysilicon protrusion (410,510) are created during the step of different manufacturing step.The exemplary embodiment party of even now Formula may bring complexity to entire manufacturing process, but be still for providing the possible of docking body contacts of the invention Alternative embodiment.

With further reference to Fig. 4 A and Fig. 5 A, it would be recognized by those skilled in the art that the prior art embodiment with Fig. 2A It compares, passes through the reduction of provided parasitic capacitance according to the embodiment of the present disclosure.Implement with such prior art Mode is compared, and the embodiment of present disclosure will not introduce gate-drain parasitic capacitances C_DG.Further, since the prior art with Fig. 2A The polysilicon region (210) of embodiment is compared, and the size (width and/or length) of polysilicon protrusion (410,510) is opposite Reduce, therefore the gate-source parasitic capacitance C according to the embodiment of the present disclosure described in Fig. 4 A and Fig. 5 A_SGLess than Fig. 2A's The C of prior art embodiment_SG。

According to some embodiments of present disclosure, polysilicon protrusion (410,510) is gate polysilicon structure (110) constituent element, and created using identical mask.Due to the constituent element as gate polysilicon structure (110), It is thus eliminated that relative to grid polycrystalline silicon (110) and associated needed for prior art transistor shown in such as Fig. 3 A P ontology (112) creates the alignment issues of polysilicon protrusion (410,510) and associated ontology protruding portion (412,512). In view of the prior art embodiment of previously discussed Fig. 3 A, it would be recognized by those skilled in the art that docking described herein Ontology linking method provides the elimination and simpler manufacturing process of such alignment procedures.

As pointed in the above paragraph of present disclosure, implement when with the prior art of (for example, Fig. 2A, Fig. 3 A) Mode ontology connection compares, such as in Fig. 4 A to Fig. 5 C the discribed various embodiments according to present disclosure docking Ontology connection offers the advantage that manufacturing process is simpler, ontology connection impedance (such as resistance) is adjustable and parasitic capacitance Reduce.Therefore, use can be surpassed using the integrated circuit of the transistor device with docking ontology connection according to the present invention There is no ontology to link or there are similar functions with the transistor device linked according to the ontology of prior art embodiment Integrated circuit.Figure 10 A to Figure 19 described later, which is shown, shows docking body contacts (connection) according to the present invention The correlation data figure of other feature performance benefit.

It, can be via more than one according to some embodiments of present disclosure as mentioned in the previous paragraph Polysilicon protrusion provides docking ontology connection to the grid polycrystalline silicon of transistor.According to such embodiment party of present disclosure Formula is described in Fig. 6, and Fig. 6 is the extension for the embodiment described in Fig. 4 A.As shown in fig. 6, multiple polysilicon protrusions (610) It is branched off, passes through source region (120), and cross source region (120) and extend to figure from gate polysilicon structure (110) The region P+ and source region (120) adjacent body contact region (440) are expressed as in 6, to form single polysilicon structure. Such different polysilicon protrusion (610) allows to create corresponding different ontology protruding portion, the ontology protruding portion again Resistance conductive path is provided between the P ontology below polysilicon gate construction (110) and body contact region (440), and The resistance conductive path for arriving source region (110) is therefore provided.A along N-type mosfet transistor (600) shown in Fig. 6 It can be obtained in Figure 1B and Fig. 4 B respectively with the sectional view of line B.In transistor width W_GIn the case where big, it may be desirable to multiple Polysilicon protrusion (610).Although in the illustrative embodiments according to present disclosure described in Fig. 6, different is more Crystal silicon protruding portion reaches public continuous body contact region (440), but according to the alternative embodiment of present disclosure, this The body contact region of sample may include one or more different and isolated regions P+, each such region P+ and source electrode Region (120) is adjacent.It should be readily apparent to one skilled in the art that how based on the exemplary structural layout embodiment party described in Fig. 6 Formula obtains such alternative embodiment.It should be noted that polysilicon protrusion (610) is (logical along the width of body regions Cross W_GDefinition) position can according to the docking ontology of Fig. 6 link transistor (600) desired design target depending on.According to this One illustrative embodiments of disclosure, as depicted in figure 6, polysilicon protrusion (610) along body regions width Degree is arranged symmetrically, wherein center line (in Fig. 6 with B indicated) of the polysilicon protrusion (610) relative to the width of body regions It is arranged symmetrically.According to the another exemplary embodiment of present disclosure, as depicted in figure 6, polysilicon protrusion (610) Arranged at equidistant position along the width of body regions, wherein between any two continuous polysilicon protrusions (610) along width Spend W_GDistance be constant.

It, can be to the root described in Fig. 5 A in similar mode in a manner of being provided in embodiment depicted in figure 6 It is extended according to the docking ontology connection embodiment of present disclosure, is branched out with providing from gate polysilicon structure (110) The more than one polysilicon protrusion (510) come.As shown in Figure 7 A, each such polysilicon protrusion (510) can reach The region comprising the region P+ associated with body contact region (540) in source region (120).As discribed in Fig. 7 A According to the illustrative embodiments of present disclosure, such body contact region (540) can be it is different and separated, and It is one-to-one relationship with each polysilicon protrusion (510).It is retouched according to the other embodiments of present disclosure, such as Fig. 7 B It draws, can be merged into one or more biggish areas P+ from the different associated regions P+ in body contact region (540) Domain (540), the ontology that the biggish region P+ can each serve as more than one polysilicon protrusion (510) connect Touch region.

As previously mentioned, grid polycrystalline silicon (110) can be a part of the finger of larger device, wherein this The device of sample may include multiple such fingers.Each such finger can be a part of individual transistor, The individual transistor creates bigger device in conjunction with other transistors.Bigger device may include be connected in series or simultaneously Connection connection is connected in series and is connected in parallel the multiple transistors combined.As it is known by the man skilled in the art, in some cases Under, adjacent finger can share identical continuous source region.According to the embodiment of the present disclosure, bigger device Finger in one, more than one or all fingers can have according to the topology layout provided in Fig. 4 A to Fig. 7 B Docking ontology connecting structure.

Fig. 8 A, which is shown, shares public source according to two adjacent finger parts of the wherein transistor device of present disclosure The embodiment in region (120).Each finger, which has, is respectively provided with associated length L_G1And L_G2Respective gates polysilicon Structure (110), in some embodiments, length L_G1And L_G2It can be equal to each other.Each gate polysilicon structure (110) can It is branched off into public source region (120) from gate polysilicon structure (110) to have and extends to body contact region (540) corresponding polysilicon protrusion (510), in some illustrative embodiments, latter body's contact area is the region P+. The illustrative embodiments according to present disclosure described in Fig. 8 A show each gate polysilicon structure more than (110) one Crystal silicon protruding portion (510), the polysilicon protrusion (510) are merged into body contacts in the far-end of polysilicon protrusion (510) In region (540).This limitation is not construed as the content for its invention that limitation present inventor is thought, and only originally One illustrative embodiments of invention.As discussed in preceding paragraphs and about Fig. 4 A to Fig. 7 B, for basis Many different structures layout of the docking body contacts of present disclosure is possible, and based on the religion according to present disclosure Show, in the limit of power of those skilled in the art.For example, in one embodiment, body contact region (540) can position At away from the identical distance of corresponding gate polysilicon structure (110).In another embodiment, body contact region (540) It can be located relative at the different distance of corresponding gate polysilicon structure (110).

It can be desirable to the gate polysilicon structure (110) of two adjacent finger parts of connection.This is usually via grid polycrystalline silicon Structure the extension in (for example, the region separated with the drain region of device and source region) and connects outside the active region of device It closes to execute.According to the embodiment of the present disclosure, as discribed in Fig. 8 B, two adjacent gate polysilicon structures can To be engaged via the public polysilicon protrusion between two adjacent gate polysilicon structures.The implementation described in the fig. 8b In mode, have by L_G1And L_G2Two gate polysilicon structures (110) of the corresponding associated grid length indicated are via two Shared polysilicon protrusion (510) connection of a structure (110).This can permit for example with a gate polysilicon structure phase The grid voltage provided at an associated gate contact is provided to adjacent grid, and therefore allows simpler and letter The whole gate polysilicon structure of change.

The public polysilicon protrusion (510) of the discribed illustrative embodiments according to present disclosure can in Fig. 8 B With while engaging corresponding gate polysilicon structure (110) as described above, via itself and body contact region (540) Connection to provide docking ontologies connection to two transistor devices shown in Fig. 8 B.It is mentioned in the discribed embodiment of Fig. 8 B It is similar to the mechanism referring to described in Fig. 4 A to Fig. 7 B for the mechanism of docking ontology connection, wherein with polysilicon protrusion (510) Associated ontology protruding portion connects the P body regions resistance-type below grid polycrystalline silicon via body contact region (540) It is connected to public source region (120), body contact region (540) provide (second) for arriving source region (540) as described above Low resistivity conductive path.Although should be noted that the region P+ (540) in Fig. 8 B seems to be centrally disposed in two grid Between pole polysilicon structure (110), but the position in such region can be according in two devices discribed in Fig. 8 B The desired ontology of each links performance requirement and changes.Similarly, between body contact region (540) with a grid The width of the section of the associated polysilicon protrusion of polysilicon structure can be different from associated with another gate polysilicon structure Section width.

In Fig. 8 A to Fig. 8 B in the discribed illustrative embodiments according to present disclosure, have corresponding related The grid length L of connection_G1And L_G2Adjacent finger part can be a part of same device or two discrete devices.According to this The another embodiment of disclosure, adjacent finger part can correspond to the discrete device being for example electrically connected with cascode configuration in FIG Finger.In such cascode configuration in FIG, as discribed in Fig. 8 C to Fig. 8 K, the source electrode of the first device is electrically connected to The drain electrode of second (latter) device.Although indicated in Fig. 8 C to Fig. 8 E and Fig. 8 I to Fig. 8 J according to the exemplary of present disclosure It configures and uses two cascode transistors devices, but the skilled person will understand that, as discribed in Fig. 8 F and Fig. 8 K, Such as three greater than two, four, five ..., ten or more the stack sizes for stacking device it is also possible.

Fig. 8 C show schematically shown in Fig. 8 I according to the docking ontology of present disclosure link cascode configuration in FIG The top view of (800C).It should be noted that the top transistor schematically shown in Fig. 8 I correspond to Fig. 8 C in describe and And pass through its associated grid length L_G1First device of mark, and the bottom transistor schematically shown in Fig. 8 I corresponds to It is describing in Fig. 8 C and pass through its associated grid length L_G2Second device of mark.By Fig. 8 C as it can be seen that by associated Grid length L_G1Indicate the first device source region (120) with by associated grid length L_G2The second device indicated Drain region (130) be shared, so that such source region and drain region are electrically connected.

As shown in Figure 8 C, can polysilicon protrusion (510) in this way the docking ontology to the second device is provided Connection: the polysilicon protrusion (510), which is connected to, (passes through L_G2Mark) gate polysilicon structure (110) of the second device and The body contact region formed in the source region (120) of the second device is extended on the source region (120) of the second device Domain (540) (for example, P+ is adulterated).As combined described in Fig. 4 A to Fig. 7 B, such polysilicon protrusion (510) can be used for Corresponding ontology protruding portion is created below in polysilicon protrusion (510), which can be in the ontology of the second device Adjustable ohmic conductive path is provided between region and body contact region (540).Link due to not having ontology, (pass through L_G1Mark) the first transistor is three terminal resistors (top transistor in figure) as shown in fig. 81.

It, can be via such two polycrystalline according to the another exemplary embodiment for the present disclosure described in Fig. 8 D Silicon protruding portion (510) come provide describe in Fig. 8 D (by L_G2Mark) connection of the docking ontology of the second device: it is described two Polysilicon protrusion (510) is connected to the gate polysilicon structure (110) of the second device and in the source region of the second device (120) it on and crosses source region (120) and extends to the body contact region adjacent with the source region of the second device (120) (440) (for example, P+ is adulterated).Therefore, as described above, such polysilicon protrusion (510) can provide corresponding ontology The body regions resistance-type of second device is connected to body contact region (440) by protruding portion.The docking ontology of Fig. 8 D connects Schematically showing for cascode configuration in FIG of knot is also provided by Fig. 8 I, wherein (passes through L_G1Mark) the first transistor be as figure Three terminal resistors shown in 8I (top transistor in figure).

It, can also be (logical into Fig. 8 C to Fig. 8 D as represented by Fig. 8 E according to some embodiments of present disclosure Cross L_G1Mark) one or more docking ontologies connections of the first device offer.It as illustrated in fig. 8e, can be via such first Polysilicon protrusion (510) links come the docking ontology provided to the first device: first polysilicon protrusion (510) is connected to (pass through L_G1Mark) gate polysilicon structure (110) of the first device, and in the public drain electrode of two cascade devices The ontology formed in common drain region/source region (130/120) is extended on region/source region (130/120) to connect Touch region (540) (for example, P+ is adulterated).As combined described in Fig. 4 A to Fig. 7 B, such polysilicon protrusion (510) can be with For creating corresponding ontology protruding portion below in polysilicon protrusion (510), which can be in the first device Adjustable ohmic conductive path is provided between body regions and body contact region (540).The docking ontology of Fig. 8 E links Schematically showing by Fig. 8 J for cascode configuration in FIG indicates, wherein (passes through L_G1And L_G2Mark) two transistors are respective Four terminal resistors with docking ontology connection.

It will be appreciated by those skilled in the art that for upward discussing according to this described in Fig. 4 A to Fig. 7 B In first device of the cascode configuration in FIG of disclosure and the second device (or more devices for bigger stack size) Either one or two of to provide the various combinations of structure of docking ontology connection be feasible.For example, the first device can be provided with root According to the docking ontology connection of any structure represented in Fig. 4 A to Fig. 5 A and Fig. 7 A to Fig. 7 B, and second (latter) device can It is provided with linking independently of the docking ontology for being provided to the first device according to any structure indicated in Fig. 4 A to Fig. 7 B Dock ontology connection.

Fig. 8 F and Fig. 8 K indicate the extension for the illustrative embodiments according to present disclosure described in Fig. 8 C and Fig. 8 E, Wherein, cascode configuration in FIG includes n transistor device being electrically connected in series, the source electrode (120) of two adjacent devices and drain electrode (130) such as the case where the embodiment described in Fig. 8 C be merged.It should be noted that according to present disclosure and In the cascode configuration in FIG indicated in Fig. 8 C to Fig. 8 K, only the last one device is (for example, the second device of Fig. 8 C, Yi Jitu The n-th device of 8F) the docking ontology connection of the structure that with good grounds Fig. 6 is indicated can be set.

It, can be similar and different by being provided to the different components of stacking according to the another embodiment of present disclosure Ontology connecting structure stacks to optimize (for example, expected performance of Fig. 8 C to 8K), thus for each of the device stacked The resistance of different value or identical value is provided between ontology and contact.Figure 10 A to Figure 19 described below indicates to link with ontology The related individual devices performance of structure.

According to some embodiments, and non-stacking all devices are provided with docking body construction, and therefore for example Fig. 8 C is discribed into 8D and Fig. 8 I to Fig. 8 J, and stacking may include the combination of three terminal devices and four-terminal device.Fig. 8 G It is further such illustrative embodiments with Fig. 8 H, wherein some (four terminals) devices of stacking are provided with according to this The docking ontology connecting structure of teaching, and the not set docking ontology connection of other (three terminals) devices.Describe according in Fig. 8 G Exemplary cascode configuration in FIG, only the last one (passes through L_GnMark) device be provided with according to the docking ontology of this teaching company Knot, and according to the exemplary cascode configuration in FIG described in Fig. 8 H, only (pass through L_G2Mark) the second device and (pass through L_Gn Mark) the last one device be provided with according to the docking ontology of this teaching connection.It is to be understood that such exemplary implementation Mode is not construed as limiting the scope of the invention, because having and being connected according to the docking ontology of present disclosure in view of this teaching The modification of such embodiment of the stacking device of knot is completely in the limit of power of those skilled in the art.

Ontology (the ditch of transistor device is described according to the embodiment of above of the present disclosure of docking ontology connection Road) region and corresponding source region electrical connection, thus at the source terminal of device existing for current potential be electrically connected.According to The another embodiment of present disclosure can provide and connect with the docking ontology connection of the current potential decoupling at corresponding source terminal It connects.Such embodiment allows to dock the independent electricity of current potential that ontology connection is coupled at the source terminal with corresponding device Position.Corresponding structure is depicted in Fig. 9 A and Fig. 9 B, and is depicted in Fig. 9 D and schematically shown accordingly.

Fig. 9 A depicts can be used for by the body regions resistance-type of device according to the embodiment of the present disclosure It is linked to the top view of the docking ontology coupler (900A) of any current potential.Transistor device (900A) is (for example, thin film SOI Device) it include for providing the similar structures of docking ontology connection as described with respect to figure 5 a, wherein the difference is that, Body contact region (540) now via creating in the polysilicon structure (910) for being connected to polysilicon protrusion (510) below The region P- is isolated and is isolated with source region (120).Similar to polysilicon protrusion (510), polysilicon structure (910) can be permitted Perhaps the corresponding isolation region P- (912) is created below in polysilicon structure (910), the region P- (912) are isolated and via polysilicon The ontology protruding portion of protruding portion (510) creation is adjacent, and is therefore electrically connected to the sheet in gate polysilicon structure (110) below Body region.The body contact region (540) of the region P- (912) in source region (120) is isolated, with the section in such as Fig. 9 B Figure does not provide any contact between region (540) and (120) with describing.Note that similar label (attached drawing mark in attached drawing Note) indicate similar item, and therefore can be described further about the other accompanying drawings of present disclosure.

Fig. 9 B shows the sectional view of the F along the line of the docking ontology coupler (900A) of Fig. 9 A.By Fig. 9 B as it can be seen that source electrode Region (120) is via the region isolation P- (912) associated with polysilicon structure (910) and BOX layer (150) and body contact region Domain (540) isolation, all active regions of the BOX layer (150) to device --- region shown in the sectional view including Fig. 9 B (120,912,540) --- public basis is provided.

It will be appreciated by those skilled in the art that due to being isolated with source region (120), so body contact region (540) it can be coupled to any desired current potential during the operation of docking ontology coupler (900A) of the invention, simultaneously The conductive path with adjustable resistance rate of the body regions of device is provided.The body contact region (540) of isolation and expectation Such coupling of current potential can for example be provided via the Metal contacts connected on region (540) top.

Another embodiment according to the present invention, as discribed in Fig. 9 C, teaching related with Fig. 9 A and Fig. 9 B can be with Extend to adjacent finger part, wherein pass through (L_G1、L_G2) finger of shared public source region (120) of mark can be in public affairs The docking ontology connection of isolation is provided in common source region (120), to allow the body contacts with any desired current potential.This field The skilled person will understand that due to its isolation relative to adjacent area, it is possible to device (900C) and body zone --- being included in drain region (130) --- setting body contact region (540) in the different any active region in domain.

It should be noted that being retouched in previously described attached drawing (for example, Fig. 4 A to Fig. 8 H) according to the sum of present disclosure What any configuration of the connection with source electrode docking ontology that is drawing can be equipped with as illustrated in Fig. 9 A to Fig. 9 D equivalent is isolated Dock ontology connection.Therefore, the stacked transistors structure described in Fig. 8 C to Fig. 8 K, which also can according to need, is provided with isolation Ontology connecting structure.Those skilled in the art can further by according to the teaching of present disclosure extend to including with source electrode The docking ontology connection of isolation and the combined configuration of docking ontology connection.

In the case where transistor is in nonconducting state (opposite with transistor situation in the conductive state), according to upper The docking ontology connection for the various embodiments that face indicates can be in transistor channel and body contact region (for example, region (440,540)) between lower resistance (first resistor described above) is provided.When with the various realities according to present disclosure The grid voltage Vg for applying the transistor of the docking ontology connection of mode is near or below the voltage (threshold voltage of transistor body Vt), thus when placing the transistor in cut-off/non-conductive state, the doping in ontology protruding portion is provided from body contact region The ohmic conductive path in the transistor body region below to grid polycrystalline silicon.Ontology protruding portion passes through silicon from the surface of silicon Entire depth is conductive.When the grid voltage Vg of such transistor is close to and above transistor threshold voltage Vt, thus by brilliant When body pipe is placed in conducting/conduction state, there are the regions that dislocation charge exhausts in ontology protruding portion.The region is from active silicon layer Top surface at start and extend in silicon.The depletion region becomes non-conductive, therefore reduces the conduction in ontology protruding portion The section (thus increasing resistivity) of silicon.Therefore, compared with the nonconducting situation of transistor, when transistor is in conduction state When (Vg > Vt), according to the docking ontology of the various embodiments of present disclosure connection can transistor channel with (setting exist At body contact region) ontology connection between higher resistance is provided.Due to providing ontology connection, this higher electricity Resistance allows to reduce the loss of the RF characteristic performance of transistor.Those skilled in the art, which are fully recognized that, provides ontology with to transistor Link the loss of the RF characteristic performance of associated transistor, and it will thus be appreciated that according to the docking sheet of present disclosure The benefit of body connection.

Figure 10 A indicates (effective) docking ontology connection resistance Reff and gate bias voltage Vg and ontology protruding portion width (by μm as unit of) figure.From the figure of Figure 10 A as can be seen that for given ontology protruding portion width (along grid width Width), ontology connection resistance increases according to gate bias voltage Vg.Specifically, for gate bias voltage Vg=-0.3V The case where (transistor is non-conductive), effective ontology connection resistance is 1M Ω, and for gate bias voltage Vg=1V, (transistor is led Electricity) the case where, effective ontology connection resistance is greater than 1000M Ω.In addition, from the figure of Figure 10 A as can be seen that for given grid Bias voltage Vg, effective resistance reduce as the width of ontology protruding portion increases.

Link the transistor of (floating body) with no ontology or there is the transistor of conventional (H grid, T grid) ontology connection It compares, there is the transistor linked according to the docking ontology of the various embodiments of present disclosure can show performance excellent Gesture.Such performance advantage includes but is not limited to the improvement control to majority carrier and current potential in the body regions of transistor The shortcomings that making, linking transistor without routine (H grid, T grid) ontology.

Compared with floating body transistor, docking ontology connection according to the present invention is provided: higher breakdown voltage, raised Lower drain-source current (Ids) under drain-source voltage (Vds) under off state (non-conductive state), (leads on state Electricity condition) under output impedance in the increased situation of Vds less reduction, and HCI (the hot current-carrying for RF application enhancements Son injection) performance.

Compared with routine (H grid, T grid) ontology links transistor, docking ontology connection according to the present invention is provided: compared with Few total parasitic gate capacitor (summation for being attached to all capacitors of grid), less drain-gate capacitance are (with floating body transistor phase Than not increasing), (being caused due to reduced drain-gate capacitance) higher f_maxAnd there is no limit to channel width to keep Ontology coupler characteristic.In addition, this docking ontology connects compared with the prior art source-body connecting structure indicated in Fig. 3 A It binds up one's hair and bright provides simpler manufacturing process, lower manufacturing cost and higher process yields.

Other than benefiting from the every other application of improved output impedance and breakdown voltage, docking according to the present invention The features above benefit of ontology connection makes it possible to realize that higher peak power increases effect for the application of RF power amplifier Rate (PAE).

Figure 10 B is shown to two floating body transistor (T_1A、T_1B) and with the various embodiments according to present disclosure Docking ontology connection two transistor (T_2A、T_2B) the drain-source under off state (for example, gate source voltage Vgs=0) The figure that electric current (Ids) is compared.Transistor T_1AWith transistor T_2AIdentical (for example, identical grid length), and transistor T_1BWith transistor T_2BIdentical (for example, identical grid length).The figure of Figure 10 B is clearly show: for having docking ontology Transistor (the T of connection_2A、T_2B) the case where, at the lift-off value of drain-source voltage Vds OFF-state current Ids (Leakage Current) compared with It is low.In addition, the figure based on Figure 10 B, it is also clear that for having the transistor (T of docking ontology connection_2A、T_2B) the case where, Effective breakdown voltage (electric current Ids reaches voltage Vds when certain level) is higher, because in all points of curve, (T_2A、 T_2B) Ids electric current be lower than (T_1A、T_1B) Ids electric current.

Figure 11 A and Figure 11 B respectively illustrate the identical transistors with the connection of docking ontology and without ontology connection The figure of the Ids and Vds of part, wherein gate source voltage Vgs changes (variation) with the step-length ladder of 25mV.It such as can from these figures Out, no matter having the transistor of docking ontology connection shows Vgs voltage smooth Ids how and Vds curve, and do not have Show the well known warpage (kink) such as the visible feature as floating body transistor of Figure 11 B.Visible warpage in Figure 11 B Position depends on the Vgs voltage for being applied to floating body transistor.As it is known by the man skilled in the art, such warpage indicates transistor Output impedance (Vds/Ids) unexpected reduction, and many RF application and low frequency simulation application in be undesirable.Such as Figure 11 B is as it can be seen that depend on applied Vgs voltage, warpage is present in the Vds voltage of 0.6V to 0.8V.

Figure 12 A to figure 12 C shows the number for indicating the ontology protruding portion of docking ontology connection transistor according to the present invention The figure of influence of the mesh to Ids and the Vds response of identical transistor device (for example, identical channel length and channel width).Figure Docking ontology coupler (its figure is shown) in 12A has a polysilicon protrusion (from corresponding grid polycrystalline silicon knot Structure is branched off), the docking ontology coupler in Figure 12 B has 4 polysilicon protrusions, and the docking sheet in Figure 12 C Body coupler has 7 polysilicon protrusions, and each polysilicon protrusion is connected to corresponding body contact region.Such as from figure The figure of 12A to Figure 12 C improves output electricity as it can be seen that by the number for the polysilicon protrusion for increasing docking ontology coupler It leads and breakdown voltage.Figure 12 D, which is shown, indicates there is fixed grid width W for fixed gate bias voltage Vg=0.6V_G Docking ontology coupler output conductance g_dsWith the figure of the number of ontology protruding portion.

Figure 13 and Figure 14, which is shown, to be indicated when using in rf applications during service life in transistor relative to hot current-carrying The docking ontology of son injection links the figure of the influence to the identical transistor device linked with ontology.This is by monitoring in RF function Under rate stress as amplifier output transistor operation, have and identical transistor without docking ontology connection being consolidated The variation of the bias current under bias input voltages is determined to measure.Figure 13 shows the crystal indicated for linking without ontology The case where managing (floating transistor) due to the reduced figure of bias current at any time caused by hot carrier in jection.From Figure 13 Figure can be seen that hot carrier in jection and cause bias current gradually to drift about and reduce at any time.This may cause use again The undesirable performance of the RF amplifier of such transistor device.In contrast, showing for Figure 14 is worked as in the same terms Identical transistor (identical transistor) with ontology connection when lower operation will not show bias current and change with time.It should As a result it shows, docking ontology connection of the invention is to be produced at any time in transistor channel due to hot carrier in jection phenomenon Raw minority carrier charge of the electron provides effective outlet.It will be appreciated by those skilled in the art that according to this public affairs as represented by Figure 14 Open the superior function of the docking ontology connection of content, and will be understood that such curve for docking ontology connection transistor can By the importance of property and designed capacity.

Figure 15 A shows expression for gate bias voltage Vg=0.5 volt and transistor width W_G=10 μm, docking is originally Body links the total grid capacitance of measurement standardization of transistor (T2) with the identical transistor (T1) for not having ontology connection (floating body) The figure of Cgg.Figure 15 B shows the figure for indicating the measurement standard Cdg for the identical transistor/condition of figure with Figure 15 A.Such as By attached drawing or Figure 15 A and Figure 15 C as it can be seen that total capacitance is only slightly increased, and is measured in the case where increasing ontology connection Cdg is actually lower.

Figure 16 A to Figure 16 B, which is shown, to be indicated to link the f to transistor according to the docking ontology of present disclosure_TFrequency and f_maxThe comparison diagram of the influence of frequency.Figure 16 A shows the f for floating body transistor_TDatagram (figure at top) and for docking Three kinds of different configuration of f of ontology connection transistor_TDatagram, floating body transistor and docking ontology connection transistor are in its other party Face is identical (for example, identical channel length and width).Such as by the figure of Figure 16 A as it can be seen that observing f_TThe slightly reduction of frequency.This The increased C obtained by the visible docking ontology connection configuration of such as Figure 15 D can be attributed to_GSCapacitor.Figure 16 B is shown pair The case where datagram of Ying Yuyu Figure 16 A identical transistor/condition f_maxDatagram.Such as by the datagram of Figure 16 B as it can be seen that f_maxFollow visible f in the figure of Figure 16 A_TReduce, without further deteriorating.

Figure 17 shows indicate the comparison according to the present invention for docking the influence that RF power amplifier is applied in ontology connection Figure.As it is known by the man skilled in the art, a quality factor of RF power amplifier are to be also known as ACLR in given level Peak power under the Adjacent Channel Power Ratio (ACPR) of (adjacency channel leakage ratio) increases efficiency (PAE).Line in RF application Property degree and frequency requirement do not allow using conventional T gridistor or H gridistor.However, it is possible to use according to this The docking ontology of invention links configuration, because by previous figure as it can be seen that it does not increase drain-gate capacitance C_DG, and also add compared with Few total grid capacitance C_GG.Therefore, by the figure of Figure 17 as it can be seen that there is the ACLR for the transistor for docking ontology connection due to crystal Pipe reaches compression (compression) before increase, and ACLR is sufficiently low.In Figure 17 originally for identical floating body device and docking Body coupler shows the typical curve of ACLR.Note that two transistors have less than -40dBc, until fast due to compression The increased ACLR of speed.For the device size and bias condition of broad range, float arrangement and docking ontology connection configuration are mentioned For being less than the ACLR (dB relative to corresponding RF carrier wave) of -40dBc.

Higher bias voltage can permit transistor and operate at higher output power Pout, until transistor reaches Compression can enable to realize higher inclined so passing through docking ontology and linking the higher breakdown voltage that transistor provides Set voltage and therefore at higher Pout to the operation of transistor.Figure 18 shows expression under relatively high voltage bias The gain of identical floating body transistor and docking ontology connection transistor under identical biasing and the datagram of Pout.By Figure 18 Datagram as it can be seen that docking ontology coupler can operate under higher power before entering compression, compression passes through increasing The reduction of benefit is (sagging) to be indicated.

As known to those skilled in the art, lower bias current (Ibias) reduces the function lost in transistor Rate, the power are the power of waste and therefore reduce the efficiency of transistor.It is operated when under high bias voltage and high RF power When, the voltage of the body regions of transistor may due to generation carrier and increase.For floating body device, as discussed above Shown in warpage in Figure 11 B, body potential increases.In the case where docking ontology coupler according to the present invention, these productions Raw carrier is removed via provided ontology protruding portion conducting channel.RF is applied, due to the sheet of floating body transistor The increase of bulk potential, therefore bias current can increase with the increase of power, especially for being shown to be increased The region that influences of body potential (warpage) in cause the operating condition of transient operation, and transistor is linked for docking ontology, Bias current still shows well.This is shown in Figure 19.

Using according to the exemplary of the transistor device of the docking ontology connections of the various embodiments of present disclosure and Non-limiting application may include: general-purpose simulation circuit, power amplifier (PA), low-noise amplifier with ontology connection (LNA), analog-digital converter (ADC), voltage controlled oscillator (VCO) and frequency range are the voltage of DC to 100GHz and higher frequency Reference circuit.

Using the teaching according to present disclosure, can advanced optimizing grid length, (grid length can be done more It is short).For example, by previously described Figure 10 B as it can be seen that can use the ontology according to present disclosure compared with floating body transistor Link transistor and obtains bigger breakdown voltage.Therefore, the docking ontology of Figure 10 B links transistor (T_2,A、T_2,B) brilliant with floating body Body pipe (T_1,A、T_1,B) compared to can be in higher V_DSIt is safely run under voltage, because in higher V_DSIt is brilliant with floating body under voltage The associated higher I of body pipe_DSElectric current may puncture the transistor.It as the technician knows, can be by changing transistor Grid length controls transistor (T_1,A、T_1,B) this breakdown, wherein biggish grid length can permit transistor more High breakdown voltage and therefore allow higher operation voltage V_DS.In other words, floating body transistor (T_1,A、T_1,B) expectation hit Wear voltage via with dock ontology connection transistor (T_2,A、T_2,B) the bigger grid length compared provides.In addition, with Fig. 3 A In the ontology connection of the discribed prior art compare, the requirement of the overlapping region between region (110) and region (340) can be with Provide bigger grid length.

As discussed above for Fig. 8 C to Fig. 8 F, docking ontology connection of the invention can be provided to including multiple The cascode configuration in FIG of stacked transistors.Figure 20 A schematically shows two stacked transistors (T_A、T_B) cascode configuration in FIG (2000A), Figure 20 B schematically show three stacked transistors (T_C、T_D、T_E) cascode configuration in FIG (2000B).Institute as above It discusses, to transistor (such as T_B、T_D、T_E) docking ontology connection can be by being arranged in the source region of transistor Body contact region provides, and the drain region of the adjacent transistor of the source region and cascode configuration in FIG is shared.It passes through The literature is worn, T is used_ATo T_EThese definition respectively indicate the crystalline substance in the circuit arrangement as shown in such as Figure 20 A and Figure 20 B Body pipe.This is shown in Figure 21 A, and Figure 21 A depicts the transistor T of Figure 20 A_BThe docking ontology according to present disclosure Connection.

As illustrated in fig. 21, it is connected to transistor T_BGate polysilicon structure (110B) polysilicon protrusion (510B) In transistor (T_B、T_A) public source/drain region (120B/130A) on extend in public source/drain region (120B/ The body contact region (540B) (for example, P+ is adulterated) formed in 130A).In some cases, due to polysilicon protrusion The expectation physical size of the expectation physical size of (510B) and body contact region (540B), therefore transistor (T_A、T_B) it is corresponding Interval between gate polysilicon structure (110A, 110B) may be larger, and therefore gate polysilicon structure in this way It the interval of the corresponding body regions limited may be larger.This is shown in Figure 21 A, wherein public source/drain region wound It builds and transistor T_BDrain region (130B) and transistor T_ASource region compare broader public domain, with provide be used for Dock the interval of ontology connection (510B, 540B).Such wider region leads to two transistor (T_A、T_B) gate polycrystalline Biggish interval between silicon structure (110A, 110B), therefore, this may cause the total of the cascode configuration in FIG (2000A) of Figure 20 A The whole of physical size increases.According to the embodiment of the present disclosure, there can be the identical phase discussed above providing While hoping the docking ontology of physical size link (for example, expectation physical size of structure (510B, 540B)), it is total to reduce common source Grid configure total physical size of (2000A).It should be noted that in Figure 21 A and subsequent figure, for realizing according to the disclosure Content various docking ontologies connection configuration various structures indicated by overlooking graph structure accordingly, wherein in view of with Fig. 1 It is related described above to Fig. 9 D, skilled person can easily appreciate that the corresponding alternative of such various structures regards Figure.

It according to the embodiment of the present disclosure, as shown in figure 21b, can be by bottom transistor T_AGrid it is more Creation areas of disconnection has to reduce to top transistor T in crystal silicon structure (110A)_BDocking ontology connection cascade Configure total physical size of (2000A).In the docking ontology connection (2100B) of Figure 21 B, the presence of areas of disconnection allows polycrystalline Silicon protruding portion (510B) extends through areas of disconnection, crosses the region for generally comprising gate polysilicon structure (110A), and because This allows two grids while keeping the expectation physical size of polysilicon protrusion (510B) and contact area (540B) Relatively closely spaced between polysilicon structure (110A) and (110B).Specifically, in order to by source region (120A) and public source/ Drain region (120B/130A) isolation forms area of isolation (2090) around areas of disconnection, and area of isolation (2090) extends to crystalline substance Body pipe (T_B、T_A) public source/drain region (120B/130A) in, and extend to transistor T_ASource region (120A) In.The another embodiment according to present disclosure described in Figure 21 D, area of isolation (2090) extend fully through source area Domain (120A) to reach the boundary (2090) in such region, and therefore by source region (120A) be divided into two it is different (separated left and right) source region (120A), wherein each source region and public source/drain region (120B/130A) Isolation.Figure 21 B, Figure 21 D area of isolation (2090) can by from the region removal (such as etching, oxidation etc.) silicon, to It forms non-conducting areas and is formed.

The docking ontology connection (2100B, 2100D) of 1B, Figure 21 D referring further to Figure 2, gate polysilicon structure (110A) Disconnection provide interval, extended beyond and gate polysilicon structure (110A) and (110B) for polysilicon protrusion (510B) Between the corresponding distance in interval, and be broken as passing through by the source region (120A) that area of isolation (2090) are formed The ontology protruding portion that polysilicon protrusion (510B) limits provides conducting channel, which is generally falling into source region Extend on the silicon area of (120A).Additionally, as discribed in Figure 21 B, Figure 21 D, body contact region (540B) is being abutted It is formed in the region of area of isolation (2090), with to transistor T_B(pass through 110_B、120_B、130_BLimit) it provides according to this teaching Docking ontology link (2100B).Body contact region (540B) is prominent in the ontology limited by polysilicon protrusion (510B) The far-end in portion is contacted with ontology protruding portion out, this is distally far from transistor T_BGrid pass through gate polysilicon structure The body regions that (110B) is limited.The silicon area and polysilicon (grid according to the embodiment of the present disclosure described in Figure 21 B Pole and ontology protruding portion) it is shaped, so that forming transistor T_ADrain electrode (130A) and transistor T_BSource electrode (120B) silicon area Domain and transistor T_ASource electrode (120A) separation, but to transistor T_BOntology protruding portion and transistor T thereto_BSheet Body protruding portion extends to the region in body contact region (540B) and provides continuous silicon area.

Figure 21 C, Figure 21 E, which are shown, to be created according to the use of present disclosure for the target (2120) of injecting p-type dopant Build the illustrative methods of (P+ doping) body contact region (540B).Polycrystalline of the creation for the barrier layer of the injection of dopant Silicon protruding portion (510B) and the not area of isolation of silicon mean the public domain between only region 120B/130A and target (2120) It is doped, to create the body contact region (540B) described in Figure 21 B.According to this teaching, art technology can be used Any other method known to personnel creates body contact region (540B).

Figure 22 shows the transistor T for cascode configuration in FIG (2000A)_AAnd T_BIt respectively include more than one finger The case where (such as two fingers, such as pass through defined in the corresponding gate polysilicon structure (110A, 110B) of Figure 22) The another embodiment according to present disclosure docking ontology link implementation (2200).Those skilled in the art will manage It solves, describing in Figure 22 is for transistor (T according to the docking ontology of present disclosure connection configuration (2200)_A、T_B) in Each have the case where more than one finger according to indicate in figure (21B, 21D) embodiment (2100B, The extension of teaching 2100D).Figure 22 is shown about transistor T_ASource electrode (120A) center line C_LThe cascade of mirror image Configure two transistor (T of (2000A)_A、T_B) each of two fingers, the source electrode (120A) is as transistor The public source of two fingers.As seen from Figure 22, transistor T_AWith around center line C_LTwo fingers of mirror image are (each Finger is identified by separated discrete regions (110A), wherein each separated discrete regions (110A) by every Disconnected at the region limited from region (2090)), each finger has the center line C about stacking_LThe zone similarity of mirror image (110A, 120A, 130A), center line C_LAcross the center of region (120A).Further away from center line C_LAnd about center line Mirror image arranges transistor T_BFinger, each finger have similar region (110B, 120B, 130B), wherein region (120B) and transistor T_ARegion (130A) be shared.Transistor T_BRegion (130E) terminate at by line (2095) mark At the region of note.

The embodiment (2200) described in 2 according to fig. 2, can be by bottom transistor T_AEach finger grid Creation areas of disconnection has to reduce to top transistor T in pole polysilicon structure (110A)_BDocking ontology connection common source Total physical size of grid configuration (2000A) altogether, as shown in Figure 22.Areas of disconnection allows transistor T_BEach finger it is more Crystal silicon protruding portion (510B) extends through areas of disconnection, crosses and generally comprises transistor T_AAdjacent finger part grid polycrystalline silicon The region of structure (110A), and therefore areas of disconnection is being kept for transistor T_BEach finger provide docking ontology While the expectation physical size of the polysilicon protrusion (510B) of connection and contact area (540B), allow adjacent finger part Relatively closely spaced between two gate polysilicon structures (110A) and (110B).Therefore, as Figure 22 is discribed, top transistor T_B(pass through gate polysilicon structure (110B) limit) each finger be provided with structure (510B, 540B) restriction Ontology connection is docked, according to the embodiment of the present disclosure, the structure (510B, 540B) can be around structure (2200) Center line C_LIt is arranged symmetrically.It should be noted that Figure 22 illustrates only the top transistor of cascode configuration in FIG (2000A) T_BFinger docking ontology connection.It can see in such as Figure 25 to Figure 29 B, to cascade stacking in addition to top The docking ontology of the finger of transistor other than transistor links.

2 docking ontology links (2200) referring further to Figure 2, in order to which (being schematically shown by Figure 20 A) common source is total The bottom transistor T of grid configuration_AEach finger (110A) (being public for two fingers) source region (120A) is isolated with each public regions and source/drain (120B/130A), forms area of isolation around two areas of disconnection (2090), the area of isolation (2090) is by transistor T_AThe shared source region (120A) of two fingers (110A) be broken into Two different (separated) source regions (120A), each source region and two public sources/drain region (120B/ 130A) it is isolated.Area of isolation (2090) can by from the region removal (such as etch, oxidation etc.) silicon, to form non-lead Electric region is formed.

With continued reference to Figure 22, the disconnection of gate polysilicon structure (110A) provides interval, is used for polysilicon protrusion (510B) extends beyond the corresponding distance in the interval between adjacent gate polysilicon structure (110A) and (110B), Yi Jitong Cross the ontology for being broken as limiting by polysilicon protrusion (510B) of the source region (120A) of area of isolation (2090) formation Protruding portion provides conducting channel, which extends on the silicon area for generally falling into source region (120A).Additionally, Body contact region (540B) is formed in the region for abutting area of isolation (2090), with to transistor T_BEach finger mention For being linked according to the docking ontology of this teaching.Body contact region (540B) is limited by two polysilicon protrusions (510B) The far-end of ontology protruding portion contacted with ontology protruding portion, this is distally far from transistor T_BGrid pass through grid polycrystalline silicon The body regions that structure (110B) limits.

By the configuration (2200) of Figure 22 as it can be seen that the silicon area according to the embodiment of the present disclosure described in Figure 22 and Polysilicon structure (grid and ontology protruding portion) is shaped, so that being directed to transistor T_AEach finger and transistor T_BPhase Adjacent finger part is answered, transistor T is formed_AFinger drain electrode (130A) and transistor T_BAdjacent finger part source electrode The silicon area and transistor T of (120B)_ASource electrode (120A) (for T_ATwo fingers be public) separate, but simultaneously To transistor T_BFinger ontology protruding portion and wherein ontology protruding portion extends to the area in body contact region (540B) Domain provides continuous silicon area.

Tool can be extended to according to the docking ontology of this teaching connection (2100B, 2200) as Figure 21 B and Figure 22 are discribed Have higher than two such as three, four and the cascode configuration in FIG of the stacking of more, wherein as discussed above and isolated area The transistor that the disconnection of the gate polysilicon structure of domain (2090) coupling can be used for stacking to cascade/finger offer pair Connect ontology connection.

Figure 23 is shown for the three transistor (T described in Figure 20 B_C、T_D、T_E) cascode configuration in FIG (2000B) basis The docking ontology of the another embodiment of present disclosure links implementation (2300), wherein each transistor has at least Two fingers.Figure 23 is shown about (bottom) transistor T_CSource electrode (120C) center line C_LThe cascade of mirror image is matched Set three transistor (T of (2000B)_C、T_D、T_E) each of two fingers, which is transistor T_C's The public source of two fingers, public source region (120C) are isolated region in the central area of source electrode (120C) (2090) it interrupts.As seen from Figure 23, transistor T_CWith around center line C_L(each finger passes through two fingers of mirror image Separated discrete regions (110C) mark, wherein each separated discrete regions (110C) is passing through area of isolation (2090) disconnected at the region limited), each finger has the center line C about stacking_LMirror image similar area (110C, 120C, 130C) (center that center line passes through region (120C) along the width in region).Further away from center line C_LAnd it closes In center line C_LMirror image is (intermediate) transistor T_DFinger (each finger pass through separated discrete regions (110D) mark), wherein each separated discrete regions (110D) quilt at the region limited by area of isolation (2090) It disconnects, is arranged in (bottom) transistor T_CWith (top) transistor T_EFinger between, each finger have similar region (110D, 120D, 130D), wherein region (120D) and transistor T_CRegion (130C) be shared.Additionally, away from Heart line C_LDistalmost end at and about center line mirror image be and transistor T_DAdjacent (top) the transistor T of finger_E's Finger (each finger is identified by separated continuum (110E)), each finger have similar region (110E, 120E, 130E), wherein region (120E) and transistor T_DRegion (130D) be shared, and region (130E) is terminated at At the region marked by line (2095).

Docking ontology connection embodiment (2300) described in 3 according to fig. 2, can be by transistor T_CAnd T_DIt is every Creation areas of disconnection has to reduce to top transistor T in the gate polysilicon structure (110C, 110D) of a finger_EPair Total physical size of the cascode configuration in FIG (2000B) of ontology connection is connect, as shown in figure 23.Transistor T_DFinger in it is disconnected Open region allows transistor T_EThe polysilicon protrusion (510E) of finger extend through areas of disconnection, cross and generally comprise crystalline substance Body pipe T_DAdjacent finger part gate polysilicon structure (110D) region.Areas of disconnection is being kept for transistor T_E's Each finger provides the polysilicon protrusion (510E) of docking ontology connection and the expectation physical size of contact area (540E) While, allow the relatively closely spaced between two gate polysilicon structures (110E) and (110D) of adjacent finger part.By Figure 23 As it can be seen that the areas of disconnection in polysilicon gate construction (110D) and (110C) is located substantially on identical position along the width of finger Place is set, and is substantially of the same size along the width.

Referring further to Figure 23, in order to by bottom transistor T_CEach finger (110C) (T_CTwo fingers It is shared) source region (120C) be isolated with each public source/drain region (120E/130D) and (120D, 130C), enclosing Area of isolation (2090) are formed in the region of (four) areas of disconnection, thus by source region (120C) and public source/leakage Polar region domain (120D/130C) disconnects.This can see in Figure 23, wherein area of isolation (2090) is by each public source/leakage Polar region domain (120D/130C) and public source region (120C) are broken into two different (and isolation) region (isolated areas Every side in domain (2090) one), the every other source region of other fingers in each different region and stacking and/ Or drain region isolation.Although being not shown in Figure 23, those skilled in the art will appreciate that, it when needed, can be with It is connect by (for example, as illustrated by contact portion 154,155 in Fig. 6) contact in areas of disconnection and for jumper connection The metal layer of contact portion come provide by area of isolation (2090) disconnect region between electric continuity.Further it is to be noted that It is not need to provide the areas of disconnection across external signal is not connected to --- public source/drain region of such as disconnection (120D/130C) (referring to Figure 20 B cascode configuration in FIG) --- electric continuity because areas of disconnection cannot prevent electric current across The flowing of the length of corresponding finger.

With continued reference to Figure 23, the disconnection of gate polysilicon structure (110D) provides interval, is used for polysilicon protrusion (510E) extends beyond the corresponding distance in the interval between neighboring gates polysilicon structure (110E) and (110D), and passes through The disconnection for public source/drain region (120D/130C) that area of isolation (2090) is formed and public source region (120C) Be broken as by with transistor T_EThe ontology that limits of the associated each polysilicon protrusion (510E) of each finger it is prominent Portion provides conducting channel, wherein ontology protruding portion is in the silicon area for generally falling into public source/drain region (120D/130C) Upper extension.Finally, the body contact region (540E) being isolated with region (120D/130C) and (120C) is abutting area of isolation (2090) it is formed in region, with to transistor T_EEach finger provide according to the docking ontology of this teaching connection.Ontology Contact area (540E) is prominent in the far-end and ontology of the ontology protruding portion limited by two polysilicon protrusions (510E) Portion's contact, this is distally far from transistor T_EGrid by gate polysilicon structure (110E) limit body regions.

By the docking ontology connection configuration (2300) of Figure 23 as it can be seen that the embodiment party according to present disclosure described in Figure 23 The silicon area and polysilicon structure (grid and ontology protruding portion) of formula are shaped, so that being directed to transistor T_C、T_DAnd T_EConfiguring (2300) center line C_LThe same side finger, formed transistor T_DFinger drain region (130D) and transistor T_EFinger source region (120E) silicon area, formed transistor T_CFinger drain region (130C) and crystal Pipe T_DFinger source region (120D) silicon area and formed transistor T_C(T_CTwo fingers share) source The silicon area in polar region domain (120C) is separated from each other, but simultaneously to transistor T_EThe ontology protruding portion of finger (pass through polycrystalline What silicon protruding portion (510E) limited) and wherein ontology protruding portion extends to the offer of the region in body contact region (540E) continuously Silicon area.

Referring further to Figure 23, because of the grid body regions of the disconnection creation isolation of gate polysilicon structure (110C), Therefore it is adjacent to can be used for the engagement on every side of disconnection and in area of isolation (2090) for vertical polycrystalline silicon structure (2320) Gate polysilicon structure.According to some embodiments of present disclosure, such vertical polycrystalline silicon structure (2320) can be with It is made sufficiently wide, to cooperate with the contact portion to metal layer (not shown), which is used for (for example, via connecing The jumper connection of contact portion) restore disconnect gate polysilicon structure continuity, to restore transistor T_CContinuous grid groove.This Field technical staff is clear from the various method and structures of such contact portion for being created to metal layer.

Figure 24 is shown for the three transistor (T described in Figure 20 B_C、T_D、T_E) cascode configuration in FIG (2000B) top Transistor T_EThe another embodiment according to present disclosure docking ontology link implementation (2400).Figure 24 is shown About (top) transistor T_EDrain region (130E) center line C_LThree crystalline substances of the cascode configuration in FIG (2000B) of mirror image Body pipe (T_C、T_D、T_E) each of two fingers, which is transistor T_ETwo fingers Common drain region.As seen from Figure 24, transistor T_EThere are two finger, (each finger passes through corresponding region (110E) to tool Mark), each finger has about center line C_L(center line is along region for the similar area (110E, 120E, 130E) of mirror image Width pass through region (130E) center).Further away from center line C_LAnd about center line C_LMirror image is (centre) crystalline substance Body pipe T_DBe arranged in (bottom) transistor T_C(top) transistor T_EFinger between finger, each finger tool There is similar region (110D, 120D, 130D), wherein region (130D) and transistor T_ERegion (120E) be shared.Most Afterwards, away from center line C_LDistalmost end and about center line mirror image be (bottom) transistor T_CWith transistor T_DFinger-like The adjacent finger of part, each finger have similar region (110C, 120C, 130C), wherein region (130C) and crystal Pipe T_DRegion (120D) be it is shared, and region (120C) terminate at by line (2095) mark region at.It should infuse Meaning, Figure 24 illustrate only the top transistor T of cascode configuration in FIG (2000B)_EFinger docking ontology connection. It can see in Figure 21 A to Figure 21 E for example described above, Figure 22 and Figure 25 to Figure 29 B, to removing for cascode configuration in FIG The docking ontology connection of the finger of transistor other than top transistor.

That describes in Figure 24 links (2400) according to the docking ontology of present disclosure for transistor T_EFinger sheet Body region provides common contact area domain (2450) (for example, P+ is adulterated).As seen from Figure 24, two gate polysilicon structures (110E) is not to each extend through silicon area and enter region across (limiting by profile (2095)) boundary of silicon area (2490), but they are engaged in the region of silicon area by vertical polycrystalline silicon structure (2410), vertical polycrystalline silicon structure (2410) it limits for the public body regions below two body regions by structure (110E) restriction.Then, horizontal Polysilicon protrusion (2420) is formed at the midpoint (near or) of structure (2410), and (is included in profile towards silicon area (2095) region in) edge horizontally extend, with formed with body regions same type doping below region.It is similar In ontology protruding portion discussed above, ontology of the horizontal polycrystalline silicon protruding portion (2420) at gate polysilicon region (110E) below Low resistivity conductive path (for example, ontology protruding portion) is provided between region and body contact region (2450).According to the disclosure The illustrative embodiments of content, it is prominent around horizontal polycrystalline silicon at the near border of the silicon area limited by profile (2095) The silicon area of portion (2420) is extended to provide elongated area (2460) out, wherein is formed body contact region (2450).By scheming 24 as it can be seen that the far-end of body contact region (2450) in elongated area (2460) is formed and is abutted and limited by profile (2095) Fixed non-silicon area, while being contacted with the ontology protruding portion limited by horizontal polycrystalline silicon protruding portion (2420).Prolonging in Figure 24 The dotted line limit of the side in region is stretched without the normal boundary of the silicon area of elongated area (2460).

Although discussed above be described as the cascade to stacked transistors according to the connection of the docking ontology of this teaching The top transistor of configuration --- the transistor T of such as Figure 20 A_BWith the transistor T of Figure 20 B_E--- (finger) provides docking Ontology connection, but the connection of such docking ontology can also be used to include that two, three, four, or more stacks crystalline substance together In the identical cascode configuration in FIG (for example, Fig. 8 I to Fig. 8 K and Figure 20 A to Figure 20 B) of the stacked transistors of body pipe, with such as Docking ontology connection is provided to the finger of the bottom transistor of stacking referring to described by Figure 25 to Figure 29 B described below. In the case where the transistor that cascade stacks includes more than one finger, one or more finger-like of same transistor Part can be set such docking ontology connection and/or one or more fingers of same transistor and can be not provided with Dock ontology connection.It is provided according to the teaching of present disclosure for forming this using standard fabrication step known in the art The standard fabrication step can be used to meet him/her in the method and structure of the docking ontology connection of sample, those skilled in the art Design requirement.In the case where needing space efficiency, can be used that Figure 21 B describes into Figure 24 according to present disclosure Docking ontology links (2100B, 2200,2300,2400) to reduce the interval between adjacent finger part.

Figure 25 shows two transistor cascades with the docking ontology connection described above according to this teaching Stack a part of (for example, Figure 20 A).Figure 25 is shown about (bottom) transistor T_ASource region center line mirror image Transistor T_AAnd T_BEach of two fingers.As seen from Figure 25, linked according to the docking ontology of figure 2 described above 2 (2200) it is provided to top transistor T_B(pass through gate polysilicon structure (110B) limit) finger, docking ontology connects Knot is formed by structure (510B, 540B, 2090).As described earlier, structure (510B) limits the body zone with finger The body regions of finger are electrically connected to this by (low-resistivity) conductive region below the identical doping in domain, the conductive region Body contact zone domain (540B).Link (800B) according to the docking ontology of figure 8 described above B and is provided to cascade stacking Bottom transistor T_A, docking ontology links to be limited by structure (510A, 540A).

Figure 26 shows the three transistor cascade heaps with the docking ontology connection described above according to this teaching The a part of folded (for example, Figure 20 B).Figure 26 is shown about (bottom) transistor T_CSource region center line mirror image crystalline substance Body pipe T_C、T_DAnd T_EEach of two fingers.As seen from Figure 26, connected according to the docking ontology of figure 2 described above 3 Knot (2300) is provided to top transistor T_E(pass through gate polysilicon structure (110E) limit) finger, dock ontology Link (2300) to be formed by structure (510E, 540E, 2090).As described earlier, structure (510E) restriction and finger The identical doping of body regions below (low-resistivity) conductive region, the conductive region is by the body regions of finger electricity It is connected to body contact region (540E).Link (2200) according to the docking ontology of figure 2 described above 2 and is provided to centre Transistor T_DFinger, docking ontology connection (2200) by structure (510D, 540D, 2090) formation.Finally, according to above The docking ontology connection (800B) of Fig. 8 B of description is provided to the bottom transistor T that the cascade of three transistors stacks_C, Ontology connection (800B) is docked to limit by structure (510C, 540C).

The docking ontology connection equipped with the various teachings according to present disclosure that Figure 27 shows Figure 20 B is total to reduce Source is total to the full duration structure (2700) that three transistor cascades of the physical size of grid stacking stack.Figure 27 show about (top) transistor T_EDrain region center line mirror image transistor T_C、T_DAnd T_EEach of four fingers, top Portion's transistor is limited by gate polysilicon region (110E).As seen from Figure 27, transistor T_C、T_DAnd T_ETwo of top fingers Shape part further relates to bottom transistor T_CSource region center line mirror image, source region be included in passes through bottom transistor T_CThe region that limits of two gate polysilicon structures (110C) in, and transistor T_C、T_DAnd T_EBottom two fingers Further relate to bottom transistor T_CSource region center line mirror image, source region be included in pass through bottom transistor T_C's In the region that two gate polysilicon structures (110C) limit.

Referring further to Figure 27, the top transistor T that cascade stacks_E(being limited by structure 110E) each finger Shape part is provided with a docking ontology connecting structure (2300), intermediate transistor T_D(being limited by structure 110D) it is each There are two finger settings docks ontology connecting structure (2200), and bottom transistor T_C(being limited by structure 110C) There are four dock ontology connecting structure (800B) for each finger setting, wherein provides docking ontology above in relation to Figure 26 The details of connecting structure (800B, 2200,2300).

With continued reference to Figure 27, above with reference to the docking ontology connection of the teaching according to present disclosure of Figure 24 discussion (2400) it is provided to top transistor T_EFinger, which defines (cascade) structure (2700) of Figure 27 The center line of drain region.It is such docking ontology connection (2400) include above with reference to Figure 24 describe structure (2410, 2420,2450,2460).Therefore, top transistor T_ERestriction drain region center line finger in structure (2700) The midpoint of width has a docking ontology connecting structure (2300), and there are two docking in the opposed ends of width tool Ontology connecting structure (2400).

Figure 28 shows full duration structure identical with Figure 27, in addition to docking ontology connecting structure (2400) is removed, from And make top transistor T_EFinger respectively there is single docking ontology connecting structure (2300).

The ontology equipped with the various teachings according to present disclosure that Figure 29 B shows Figure 29 A links to reduce common source Four transistor cascades of the physical size that grid stack altogether stack the full duration structure (2900B) of (2900A).Figure 29 B shows Go out about (top) transistor T_EDrain region center line C_LThe transistor T of mirror image_B、T_C、T_DAnd T_EEach of Four fingers, top transistor pass through gate polysilicon region (110E) limit.By Figure 29 B as it can be seen that transistor T_B、T_C、T_D And T_ETwo fingers at top further relate to bottom transistor T_BSource region center line mirror image, source region Included in pass through bottom transistor T_BThe region that limits of two gate polysilicon structures (110B) in, and transistor T_B、T_C、 T_DAnd T_ETwo fingers of bottom further relate to bottom transistor T_BSource region center line mirror image, source area Domain, which is included in, passes through bottom transistor T_BTwo gate polysilicon structures (110B) limit region in.

9B referring further to Figure 2, the top transistor T that cascade stacks_E(being limited by structure 110E) it is each Finger is provided with a docking ontology connecting structure (2400), transistor T_D(being limited by structure 110D) each finger-like Part is provided with a docking ontology connecting structure (2300), transistor T_C(being limited by structure 110C) each finger set Ontology connecting structure (2200) are docked there are two setting, and bottom transistor T_B(being limited by structure 110B) each finger-like There are four dock ontology connecting structure (800B) for part setting, wherein provides docking ontology above in relation to Figure 26 and Figure 24 and connects The details of junction structure (800B, 2200,2300,2400).With full duration structure (2700) phase described in figure 2 described above 7 Right, it is a type of right that the top transistor that the full duration structure (2900B) described in Figure 29 B is only stacked to cascade provides Ontology connecting structure (structure 2400) is connect, it is right with two of the top transistor for being provided to stacking corresponding with structure (2700) Connect ontology connecting structure (2300,2400) in contrast.

By Figure 27, Figure 28 and Figure 29 B as it can be seen that transistor (such as T_E、T_D) finger docking ontology connecting structure Ontology protruding portion (for example, ontology connecting structure (2200,2300) as shown in figure 22 to figure 23 ontology protruding portion (510B, 510E)) by next (lower part) transistor (for example, T_D、T_C) adjacent finger part gate polysilicon structure in formed in Break to provide.Then, to next transistor (for example, T_D) docking ontology connection ontology protruding portion (for example, 510D) pass through In next (lower part) transistor (for example, T_C) adjacent finger part gate polysilicon structure in formed interrupt to provide, etc. Deng.Therefore, for each level, since the top transistor that the cascade of multiple transistors stacks and to down toward common source It is total to the bottom transistor that grid stack, the number of the ontology protruding portion in the finger for the transistor that cascade stacks doubles, because (docking ontology connection) sheet can be set in each of gate polysilicon structure (110D ..., 110C) for disconnection section Body protruding portion may need the disconnection in adjacent gate polysilicon structure.This is illustrated in Figure 28, wherein top Portion transistor T_EFinger be provided with a docking ontology connecting structure (2300), ontology protruding portion (510E) is next Bottom transistor T_DFinger gate polysilicon structure (110D) areas of disconnection in formed, thus in every side of disconnection Two different gate polysilicon structures (110D) are formed, each gate polysilicon structure then has a docking ontology connection Structure (2200).Inter-transistor T_DFinger two docking ontologies connection (2200) then lead to gate polysilicon structure (110C) is disconnected, hence for bottom transistor T_CFinger, with by ontology protruding portion (510E) formed disconnection together with Form four different (disconnection) gate polysilicon structures (110C).It would be recognized by those skilled in the art that total for common source The big situation of grid stack height, in the gate polysilicon structure of the finger of bottom transistor and top transistor in stacking There may be big differences for the number of disconnection.If desired, for example insertion pair can be passed through above for described in Figure 21 A It connects ontology connection and is not turned off in neighboring gates polysilicon structure to reduce this big difference, on this has effectively reset The number of the ontology protruding portion for each transistor level of face description doubles.

Finally, it will be appreciated by those skilled in the art that the various semiconductor structures described in draw above can be with Various patterns carry out physical layout, and some of patterns may include the symmetry relative to various axis, such as discussed opposite In the center line C of Figure 22 to Figure 24, Figure 27, Figure 28 and 29B_LSymmetry.According to some exemplary realities of present disclosure Mode is applied, as discribed in Figure 29 B, such semiconductor structure () can be relative to center line C '_LSymmetrically, center line C '_L The central area of the finger of cascode transistors is passed through along the length of finger.

It would be recognized by those skilled in the art that as passing through the various docking ontology above with reference to described in Figure 20 A to Figure 28 Link the cost advantage that the physical size of cascode configuration in FIG brought by permitted relatively closely spaced reduces.Physical size this Kind, which reduces, to provide performance advantage for RF circuit.For the application for needing a large amount of transistor fingers, finger it is closer Distance allows shorter interconnection length to connect them.Excessive interconnection length needed for connecting a large amount of transistor fingers may draw Enter parasitic capacitance, resistance and inductance, parasitic capacitance, resistance and inductance may be decreased RF performance.

Including cascode configuration in FIG discussed above equipped with according to the improved of the various teachings of present disclosure Such semiconductor devices of ontology connection construction can be used for such as radio frequency (RF) amplifier, radio frequency (RF) amplifier include but Be not limited to the RF power amplifier operated under various class of operations and honeycomb RF power amplifier, the class of operation include but It is not limited to switch classification D, E and F, saturation classification B and C and linear classification A and A/B.

It should be noted that although being provided using the exemplary cases of N-type SOI MOSFET according to present disclosure Various illustrative embodiments, but such exemplary cases mainly due to clearly purpose and provide.According to this hair The various embodiments of bright docking ontology connection can be equally applicable to other transistor types and other transistor technologies, special Source region it is not and/or the case where drain region extends downward into insulation layers such as SOI device " BOX " layer.

Term " MOSFET " technically refers to metal-oxide semiconductor (MOS)；Another synonym of MOSFET is " MISFET ", i.e. metal-insulator semiconductor (MIS) FET.However, " MOSFET " has become most types of insulated gate FET The universal tag of (" IGFET ").However, it is well known that the term " metal " in title MOSFET and MISFET is now logical It is often misnomer, because previous metal gate material is typically now polysilicon layer (polysilicon).Similarly, in title MOSFET " oxide " may be misnomer because using different dielectric materials, it is therefore an objective to obtain strong channel under smaller application voltage. Therefore, terms used herein " MOSFET " should not be construed as being limited to metal-oxide semiconductor (MOS) on literal, but alternatively Generally include IGFET.

It such as should be it will be evident that various embodiments of the invention can be implemented with full for those of ordinary skill in the art The various specific requirements of foot.Unless the problem of being otherwise noted above, suitable component values is otherwise selected to be design alternative, and And various embodiments of the invention can be with any suitable IC technology (including but not limited to MOSFET structure and IGFET knot Structure) it realizes.Any suitable substrate and technique can be used --- it include but is not limited to standard body silicon, silicon-on-insulator (SOI), silicon on sapphire (SOS), GaAs pHEMT and MESFET technology --- to manufacture integrated circuit embodiment.However, Inventive concept described above is for the manufacturing process (including SOS) based on SOI and the manufacturing process with similar characteristics It is particularly useful.Manufacture in the CMOS on SOI or SOS realizes low-power consumption, since FET stack can be held during operation By high power signals, the good linearity and high-frequency operation (being more than about 10GHz, particularly from about 20GHz or more).Monolithic IC is realized It is particularly useful, because parasitic capacitance can usually keep lower by well-designed.

According to specific specifications and/or technology can be realized (for example, NMOS, PMOS or CMOS and enhanced or depletion type Transistor device) adjust voltage level or reverse voltage polarity and/or logical signal polarity.It can according to need for example logical Following manner is crossed to adjust component voltage, electric current and power handling capability: adjusting device size, series connection " stacking " component are (special It is not FET) to bear higher voltage, and/or using multiple components in parallel to handle bigger electric current.It can increase in addition Circuit block to enhance the ability of disclosed circuit and/or to provide other function, it is disclosed without significantly changing Circuit function.

The application that may include the novel device and system of various embodiments includes electronic circuit, which uses In high-speed computer, communication and signal processing circuit, modem, uniprocessor or multi-processor module, single or multiple Embeded processor, data switching exchane and including multilayer, the specific application module of multi-chip module.This device and system are also Can be included as various electronic systems --- for example TV, cellular phone, personal computer (for example, laptop computer, Desktop computer, handheld computer, tablet computer etc.), work station, radio, video player, audio player (example Such as, Mp 3 player), the vehicles, Medical Devices (for example, cardiac monitor, blood pressure monitor etc.) etc. --- interior sub-portion Part.Some embodiments may include many methods.

Movement described herein can be executed with the sequence other than described sequence.About proposed in this paper Various movements described in method can be to repeat, execute in a manner of serial or parallel.

The attached drawing for forming a part of the invention is shown in which that theme can be practiced by way of illustration, not of limitation Specific embodiment.The embodiment shown is described in enough detail, so that those skilled in the art can practice herein Disclosed teaching.It can use and therefrom obtain other embodiments, so as in the model without departing from present disclosure The replacement and change of structure and logic are carried out in the case where enclosing.Therefore, which is not construed as with conditional Meaning, and the equivalent that is only assigned by the appended claims and these claims of the range of various embodiments Full scope limits.

Herein, for convenience's sake, subject matter only can be referred to come either individually or collectively body by term " invention " These embodiments, and be not intended to and scope of the present application be limited to any single invention or inventive concept of one's own accord, such as Fruit actually discloses more than one invention or inventive concept.Therefore, although particular implementation side has been illustrated and described Formula, can be in place of particular implementation with any arrangement for realizing identical purpose but be computed.Present disclosure It is intended to cover any and all adjustment or variation of various embodiments.After having read above description, embodiment of above The combination for the other embodiments not specifically described herein will be apparent to those skilled in the art.

The abstract of present disclosure is provided to meet 37C.F.R. § 1.72 (b), it is required that abstract will allow the reader to Quickly determine the property of this technology disclosure.Abstract is submitted, and is interpreted as it and be will not be used to interpret or limit power The range or meaning that benefit requires.In specific embodiment in front, for the purpose for simplifying present disclosure, individually implementing Various features are combined in mode.This method of present disclosure is not necessarily to be construed as needing than in each claim The more features being expressly recited.Exactly, invention can be found in all features less than single disclosed embodiment Theme.Therefore, appended claims is incorporated in specific embodiment herein, wherein each claim itself is as single Only embodiment.

Claims

1. a kind of semiconductor structure, comprising:

First grid polysilicon structure, limits the first noumenon region, and the first noumenon region has the first conduction type；

Second grid polysilicon structure, limits the second body regions, and second body regions have first conductive-type Type；

First drain region adjacent with the first noumenon region has the second conduction type；

First source region adjacent with the first noumenon region, with second conduction type；

Second source region adjacent with second body regions, with second conduction type；

Second drain region adjacent with second body regions, with second conduction type,

First source region and second drain region limit the first public source/drain region, and described first is public Regions and source/drain has second conduction type；

First non-conductive area of isolation is configured to be formed in second body regions and interrupt, by described second Body region is divided into two sseparated second body regions；

At least one the first noumenon contact area with first conduction type, at least one described the first noumenon contact zone Domain is formed in first public source/drain region, is separated with the first noumenon region and second body regions And abut the described first non-conductive area of isolation；And

At least one the first noumenon protruding portion with first conduction type, at least one described the first noumenon protruding portion across First public source/drain region extends, with the first noumenon region and at least one described the first noumenon contact zone Domain contact,

Wherein, the described first non-conductive area of isolation, at least one described the first noumenon contact area and it is described at least one The first noumenon protruding portion limits the first docking ontology connecting structure.

2. semiconductor structure according to claim 1, wherein the first non-conductive area of isolation is further configured to extend First public source/drain region silicon area, at least one described the first noumenon contact area and it is described at least One the first noumenon protruding portion provides continuous silicon area.

3. according to claim 1 or semiconductor structure as claimed in claim 2, wherein the first non-conductive area of isolation is also It is configured to be formed in second source region and interrupt, the source region is divided into two sseparated second source areas Domain.

4. according to claim 1 or semiconductor structure as claimed in claim 2, wherein at least one described the first noumenon is prominent The length in portion is greater than the length limited by the interval between the first noumenon region and second body regions.

5. semiconductor structure according to claim 1, wherein the first noumenon protruding portion extends along such direction, The direction with by the first noumenon region and second body regions along the direction that the width of the body regions limits Vertically.

6. semiconductor structure according to claim 1, further includes:

At least one second body contact region with first conduction type, with the first noumenon region and described Second body regions separate；And

At least one second ontology protruding portion with first conduction type, extends in second source region, And it is contacted with one in described two the second body regions separated and at least one described second body contacts.

7. semiconductor structure according to claim 6, further includes:

The second other body contact region with first conduction type, with the first noumenon region and described the Two body regions separate；And

The second other ontology protruding portion with first conduction type, extends in second source region, and And it is contacted with another in described two the second body regions separated.

8. according to claim 6 or semiconductor structure as claimed in claim 7, wherein at least one described second body contacts Region is formed in second source region, to be laterally surrounded by second source region.

9. according to claim 6 or semiconductor structure as claimed in claim 7, wherein at least one described second body contacts Region abuts second source region.

10. semiconductor structure according to claim 9, wherein at least one described second body contact region and described In addition the second body contact region forms continuous silicon area.

11. according to claim 1, semiconductor structure described in any one of 2 or 6, wherein the first grid polysilicon structure It is limited respectively with the second grid polysilicon structure with the first transistor and second transistor of cascode configuration in FIG arrangement Finger.

12. semiconductor structure according to claim 11, further includes:

The first other finger of the first transistor；

The second other finger of the second transistor；And

In addition the first docking ontology connecting structure, comprising:

I) other the first noumenon contact area；

Ii) other the first noumenon protruding portion；And

Iii) the described first non-conductive area of isolation,

Wherein, the first other finger, the second other finger and the first other docking ontology Connecting structure surrounds the semiconductor relative to the first finger, the second finger and the first docking ontology connecting structure The center line mirror image of structure, wherein the center line is the central area by second source region along second source What the width in polar region domain limited, second source region is the public affairs of second finger and the second other finger Common source region.

13. semiconductor structure according to claim 1, further includes:

Third gate polysilicon structure limits the third body regions with first conduction type；

The third drain region adjacent with the third body regions, with second conduction type, the third drain electrode Region and second source region limit the second public drain electrode/source region, and second public drain electrode/source region has Second conduction type；And

The third source region adjacent with the third body regions, with second conduction type；

Wherein, the described first non-conductive area of isolation is further configured in the third body regions and second common source It is formed and is interrupted in pole/drain region, to be respectively divided into the third body regions and second public source/drain region Two sseparated third body regions and two sseparated second public sources/drain region.

14. semiconductor structure according to claim 13 further includes the connection configuration of the second docking ontology, second docking Ontology connection, which configures, includes:

Second non-conductive area of isolation is configured in one in described two separated third body regions in formation It is disconnected；

The second body contact region with first conduction type, in second public source/drain region area It is formed in domain, is separated with second body regions and the third body regions and abut the described second non-conductive isolated area Domain；And

The second ontology protruding portion with first conduction type, across second public source/drain region region Extend, contacted with one in described two the second body regions separated and second body contact region,

Wherein, second public source/drain region region is described two the second separated public source/drain electrodes In region with the one adjacent region in described two the second body regions separated.

15. semiconductor structure according to claim 14, wherein the second non-conductive area of isolation is further configured to prolong The silicon area of the second public source region/drain region is stretched, for second body contact region and second described Body protruding portion provides continuous silicon area.

16. according to claim 14 or claim 15 described in semiconductor structure, wherein the second non-conductive area of isolation It is further configured to be formed in the third source region and interrupt, the source region is divided into two sseparated third source electrodes Region.

17. according to claim 14 or claim 15 described in semiconductor structure, wherein at least one described second ontology is prominent The length in portion is greater than the length limited by the interval between second body regions and the third body regions out.

18. semiconductor structure according to claim 14, wherein the second ontology protruding portion prolongs along such direction It stretches, the direction is vertical with the direction limited by second body regions and the third body regions.

19. semiconductor structure according to claim 14, further include in described two the second body regions separated Another associated second other docking ontology connection configuration.

20. semiconductor structure according to claim 19, wherein the second other docking ontology, which links, includes:

In addition the non-conductive area of isolation of second is configured to another in described two separated third body regions Middle formation is interrupted；

The second other body contact region with first conduction type, in second public source/drain region It is formed in the region in domain, separated with second body regions and the third body regions and abuts second in addition Non-conductive area of isolation；And

The second other ontology protruding portion with first conduction type, across second public source/drain region Region extend, in described two the second body regions separated another and it is described in addition the second body contact region Contact,

Wherein, second public source/drain region region is described two the second separated public source/drain electrodes In region in described two the second body regions separated described in another adjacent region.

21. semiconductor structure according to claim 20, wherein the second other non-conductive area of isolation is also matched It is set to the silicon area for extending the second public source/drain region, for other second body contact region and institute It states the second other ontology protruding portion and continuous silicon area is provided.

22. according to semiconductor structure described in claim 20 or claim 21, wherein described other second it is non-conductive every It is further configured to be formed in the third source region from region and interrupt, to be further divided into the source region further Separated source region.

23. according to semiconductor structure described in claim 20 or claim 21, wherein the second other ontology is prominent The length in portion is greater than the length limited by the interval between second body regions and the third body regions.

24. semiconductor structure according to claim 20, wherein the second other ontology protruding portion is along such side To extension, the direction is vertical with the direction limited by second body regions and the third body regions.

25. semiconductor structure according to claim 19 further includes and one in the third body regions separated At least one associated third docks ontology connecting structure, at least one third docking ontology connecting structure includes:

Third body contact region with first conduction type, with second body regions and the third ontology Region separates；And

Third ontology protruding portion with first conduction type, across the third source region extend, and with it is described One in separated third body regions and third body contact region contact.

26. semiconductor structure according to claim 25 further includes multiple third docking ontology connecting structures, each third It is associated from the different third body regions in the third body regions separated to dock ontology connecting structure.

27. according to semiconductor structure described in claim 25 or claim 26, wherein the third body contact region exists It is formed in the third source region, to be laterally surrounded by the third source region.

28. semiconductor structure according to claim 26, wherein in the multiple third docking ontology connecting structure extremely A few third body contact region abuts the third source region.

29. semiconductor structure according to claim 28, wherein two in the multiple third docking ontology connecting structure A or more third body contact region forms continuous silicon area.

30. semiconductor structure described in any one of 4,19,25 and 26 according to claim 1, wherein the first grid is more Crystal silicon structure, the second grid polysilicon structure and the third gate polysilicon structure are limited matched with cascade respectively Set the first transistor of arrangement, the finger of second transistor and third transistor.

31. semiconductor structure according to claim 30, further includes:

The first other finger of the first transistor；

The second other finger of the second transistor；

The other third finger of the third transistor；

At least one the first other docking ontology connecting structure, comprising:

I) other the first noumenon contact area；

Ii) other the first noumenon protruding portion；And

Iii) the described first non-conductive area of isolation；And

At least one the second other docking ontology connecting structure, comprising:

Iv) the second other body contact region；

V) the second other ontology protruding portion；And

Vi) the described second non-conductive area of isolation；

Wherein, the first other finger, the second other finger, the other third finger, described In addition the first docking ontology connecting structure and the second other docking ontology connecting structure relative to the first finger, Second finger, third finger, the first docking ontology connecting structure and the second docking ontology connecting structure, enclose Around the center line mirror image of the semiconductor structure, wherein the center line is by the central area edge of the third source region The width of the third source region limit, the third source region is the third finger and described other the The public source region of three fingers.

32. a kind of semiconductor structure, comprising:

At least two examples of semiconductor structure according to claim 12, at least two example around it is described at least The center line mirror image of first drain region of first finger of two examples, the center line are public along limiting The width of first drain region of first drain region, the semiconductor structure further include:

First vertical polycrystalline silicon structure, at the first end of the first grid polysilicon structure of at least two example Engage the first grid polysilicon structure, institute of the first vertical polysilicon structure qualification at least two example State the public body regions in lower section in the first noumenon region；And

First level polysilicon structure extends through the semiconductor structure from the midpoint of the first vertical polycrystalline silicon structure Silicon area first edge, the public body regions in the lower section extend to the silicon area by the first level polysilicon structure The first edge in domain.

33. semiconductor structure according to claim 32, further includes:

Second vertical polycrystalline silicon structure, at the second end of the first grid polysilicon structure of at least two example Engage the first grid polysilicon structure, institute of the second vertical polysilicon structure qualification at least two example State the public body regions in lower section in the first noumenon region；And

Second horizontal polycrystalline silicon structure extends through the semiconductor structure from the midpoint of the second vertical polycrystalline silicon structure The silicon area the second edge opposite with the first edge, the second horizontal polycrystalline silicon structure is public by the lower section Body regions extend to the second edge of the silicon area altogether.

34. a kind of semiconductor structure, comprising:

At least two examples of semiconductor structure according to claim 31, at least two example around it is described at least The center line mirror image of first drain region of first finger of two examples, the center line are public along limiting The width of first drain region of first drain region, the semiconductor structure further include:

35. semiconductor structure according to claim 34, further includes:

36. semiconductor structure according to claim 11, wherein the transistor of the cascode configuration in FIG is metal Oxide semiconductor field effect transistor (MOSFET).

37. semiconductor structure according to claim 36, wherein the transistor is using according to one of following technology Technology and manufacture: a) silicon-on-insulator (SOI) technology and b) silicon on sapphire (SOS) technology.

38. semiconductor structure according to claim 30, wherein the transistor is metal oxide semiconductor field-effect Transistor (MOSFET).

39. the semiconductor structure according to claim 38, wherein the transistor is using according to one of following technology Technology and manufacture: a) silicon-on-insulator (SOI) technology and b) silicon on sapphire (SOS) technology.

40. semiconductor structure according to claim 36 is suitable as the application selected from the group being made of following amplifier In amplifier: a) radio frequency (RF) amplifier, b) RF power amplifier, c) honeycomb RF power amplifier, d) switch RF power puts Big device, e) CMOS (complementary metal oxide semiconductor) RF power amplifier and f) honeycomb CMOS RF power amplifier.

41. semiconductor structure according to claim 40, wherein the class of operation of the amplifier is in following classification It is one or more: i) linear classification A, ii) linear classification A/B, iii) saturation classification B, iv) saturation classification C, v) switch classification D, vi) switch classification E and vii) switch classification F.

42. the semiconductor structure according to claim 38 is suitable as the application selected from the group being made of following amplifier In amplifier: a) radio frequency (RF) amplifier, b) RF power amplifier, c) honeycomb RF power amplifier, d) switch RF power puts Big device, e) CMOS (complementary metal oxide semiconductor) RF power amplifier and f) honeycomb CMOS RF power amplifier.

43. semiconductor structure according to claim 42, wherein the class of operation of the amplifier is in following classification It is one or more: i) linear classification A, ii) linear classification A/B, iii) saturation classification B, iv) saturation classification C, v) switch classification D, vi) switch classification E and vii) switch classification F.

44. a kind of semiconductor structure including multiple transistors, the semiconductor structure include:

Insulating layer；

Cover the silicon layer of the insulating layer；

The active region formed in the silicon layer, the active region extend through the silicon layer to connect with the insulating layer Touching, the active region includes the body zone of one or more fingers of each transistor in the multiple transistor Domain, source region and drain region, the multiple transistor are configured as the cascade arranged from the top to the bottom stacking, In, for the cascade stack the successive transistor of every two, the top transistor of the successive transistor of every two The drain region of the finger of the source region and bottom transistor of finger is in public source/drain region of the silicon layer It is formed；And

At least one docking ontology connecting structure associated with the top finger, comprising:

I) non-conductive area of isolation；

Ii) body contact region, the shape in the public source/drain region of the finger of two successive transistors At the area of isolation of the non-conductive area of isolation is separated and abutted with the body regions of the finger；And

Iii) ontology protruding portion region is formed in the silicon layer, the ontology with the finger of the top transistor Region and body contact region contact,

Wherein, at least one described non-conductive area of isolation is configured to:

It is formed and is interrupted in the region of the body regions of the finger of the restriction bottom transistor of the silicon layer, it will The body regions are divided into separated body regions, and

Extend the interruption in such region of the silicon layer so that the region to be divided into separated region, wherein the region The body regions and public source of the finger of the restriction one or more successive transistors adjacent with the bottom transistor/ Drain region.

45. semiconductor structure according to claim 44, further includes:

Other docking ontology connecting structure associated with the bottom finger, wherein the other docking ontology connects The body regions of the finger in the ontology protruding portion region and bottom transistor of each of junction structure separated Contact.

46. semiconductor structure according to claim 45, in which:

Each finger of transistor in the multiple transistor includes the number with the body regions of each finger separated The associated docking ontology connecting structure of mesh equal number, and

The ontology protruding portion region of each of the associated docking ontology connecting structure is separated with each finger Body-region contact.

47. according to semiconductor structure described in claim 44 or claim 45, in which:

The cascade is stacked including the first top transistor and the last one bottom transistor,

Each transistor in the multiple transistor that the cascade stacks includes two or more fingers；And

The region of any two fingers of each transistor surrounds the central area by public source region along the public affairs The center line mirror image that the width in common source region limits, the public source region is the two of the last one bottom transistor The source region of a finger.

48. semiconductor structure according to claim 47, wherein the semiconductor structure is relative to the center line pair Claim.

49. semiconductor structure according to claim 47, wherein each finger of first top transistor includes One and the associated docking ontology connecting structure of only one.

50. semiconductor structure according to claim 47, wherein the transistor adjacent with first top transistor Each finger includes one and the associated docking ontology connecting structure of only one.

51. semiconductor structure according to claim 50, wherein the region of any two fingers of each transistor It is still around the center line mirror image limited by the central area of common drain region along the width of the common drain region, it is described Common drain region is the drain region of two fingers of first top transistor, and described two fingers include first Top finger and the second top finger, the semiconductor structure further include:

Vertical polycrystalline silicon structure engages the grid polycrystalline silicon knot of first top finger and second top finger Structure, body regions of the vertical polysilicon structure qualification for first top finger and second top finger The public body regions in lower section；And

Horizontal polycrystalline silicon structure extends through the silicon area of the semiconductor structure from the midpoint of the vertical polycrystalline silicon structure Edge, the public body regions in the lower section extend to the edge of the silicon area by the horizontal polycrystalline silicon structure.

52. semiconductor structure according to claim 51, wherein the semiconductor structure relative to along one or The length of more fingers passes through one or more finger of each transistor in the multiple transistor The center line at center is symmetrical.

53. semiconductor structure according to claim 48, wherein the semiconductor structure relative to along one or The length of more fingers passes through one or more finger of each transistor in the multiple transistor The center line at center is symmetrical.

54. semiconductor structure according to claim 49, wherein the semiconductor structure relative to along one or The length of more fingers passes through one or more finger of each transistor in the multiple transistor The center line at center is symmetrical.

55. a kind of for providing the method that ontology links to the transistor arranged with cascode configuration in FIG, the cascade is matched It sets and includes:

Second drain region adjacent with second body regions, with second conduction type, and

The described method includes:

Interruption is formed in second body regions by the first non-conductive area of isolation, by second body regions point At two sseparated second body regions；

Being formed in first public source/drain region, there is at least one the first noumenon of first conduction type to connect Region is touched, at least one described the first noumenon contact area separates simultaneously with the first noumenon region and second body regions And abut the first non-conductive area of isolation；And

At least one the first noumenon protruding portion with first conduction type is formed, at least one described the first noumenon is prominent Portion extends across first public source/drain region, connects with the first noumenon region and at least one described the first noumenon Region contact is touched,