CN109314132B

CN109314132B - Butt body contact for SOI transistors

Info

Publication number: CN109314132B
Application number: CN201680085521.9A
Authority: CN
Inventors: 西蒙·爱德华·威拉德
Original assignee: PASSION
Current assignee: PASSION
Priority date: 2016-03-23
Filing date: 2016-06-29
Publication date: 2021-10-29
Anticipated expiration: 2036-06-29
Also published as: CN109314132A; SG11201807808WA; WO2017164904A1; DE112016006634T5; CN114122141A

Abstract

Systems, methods, and devices for improved body joint configurations are described. The improved body tie configuration is configured such that a lower resistance body tie is present when the transistor is "off" (Vg is about 0 volts). When the transistor is "on" (Vg > Vt), the resistance to the body link is much higher, reducing the performance penalty associated with the presence of the body link. Space-efficient body tie constructions suitable for cascode configurations are also described.

Description

Butt body contact for SOI transistors

Cross Reference to Related Applications

This application is related to U.S. application No. 14/945,323 filed on 11/18/2015, the disclosure of which is incorporated herein by reference in its entirety.

Technical Field

Various embodiments described herein relate generally to systems, methods, and apparatuses for suppressing floating body effects in semiconductor devices.

Background

Floating body silicon-on-insulator (SOI) transistors are limited in operating voltage and power due to accumulated hot carriers, which may increase the potential of the body region of the SOI transistor. Body-tied (tied) SOI transistors have been shown to extend voltage and power handling capabilities compared to floating body SOI transistors.

For drain-to-source voltages (Vds) greater than about 3.2 volts, floating body SOI transistors have been shown to drift hot carriers that are not conductive (e.g., when in a non-conductive state, the magnitude of the threshold voltage decreases and the drain current increases). Body-bonded devices have been shown not to suffer from this mechanism.

When a floating body transistor is conductive, under moderate bias of the various levels of drain-source voltage of the transistor, the corresponding floating body effect may cause a sudden decrease in the output impedance of the transistor, which in turn may reduce the analog gain of the transistor and increase the complexity of the corresponding device modeling. The body-tied device (transistor) suppresses the reduction of the output impedance and extends the range of higher output impedance for higher drain-source voltages.

Body ties on wide (large gate width) transistors with conventional (H-gate, T-gate) body tie structures become less effective at suppressing device degradation due to high resistance and increased parasitic capacitance that reduce the ability to control floating body effects. In particular, for large transistor widths, conventional body-tied devices (e.g., H-gates, T-gates) are less effective at suppressing such degradation, and the increased drain-gate capacitance associated with conventional body-tied devices may reduce performance in applications using such transistors, such as Radio Frequency (RF) amplifier applications.

Although body bonding may improve the voltage handling capability of a transistor, the on-state conductivity of the transistor may be reduced.

Disclosure of Invention

It may be desirable to extend the voltage and power handling capability of semiconductor devices, such as RF Integrated Circuits (ICs), by providing improved body tie configurations. Such semiconductor devices may include Metal Oxide Semiconductor (MOS) Field Effect Transistors (FETs), Complementary Metal Oxide Semiconductor (CMOS) FETs, and in particular MOSFETs and CMOSFETs fabricated on silicon-on-insulator (SOI) substrates and silicon-on-sapphire (SOS) substrates. Such semiconductor devices equipped with improved body tie configurations according to various teachings of the present disclosure may be used, for example, for Radio Frequency (RF) amplifiers including, but not limited to, RF power amplifiers and cellular RF power amplifiers operating under various operating classes including, but not limited to, switch classes D, E and F, saturation classes B and C, and linear classes a and a/B.

According to a first aspect of the present disclosure, a semiconductor structure is presented, the semiconductor structure comprising: a first gate polysilicon structure defining a first body region, the first body region having a first conductivity type; a second gate polysilicon structure defining a second body region, the second body region having the first conductivity type; a first drain region adjacent the first body region and having a second conductivity type; a first source region adjacent the first body region and having a second conductivity type; a second source region adjacent to the second body region and having a second conductivity type; a second drain region adjacent the second body region and having a second conductivity type; the first source region and the second drain region define a first common source/drain region having the second conductivity type; a first non-conductive isolation region configured to form an interruption in the second body region to divide the second body region into two separate second body regions; at least one first body contact region of the first conductivity type formed within the first common source/drain region, separate from the first and second body regions and abutting the first non-conductive isolation region; and at least one first body protrusion (tab) of the first conductivity type extending across the first common source/drain region in contact with the first body region and the at least one first body contact region, wherein the first non-conductive isolation region, the at least one first body contact region, and the at least one first body protrusion define a first butted (clipped) body tie structure.

According to a second aspect of the present disclosure, a semiconductor structure comprising a plurality of transistors is described, the semiconductor structure comprising: an insulating layer; a silicon layer covering the insulating layer; an active region formed in the silicon layer, the active region extending through the silicon layer to contact the insulating layer, the active region including a body region, a source region, and a drain region of one or more fingers of each transistor of the plurality of transistors, the plurality of transistors configured as a cascode stack arranged from top to bottom, wherein, for each two consecutive transistors of the cascode stack, the source region of the finger of the top transistor and the drain region of the finger of the bottom transistor of each two consecutive transistors are formed in a common source/drain region of the silicon layer; and at least one docking body coupling structure associated with the top finger, comprising: i) a non-conductive isolation region; ii) a body contact region formed within the common source/drain region of the fingers of two successive transistors, separate from the body regions of the fingers and abutting the isolation region of the non-conductive isolation region; and iii) a body protrusion region formed in the silicon layer, in contact with the body region and the body contact region of the finger of the top transistor, wherein the at least one non-conductive isolation region is configured to: forming a break in a region of the silicon layer defining a body region of a finger of the bottom transistor to divide the body region into separate body regions, and extending the break in the region of the silicon layer defining the body region and a common source/drain region of the finger of one or more successive transistors adjacent the bottom transistor to divide the region into separate regions.

According to a third aspect of the present disclosure, there is provided a method for providing body tie to transistors arranged in a cascode configuration, the cascode configuration comprising: a first gate polysilicon structure defining a first body region, the first body region having a first conductivity type; a second gate polysilicon structure defining a second body region, the second body region having the first conductivity type; a first drain region adjacent the first body region and having a second conductivity type; a first source region adjacent the first body region and having a second conductivity type; a second source region adjacent to the second body region and having a second conductivity type; a second drain region adjacent the second body region and of the second conductivity type, the first source region and the second drain region defining a first common source/drain region of the second conductivity type; the method comprises the following steps: forming an interruption in the second body region by the first non-conductive isolation region to divide the second body region into two separate second body regions; forming at least one first body contact region of the first conductivity type within the first common source/drain region, the at least one first body contact region being separate from the first and second body regions and abutting the first non-conductive isolation region; and forming at least one first body protrusion of the first conductivity type extending across the first common source/drain region in contact with the first body region and the at least one first body contact region, wherein the first non-conductive isolation region, the at least one first body contact region, and the at least one first body protrusion define a first butted body tie structure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate one or more embodiments of the disclosure and, together with the description of the example embodiments, serve to explain the principles and implementations of the disclosure.

Fig. 1A shows a top view of an N-type MOSFET transistor device.

Fig. 1B shows a cross-sectional view of the transistor device in fig. 1A along line a.

Fig. 1C shows a schematic representation of the transistor device of fig. 1A.

Fig. 2A shows a top view of an N-type MOSFET transistor device with a T-gate body tie according to a prior art embodiment.

Fig. 2B shows a schematic representation of the transistor device of fig. 2A.

Fig. 2C shows a top view of an N-type MOSFET transistor device with an H-gate body tie, according to a prior art embodiment.

Fig. 3A shows a top view of an N-type MOSFET transistor device with source-body tie according to a prior art embodiment.

Fig. 3B shows a schematic representation of the transistor device of fig. 3A.

Fig. 4A shows a top view of an N-type MOSFET transistor with a butted body contact according to an embodiment of the present disclosure.

Fig. 4B shows a cross-sectional view of the transistor device in fig. 4A along line B.

Fig. 5A shows a top view of an N-type MOSFET transistor with a butted body contact according to an alternative embodiment of the present disclosure.

Fig. 5B shows a cross-sectional view of the transistor device in fig. 5A along line C.

Fig. 5C shows a schematic representation of the transistor device of fig. 4A and 5A.

Fig. 6 shows a top view of an N-type MOSFET transistor with a butted body contact, wherein the body contact is provided via a plurality of different body protrusions, according to an alternative embodiment of the present disclosure.

Fig. 7A and 7B show top views of alternative embodiments to the embodiment shown in fig. 6.

Fig. 8A illustrates a top view of two adjacent fingers of a transistor device having a butted body contact, wherein respective polysilicon protrusions are created within a common source region, in accordance with an embodiment of the present disclosure.

Fig. 8B shows an alternative embodiment to that shown in fig. 8A, in which the respective polysilicon projections are bonded.

Fig. 8C-8H illustrate top views of stacked transistors with abutting body contacts according to various embodiments of the present disclosure.

Fig. 8I schematically shows the stacked transistor of fig. 8C and 8D.

Fig. 8J schematically shows the stacked transistor of fig. 8E.

Fig. 8K schematically shows the stacked transistor of fig. 8F.

Fig. 9A shows a top view of a transistor with isolated butted body contacts.

Fig. 9B shows a cross-sectional view of the transistor device in fig. 9A along line F.

Figure 9C shows a top view of two adjacent fingers of a transistor device with isolated abutting body contacts.

Fig. 9D shows a schematic representation of the transistor device of fig. 9A-9B.

Fig. 10A shows a graph of butt body connection (contact) resistance, gate bias voltage, and body protrusion width.

Fig. 10B shows a graph comparing drain-source currents in the off-state for two floating body transistors and two transistors with butted body ties according to various embodiments of the present disclosure.

Fig. 11A and 11B show graphs of drain-source current versus drain-source voltage for otherwise identical transistor devices with and without abutting body ties in accordance with embodiments of the present disclosure.

Fig. 12A-12C show graphs representing the effect of the number of body protrusions of a butted body-tied transistor according to the present invention on the drain-source current versus drain-source voltage response of the same transistor device.

Fig. 12D shows a graph representing the output conductance of a butted body-tied transistor device versus the number of body protrusions, in accordance with various embodiments of the present invention.

Fig. 13 shows a graph representing the effect of hot carrier injection on a floating body transistor.

Fig. 14 shows a diagram representing the effect of a butt-body joint with respect to hot carrier injection according to the present invention.

Fig. 15A and 15B show comparative graphs representing total gate capacitance and drain-gate capacitance for the same transistor with various body ties and without body ties.

FIGS. 16A-16B illustrate f representing a butted body-tied pair transistor according to the present invention_TFrequency sum f_maxA comparison of the effect of frequency.

Fig. 17 shows a comparative graph representing the effect of abutting body junctions on adjacent channel leakage ratio performance of an RF power amplifier according to the present invention.

Fig. 18 shows a graph showing the effect of a butted body junction according to the present invention on the gain versus output power (Pout) of a transistor at a relatively high voltage bias at the same bias.

Fig. 19 shows a comparative graph representing the effect of a butted body junction according to the invention on the bias current (Ibias) for a given output power of an RF power amplifier.

Fig. 20A shows a schematic representation of a cascode configuration comprising two stacked transistors.

Fig. 20B shows a schematic representation of a cascode configuration including three stacked transistors.

FIG. 21A shows the top transistor T provided to the cascode configuration represented by FIG. 20A for the case where the cascode configuration of transistors has one finger_BAccording to embodiments of the present disclosure.

Fig. 21B and 21D show the top transistor T provided to the cascode configuration represented by fig. 20A for the case where the transistors of the cascode configuration each have one finger_BAccording to embodiments of the present disclosure.

Fig. 21C and 21E illustrate methods for creating body contact regions for the docking body joint depicted in fig. 21B and 21D, respectively.

FIG. 22 shows the top transistor T provided to the cascode configuration represented by FIG. 20A for the case where the transistors of the cascode configuration each have two fingers_BAccording to embodiments of the present disclosure. FIG. 22 shows the transistor T provided to the top_BSuch a space efficient butt body joining of each finger of (a) is provided.

Fig. 23 shows the top transistor T provided to the cascode configuration represented by fig. 20B for the case where the transistors of the cascode configuration each have two fingers_EAccording to embodiments of the present disclosure. FIG. 23 shows a transistor T provided to the top_ESuch a space efficient butt body joining of each finger of (a) is provided.

Fig. 24 shows the top transistor T provided to the cascode configuration represented by fig. 20B for the case where the transistors of the cascode configuration each have two fingers_EAccording to the present disclosureThe docking bodies of the embodiments are coupled.

Fig. 25 shows a portion of the cascode configuration represented by fig. 20A with the butted body ties provided to the various fingers of the transistors of the cascode configuration according to fig. 8B and 22.

Fig. 26 shows a portion of the cascode configuration represented by fig. 20B with the butted body ties provided to the various fingers of the transistors of the cascode configuration according to fig. 8B, 22 and 23.

Fig. 27 shows the full width structure of the cascode configuration represented by fig. 20B with the butted body ties provided to the various fingers of the transistors of the cascode configuration according to fig. 8B, 22, 23 and 24.

Fig. 28 shows the full width structure of the cascode configuration represented by fig. 20B with the butted body ties provided to the various fingers of the transistors of the cascode configuration according to fig. 8B, 22 and 23.

Fig. 29A shows a schematic representation of a cascode configuration including four stacked transistors.

Fig. 29B shows the full width structure represented by fig. 29A with the cascode configuration of the butt-body junction according to fig. 8, 22, 23 and 24, with the topmost transistor T to the cascode configuration_EThe docking body coupling of (3) is only according to the docking body coupling of fig. 24.

Detailed Description

Throughout this specification, embodiments and variations have been described for the purpose of illustrating the use and implementation of the inventive concepts. The illustrative description is to be understood as presenting examples of the inventive concept and not as limiting the scope of the concept disclosed herein.

In the present disclosure, an apparatus is described that provides all of the benefits of conventional body-tied semiconductor devices, such as H-gate MOSFET devices and T-gate MOSFET devices, without the limitations and degradations associated with these configurations. Methods for making and using such devices are also described.

According to various embodiments of the present disclosure, a butted body contact in a semiconductor device may improve the operational performance of the semiconductor device. As used herein, the expressions "butt-body contact", "butt-body bond", and "butt-body bonded" are equivalent, and these expressions relate to various methods and apparatus for providing body bonding to a semiconductor device, described in the following paragraphs according to the present disclosure with the aid of various corresponding figures. In the exemplary case of a transistor device, such a butt-body joint may be provided by: the body region of the transistor device is "connected" to the source region of the transistor device via a conductive path having a desired conductivity (e.g., resistivity). Alternatively, abutting body ties may be provided as open (open) contacts for tying the body region of the transistor device to any desired external potential provided at the open contacts, which are resistively connected to the body region of the transistor device via a conductive path of desired conductivity.

The abutting body joining according to various embodiments of the present disclosure may be achieved by providing the semiconductor device with some additional structures such as a "body protrusion" as exemplified by item (512) in fig. 5B, a "polysilicon protrusion" as exemplified by item (510) in fig. 5A, and a "body contact region" as exemplified by item (540) in fig. 5A and 5B. Such structures, as well as any other structures related to the implementation of docking body coupling according to the present disclosure, will be further described in the following paragraphs.

As used herein, a body protrusion (e.g., item (512) in fig. 5B) is a region having the same type of doping as a body region (e.g., item (112) in fig. 5B) below a gate polysilicon structure (e.g., item (110) in fig. 5A-5B)) of a semiconductor device (i.e., transistor body, transistor channel, transistor conduction channel), which branches off from and adjoins the body region below the gate polysilicon structure of the semiconductor device (branch out) and extends to or through a source region (e.g., item (120) in fig. 5A-5B) or a drain region of the semiconductor device. In one exemplary embodiment of the present disclosure, such body protrusions may be created with a corresponding polysilicon protrusion (e.g., item (510) in fig. 5A) branching off from the gate polysilicon structure of the device, and thus may be an integral part of the gate polysilicon structure. The polysilicon protrusion is used as a mask to prevent doping of the semiconductor region under the polysilicon protrusion, thereby creating a body protrusion.

As used herein, a body contact region (e.g., item (540) in fig. 5A-5B) is a region having the same type of doping as the body region (e.g., item (112) in fig. 5B) for providing a low resistivity conductive path to a desired potential to be applied to the body region of the device. Thus, the body protrusion (e.g., item (512) in fig. 5B) provides a conductive path between the body region having a first resistivity (e.g., R1 in fig. 5C) and the body contact region, and the body contact region provides a conductive path to a desired body tie potential having a second resistivity (e.g., R2 in fig. 5C).

As presented in the following portions of the present disclosure, docking body contacts according to various embodiments of the present disclosure may be provided by connecting one or more body protrusions to a body region of a device. According to various embodiments of the present disclosure described later, such body protrusions are in contact with a body contact region having the same type of doping as the body region under the gate polysilicon structure. According to various embodiments of the present disclosure, the doping of the body contact region may have an associated concentration that is similar to, less than, or greater than the associated doping concentration of the body region. According to various embodiments of the present disclosure described later, the body contact region may be created in a source region adjacent to the gate polysilicon structure or may be created in a region adjacent to the source region adjacent to the gate polysilicon structure. Alternative embodiments are also possible in which the body contact region is within the drain region of the semiconductor device.

Embodiments as described herein are exemplified by N-type MOSFET devices. One of ordinary skill in the art will readily apply the inventive concepts disclosed herein to other types of semiconductor devices, such as P-type MOSFET devices, by applying different types of doping schemes as appropriate. Embodiments in accordance with the present invention may also be applied to extended drain devices such as Laterally Diffused Metal Oxide Semiconductor (LDMOS) devices, and other gated transistors or devices.

According to various embodiments of the present disclosure, a semiconductor device having a butted body contact may include a semiconductor device including a Field Effect Transistor (FET) formed on a silicon-on-insulator (SOI). The FET devices may include Complementary Metal Oxide Semiconductor (CMOS), Metal Oxide Semiconductor Field Effect Transistors (MOSFET), and other types of Field Effect Transistor (FET) devices. In an embodiment, a silicon-on-insulator (SOI) may include a silicon-on-sapphire (SOS).

As used herein, MOSFET P-body (e.g., item (112) in fig. 5B), P-body region, and body region refer to the P-doped silicon under the gate polysilicon structure (e.g., item (110) in fig. 5A-5B), which provides a conductive channel to the MOSFET during operation. The body region and body protrusion (e.g., item (512) in fig. 5B) create a continuous P-doped region beneath the gate polysilicon structure and polysilicon protrusion (e.g., item (510) in fig. 5A-5B).

In one embodiment according to the present disclosure, the P-doped silicon (away from the body of the gate polysilicon structure) under the distal end of the polysilicon protrusion is in contact with a P + doped region (body contact region) of the semiconductor device. As mentioned above, such P + doped regions defining the body contact regions are regions having the same type of doping as the body regions underlying the gate polysilicon structure and may have any doping concentration and are not limited to P + doping.

In one exemplary embodiment according to the present disclosure, the body contact region may have a square or rectangular shape. As will be described in later portions of the disclosure, the body contact region may provide a low resistivity conductive path to a desired body tie potential via a metal contact or via a low resistivity layer, such as a suicide layer, atop the contact region. Furthermore, the body contact region may be in contact with the source region of the semiconductor device to provide source body tie, or isolated from any active regions of the device (e.g., source/drain regions), to enable any potential to be provided to the body (decoupled from the source potential).

In one embodiment according to the present disclosure, multiple polysilicon projections (branching off from the gate polysilicon) may be provided for the same gate polysilicon structure, with respective body projections (P-doped regions under the polysilicon projections) connected to different and separate body contact regions (e.g., fig. 7A described later).

In another embodiment according to the present disclosure, a plurality of polysilicon projections are provided for the same gate polysilicon, and the respective body projections may be connected to the same continuous body contact region (e.g., fig. 7B described later).

In one embodiment according to the present disclosure, the body protrusion is in contact with the body contact region at a distal end of the body protrusion distal from the body region of the gate.

In one embodiment according to the present disclosure, a MOSFET transistor includes a plurality of fingers with an associated plurality of gate polysilicon structures, with a respective polysilicon protrusion connected to each gate polysilicon structure (e.g., fig. 8A-8B described later).

In yet another embodiment of the present disclosure, the body protrusion corresponding to the polysilicon gate of the adjacent finger may be connected to the same continuous P + doped region (e.g., fig. 8B described later).

In yet another embodiment of the present disclosure, polysilicon protrusions branching off from the polysilicon gates of adjacent fingers may be joined (e.g., fig. 8B described later).

According to some embodiments of the present disclosure, a body contact region connected to a distal end (remote from the body region) of the body protrusion is created within a source region of the MOSFET transistor, thereby creating a P + doped region within an N + doped source region. According to yet another embodiment of the present disclosure, such a body contact region is created in a region adjacent to and in contact with the source region of the MOSFET transistor. It should be noted that although the body contact region is described as a P + doped region, this should not be taken as limiting the scope of what the inventors regard as their invention, as various doping levels of the body contact region, including doping similar to that of the body region, may also be used in the butt-body contact invention.

Further explanation of the above embodiments according to the present disclosure will be provided in a subsequent section of the present disclosure with reference to the associated drawings.

Fig. 1A shows a top view of an N-type SOI MOSFET device (100). The gate finger (110) is shown between the source region (120) and the drain region (130). The gate fingers (110) have a length L_GAnd width W_G. In one aspect, the gate fingers may be made via a gate polysilicon structure (110), the gate polysilicon structure (110) may block implantation of dopant ions for doping adjacent source and drain regions of the MOSFET. One of ordinary skill in the art will readily recognize that a multi-fingered SOI device may have a plurality of such fingers, wherein each finger may include a respective gate polysilicon structure (110), a drain region (130) having a respective drain contact (155), and a source region (120) having a respective source contact (145). In some embodiments, adjacent fingers may share respective drain and/or source regions.

Fig. 1B shows a cross-sectional view of the N-type SOI MOSFET device (100) of fig. 1A along line a. In one aspect, a gate polysilicon structure (110) is shown disposed on an insulating gate silicon oxide layer (115). In one aspect, the body region (112) under the gate polysilicon structure (110) is doped with P-type dopants (P-body), and the source region (120) and the drain region (130) are heavily implanted with N-type dopants (N +). As shown in the cross-sectional view of fig. 1B, the regions (112, 120, 130) of the SOI MOSFET device are created atop a Buried Oxide (BOX) layer (150) formed on a semiconductor substrate (160), and thus, due to the insulating nature of the BOX layer (150), no conductive path between the regions (112, 120, 130) and the semiconductor substrate (body) is provided in the SOI MOSFET depicted in fig. 1A and 1B. One skilled in the art will readily recognize that regions (112, 120, 130) of an SOI MOSFET device (100) may be formed in a thin silicon layer (180) overlying an insulating layer (150), such regions (112, 120, 130) extending through the depth of the thin silicon layer (180) to reach the insulating layer (150). Accordingly, and as is known in the art, the SOI MOSFET device (100) may be referred to as a thin film SOI MOSFET, the thin film being referred to as a thin silicon layer (180). It should be noted that various embodiments according to the present disclosure, which will be described below, may be implemented in thin film SOI MOSFET devices.

The SOI MOSFET device (100) depicted in fig. 1A and 1B does not provide a body tie, which, as is known to those skilled in the art, is a connection between the P-body and a reference (fixed) potential, such as the source region of the device. Such SOI devices, schematically represented in fig. 1C, are floating body devices and are therefore susceptible to the disadvantages discussed in the above section of the present disclosure.

Fig. 2A shows a top view of an N-type MOSFET transistor (200) with a T-gate body tie structure according to a prior art embodiment. In the prior art embodiment represented by fig. 2A, the gate polysilicon structure (110) is extended to include a structure (210), the structure (210) complementing the conventional structure (110) for creating the conductive channel (i.e., body region, channel region) of the device (200). Thus, the T-shaped polysilicon structure (110, 210) enables the formation of a corresponding P body region underneath the polysilicon, which P body region is in contact with a P + region (240), the latter P + region (240) allowing a low resistance contact with the P-region underneath the polysilicon extension region (210) and thus a transistor body underneath the polysilicon region (110). The P-body region under the polysilicon region 210 also allows for isolation of the source region 120 and the drain region 130 relative to the heavily doped region 240. The skilled person will appreciate that the T-gate body tie structure of the prior art body tie transistor (200) allows the P + region (240) to be in electrical contact with the constant voltage node to provide a conductive path for floating charges in the channel region of the transistor (200). According to some implementations, the P + region (240) may be in contact with an overlying metal layer, which may be connected to a constant voltage. Such a constant voltage may be a voltage applied to the source terminal of the transistor, or a reference potential such as ground or a fixed (negative) voltage. Those skilled in the art will appreciate that the top view depicted in fig. 2A is a simplified top view of the transistor (200) as only the structures/elements relevant to the description of the (prior art) embodiment are shown. Those skilled in the art will appreciate that other structures/elements such as drain/source contacts have been omitted from such figures to make clarity. Generally, the same approach is taken in presenting the various figures that form a part of this disclosure.

The T-gate body tie structure used in the N-type transistor (200) may reduce the floating body effect present in the transistor (100) of FIG. 1A. However, the tgate body link provides an increased parasitic capacitance (C) between the gate and source of the transistor (200) via the extended polysilicon structure (210) adjacent to the drain and source regions (130, 120)_SG) And an increased parasitic capacitance (C) between the gate and the drain of the transistor (200)_DG). Such parasitic capacitance (C)_SG，C_DG) Do not have constant capacitance values because their values can vary depending on the voltage applied to the transistor terminals. The latter parasitic capacitance (C)_SG，C_DG) Shown in fig. 2B (as a variable capacitance), fig. 2B schematically represents a transistor (200), which transistor (200) comprises a connected body contact providing a desired potential. Those skilled in the art will readily appreciate the adverse effects of such parasitic capacitances on the performance of the transistor (200), which can reduce, among other things, the switching speed of the transistor and the characteristic operating frequency f of the transistor (200) using a T-gate body tie_TAnd f_max. Due to parasitic capacitance (C)_SG，C_DG) Such capacitance may also negatively affect the linearity of the prior art transistor (200).

Alternative implementations of T-gate body tie known to those skilled in the artSuch as the H-gate body tie depicted in fig. 2C, also provides the benefit of reducing floating body effects, but at the expense of increased parasitic capacitance, which may degrade the RF performance of the device (e.g., lower f_TAnd f_max). The prior art implementation of the H-gate body tie depicted in fig. 2C has the following advantages: in the case of transistors having a large width (W)_G) With the increased parasitic capacitance (C) discussed for the case of the T-gate body tie_SG，C_DG) And associated negative effects, provides more efficient (e.g., symmetrical) body coupling. However, for large transistor widths, the H-gate or T-gate cannot provide an effective body tie to the transistor, as providing a body tie at the far end of the transistor channel would result in a higher resistance for the middle of the channel width.

Fig. 3A shows a top view of an N-type MOSFET transistor (300) with a source-body tie structure according to a prior art embodiment. In the prior art embodiment represented by fig. 3A, the body contact is provided by adding a P + region (340) in the source region (120), the P + region (340) connecting the P body region under the gate polysilicon structure (110) to the source region (120). In other words, the P + region 340 provides a low resistance path between the source region 120 and the P body region under the gate polysilicon structure 110, as schematically depicted in fig. 3B.

As with the T-gate body tie structure of fig. 2A, the source body tie structure used in the N-type transistor (300) of fig. 3A may reduce the floating body effect present in the transistor (100) of fig. 1A. Furthermore, the source-body tie structure of fig. 3A does not provide increased parasitic capacitance since the gate polysilicon structure (110), such as provided in a T-gate (and H-gate) structure, is not extended.

The region 340 in fig. 3A must link the source region 120 to the P-body region associated with the gate polysilicon structure 110, and thus, the region 340 must have a non-zero overlap (Δ) with the P-body region (see lincoln laboratories, revised 2006: 1, 6.2006, entitled "ttl Low-Power FDSOI CMOS Process," the entire contents of which are incorporated herein by reference). Such overlap may locally alter the characteristics of the conductive channel of the transistor (300) in the region where the overlap occurs, and thus may negatively affect the performance of the transistor, for example, causing a non-linear response (e.g., I-V characteristic) of the transistor (300).

The construction of source-body ties as provided by the prior art embodiment of fig. 3A may also result in increased manufacturing complexity, including aligning the P + region (340) relative to the gate polysilicon region (110). The accuracy associated with the latter alignment step can directly affect the linearity of the transistor and the consistency of the I-V characteristic of the transistor due to any variations in alignment, and also affect the cost and yield of manufacturing such transistors.

Fig. 4A shows a top view of an N-type MOSFET transistor (400) with a butted body contact according to an embodiment of the disclosure. According to an embodiment of the present disclosure, the MOSFET transistor device (400) may be a thin film SOI device including an active region (e.g., 120, 130) formed in a thin silicon layer (180 in fig. 4B) overlying an insulating layer (150 in fig. 4B), the active region extending through the depth of the thin silicon layer to reach the insulating layer. The transistor (400) includes a polysilicon protrusion (410), the polysilicon protrusion (410) branching from the gate polysilicon structure (110), passing through the source region (120), and extending beyond the source region (120) to a body contact region (440) adjacent the source region (120). Since the polysilicon protrusion (410) is a structure that abuts the gate polysilicon structure (110) (e.g., forming a single structure), a respective body protrusion is created under the polysilicon protrusion (410) that has the same type (doping) as the P body region under the gate polysilicon structure (110) (since the polysilicon protrusion (410) prevents N + implantation into the P body during the implantation phase associated with, for example, the doping of the adjacent drain (130) and source (120) regions). As can be seen in fig. 4B, such body protrusions connect the P body region under the gate polysilicon structure (110) to the body contact region (440) (shown as a P + region in fig. 4A-4B) adjacent to the source region (120). According to various embodiments of the present disclosure, the body contact region has the same type of doping as the P-body region, which may have the same concentration (e.g., P-) or a higher concentration (e.g., P +) than the concentration of the P-body region.

With further reference to fig. 4A-4B, during operation of the transistor 400, the body contact region 440 and the body protrusion 412 may provide a conductive path for carriers between the transistor body 112 and the N + source region 120, which provides a final extraction node for floating charges previously contained in the transistor body 112.

Fig. 4B shows a cross-sectional view along line B of fig. 4A of the N-type MOSFET transistor (device) (400) with a butted body contact shown in fig. 4A according to an embodiment of the invention. As can be seen in the cross-sectional view of fig. 4B, the transistor body region (112) under the gate polysilicon structure (110) is contiguous with the P body region (412), the P body region (412) being formed under the polysilicon protrusion (410), referred to herein as the body protrusion. A cross-sectional view of the transistor (400) along line a in fig. 4A can be seen in fig. 1B previously discussed.

Fig. 5A shows a top view of an N-type MOSFET transistor (500) with a butted body contact according to another embodiment of the disclosure. The transistor (500) comprises a polysilicon protrusion (510), the polysilicon protrusion (510) branching out from the gate polysilicon structure (110) into the source region (120) and extending to a P + region (540), i.e. a body contact region, created within the source region (120). Since the polysilicon protrusion (510) is a structure that is contiguous with the gate polysilicon structure (110), a corresponding body protrusion is created under the polysilicon protrusion (510) that is of the same type (doping) as the P-body region under the gate polysilicon structure (110). As can be seen in fig. 4B, such body protrusions connect the P-body region under the gate polysilicon structure (110) to the body contact region (540) formed in the source region (120).

Fig. 5B shows a cross-sectional view of the N-type MOSFET transistor (device) with butted body contacts shown in fig. 5A along line C of fig. 5A according to an embodiment of the invention. As can be seen in the cross-sectional view of fig. 5B, the body region (112) under the gate polysilicon structure (110) is contiguous with the P body region (512) (body protrusion) formed under the polysilicon protrusion (510). Furthermore, the body protrusion (512) contacts a body contact region (540) created within the source region (120) at a distal end of the body protrusion (512). A cross-sectional view of the transistor (500) along line a in fig. 5A can be seen in fig. 1B previously discussed.

As known to those skilled in the art, a low resistivity layer, such as a silicide layer, may be present on top of the exposed silicon region of the semiconductor device. Such a low resistivity layer may provide a low resistance conductive path between all points of the underlying silicon region. For example, referring to fig. 5B, a continuous silicide layer (not shown) deposited on top of region (120) and region (540) may provide a low resistivity conductive path between two adjacent regions (120) and any point of region (540).

With further reference to fig. 4A-5B, the body protrusion (412, 512) of the transistor (400, 500) according to embodiments of the present disclosure depicted in fig. 4A and 5A may provide a first resistive (conductive) path between the body region (112) and the body contact region (440, 540), and a continuous low resistivity layer, e.g., a silicide layer, deposited on top of the body contact region (440, 540) and the source region (120) may provide a second resistive path between the body protrusion (412, 512) and the source region (120). Those skilled in the art will readily appreciate that the resistance associated with the first resistive path (R1) may be substantially greater than the resistance associated with the second resistive path (R2) based on the doping type and concentration of these regions. Fig. 5C is a schematic representation of an N-type MOSFET transistor (400, 500) in which the body protrusion (412, 512) and body contact region (440, 540) provide a resistive connection between the body and source of the transistor (first and second resistive paths having equivalent resistances R1 and R2, respectively). This resistive connection is represented by the resistor R connecting the source S of the transistor to the bulk of fig. 5C (R1 + R2).

A second resistive path between the body protrusion (412, 512) and the source region (120) may be provided via an alternative method using the conductive (silicide layer) discussed above. According to embodiments of the present disclosure, metal contacts associated with different regions may be used to provide a second resistive path. For example, a metal contact atop the body contact region (440, 540) may be bridged to a metal contact (145) atop the source region (120) via a metal, creating a second low resistivity path.

With further reference to fig. 5C, in some cases it may be desirable to provide different values of resistance R to obtain the desired effect of the provided body tie. Since the resistance R2 provided by the second resistive path is very small (substantially zero) compared to the resistance R1 provided by the first resistive path, the resistance R2 cannot be used to substantially modify the resistance of the resistor R. According to various embodiments of the present disclosure, different resistance values of the resistor R may be provided by adjusting the value of the resistance R1 via parameters of the body protrusion (412, 512).

According to embodiments of the present disclosure, the resistance value of resistor R1 in fig. 5C, and thus the resistance value of resistor R, may be adjusted via the width and/or length of the polysilicon protrusion (410, 510) associated with the body protrusion (412, 512). Those skilled in the art will understand how to modify the width and/or length of the polysilicon protrusion (410, 510), and thus the body protrusion (412, 512) accordingly, the resistance R1, and thus the resistivity of the first resistive path (between region (112) and region (440, 540)) may be modified.

According to yet another embodiment of the present disclosure, the number of polysilicon projections (510, 410) of a given gate polysilicon structure may be more than one, such as two, three, four, or more (e.g., fig. 6-7B described later). The relative spacing of the polysilicon projections and the width and/or length of the polysilicon projections (410, 510) may be used to adjust the resistance value R1 of the resistive path between the body region (112) and the body contact region (440, 540), and thus the resistance value of the resistor R.

According to another exemplary embodiment of the present disclosure, the polysilicon protrusion (410, 510) may be created during a different fabrication step than the step used to fabricate the gate polysilicon structure (110). While such exemplary embodiments may introduce complexity to the overall manufacturing process, they are still possible alternatives for providing the docking body contacts of the present invention.

With further reference to fig. 4A and 5A, those skilled in the art will recognize the reduction in parasitic capacitance provided by embodiments in accordance with the present disclosure as compared to the prior art embodiment of fig. 2A. In contrast to such prior art embodiments, embodiments of the present disclosure do not introduce gate-drain parasitic capacitance C_DG. Furthermore, the gate-source parasitic capacitance C according to embodiments of the present disclosure depicted in fig. 4A and 5A is due to the relatively reduced size (width and/or length) of the polysilicon protrusion (410, 510) compared to the polysilicon region (210) of the prior art embodiment of fig. 2A_SGC of the prior art embodiment smaller than FIG. 2A_SG。

According to some embodiments of the present disclosure, the polysilicon protrusion (410, 510) is a constituent element of the gate polysilicon structure (110) and is created using the same mask. As a constituent element of the gate polysilicon structure (110), alignment issues required to create polysilicon protrusions (410, 510) and associated body protrusions (412, 512) relative to the gate polysilicon (110) and associated P-body (112) for prior art transistors such as that shown in fig. 3A are eliminated. In view of the prior art embodiment of fig. 3A discussed previously, those skilled in the art will recognize that the docking body joining method described herein provides for the elimination of such an alignment step and a simpler manufacturing process.

As noted in the above paragraphs of the present disclosure, docking body joining according to various embodiments of the present disclosure, such as depicted in fig. 4A-5C, provides the following advantages when compared to the body joining of prior art embodiments (e.g., fig. 2A, 3A): the manufacturing process is simpler, the body-coupled impedance (e.g., resistance) is adjustable, and the parasitic capacitance is reduced. Thus, an integrated circuit using transistor devices with abutting body ties according to the present invention may outperform an integrated circuit with similar functionality using transistor devices without body ties or with body ties according to prior art embodiments. Fig. 10A to 19, which will be described later, show comparative data graphs showing additional performance advantages of the docking body contact (connection) according to the present invention.

As mentioned in the above paragraphs, according to some embodiments of the present disclosure, a butting body link may be provided to the gate polysilicon of a transistor via more than one polysilicon protrusion. Such an embodiment according to the present disclosure is depicted in fig. 6, fig. 6 being an extension of the embodiment depicted in fig. 4A. As shown in fig. 6, a plurality of polysilicon projections (610) branch off from the gate polysilicon structure (110), pass through the source region (120), and extend beyond the source region (120) to a body contact region (440), denoted as a P + region in fig. 6, adjacent to the source region (120) to form a single polysilicon structure. Such different polysilicon projections (610) in turn allow for the creation of respective different body projections that provide a resistive conductive path between the P-body under the polysilicon gate structure (110) and the body contact region (440), and thus to the source region (110). Cross-sectional views along lines a and B of the N-type MOSFET transistor (600) shown in fig. 6 can be taken in fig. 1B and 4B, respectively. In the width W of the transistor_GIn large cases, multiple polysilicon projections (610) may be desired. Although in the exemplary embodiment depicted in fig. 6 in accordance with the present disclosure the different polysilicon projections reach a common continuous body contact region (440), according to an alternative embodiment of the present disclosure such body contact region may comprise one or more different and separate P + regions, each such P + region being adjacent to a source region (120). Those skilled in the art will readily understand how to derive such alternative embodiments based on the exemplary structural layout embodiment depicted in fig. 6. It should be noted that the polysilicon protrusion (610) is along the width of the body region (by W)_GDefined) may be determined according to the desired design goals of the butted body-tied transistor (600) of fig. 6. According to an exemplary embodiment of the present disclosure, as depicted in fig. 6, the polysilicon protrusions (610) are symmetrically arranged along the width of the body region, wherein,the polysilicon projections (610) are symmetrically arranged with respect to a center line (denoted by B in fig. 6) of the width of the body region. According to yet another exemplary embodiment of the present disclosure, as depicted in fig. 6, the polysilicon projections (610) are arranged at equidistant locations along the width of the body region, wherein between any two consecutive polysilicon projections (610) along the width W_GIs constant.

In a manner similar to that provided in the embodiment depicted in fig. 6, the butted body tie embodiment according to the present disclosure depicted in fig. 5A may be expanded to provide more than one polysilicon protrusion (510) branching off from the gate polysilicon structure (110). As shown in fig. 7A, each such polysilicon protrusion (510) may reach a region within the source region (120) that contains a P + region associated with the body contact region (540). As depicted in fig. 7A, such body contact regions (540) may be distinct and separate and in a one-to-one relationship with each polysilicon protrusion (510), according to an exemplary embodiment of the present disclosure. According to other embodiments of the present disclosure, as depicted in fig. 7B, P + regions associated with different body contact regions (540) may be merged into one or more larger P + regions (540) that may each serve as a body contact region for more than one polysilicon protrusion (510).

As previously mentioned, the gate polysilicon (110) may be part of a finger of a larger device, wherein such a device may include a plurality of such fingers. Each such finger may be part of a separate transistor that in combination with other transistors creates a larger device. Larger devices may include multiple transistors connected in series or in parallel or a combination of series and parallel connections. As is known to those skilled in the art, in some cases, adjacent fingers may share the same continuous source region. According to embodiments of the present disclosure, one, more than one, or all of the fingers of a larger device may have a butt-body joining structure according to the structural layout provided in fig. 4A-7B.

Fig. 8A illustrates an embodiment in which two adjacent fingers of a transistor device share a common source region (120) according to the present disclosure. Each finger having a respective associated length L_G1And L_G2In some embodiments, the length L_G1And L_G2May be equal to each other. Each gate polysilicon structure (110) may have a respective polysilicon protrusion (510) branching from the gate polysilicon structure (110) into the common source region (120) and extending to a body contact region (540), which in some exemplary embodiments is a P + region. The exemplary embodiment depicted in fig. 8A, in accordance with the present disclosure, shows one polysilicon protrusion (510) per gate polysilicon structure (110), the polysilicon protrusion (510) merging into the body contact region (540) at the distal end of the polysilicon protrusion (510). Such a limitation should not be construed as limiting the contents of the invention which the inventors of the present application regard as their invention, but is merely an exemplary embodiment of the present invention. As discussed in the above paragraphs and with respect to fig. 4A-7B, many different structural layouts for the docking body contacts according to the present disclosure are possible and within the abilities of one of ordinary skill in the art based on the teachings according to the present disclosure. For example, in one embodiment, the body contact regions (540) may be located at the same distance from the respective gate polysilicon structures (110). In another embodiment, the body contact regions (540) may be located at different distances relative to the respective gate polysilicon structures (110).

A gate polysilicon structure (110) connecting two adjacent fingers may be desired. This is typically performed via extension and bonding of the gate polysilicon structure outside the active area of the device (e.g., a region separate from the drain and source regions of the device). According to an embodiment of the present disclosure, as depicted in fig. 8B, two adjacent gate polysilicon structures may be joined via a common polysilicon protrusion between the two adjacent gate polysilicon structures. In the embodiment depicted in FIG. 8B, there is a channel defined by L_G1And L_G2To representThe two gate polysilicon structures (110) of respective associated gate lengths are connected via a polysilicon protrusion (510) common to both structures (110). This may allow, for example, a gate voltage provided at one gate contact associated with one gate polysilicon structure to be provided to an adjacent gate, and thus allow for a simpler and simplified overall gate polysilicon structure.

The common polysilicon protrusion (510) depicted in fig. 8B in accordance with an exemplary embodiment of the present disclosure may provide a butt body tie to the two transistor devices shown in fig. 8B via its connection with the body contact region (540) while engaging the respective gate polysilicon structure (110) as described above. The mechanism for providing a butted body tie in the embodiment depicted in fig. 8B is similar to that described with reference to fig. 4A-7B, wherein the body protrusion associated with the polysilicon protrusion (510) resistively connects the P-body region underlying the gate polysilicon to the common source region (120) via the body contact region (540), the body contact region (540) providing a (second) low resistivity conductive path to the source region (540) as described above. It should be noted that although the P + region (540) in fig. 8B appears to be centrally located between the two gate polysilicon structures (110), the location of such regions may vary depending on the desired body tie performance requirements of each of the two devices depicted in fig. 8B. Similarly, the width of the segment of the polysilicon protrusion associated with one gate polysilicon structure between the body contact regions (540) may be different from the width of the segment associated with another gate polysilicon structure.

In the exemplary embodiments according to the present disclosure depicted in fig. 8A-8B, there is a corresponding associated gate length L_G1And L_G2May be part of the same device or two separate devices. According to yet another embodiment of the present disclosure, adjacent fingers may correspond to fingers of a split device that are electrically connected, for example, in a cascode configuration. In such a cascode configuration, as depicted in fig. 8C-8K, the source of the first device is electrically connected to the drain of the second (latter) device. Although the exemplary configurations in accordance with the present disclosure represented in fig. 8C-8E and 8I-8J use two cascode transistor devices, the skilled person will understand that stack sizes greater than two, e.g. three, four, five, …, ten or more stacked devices are also possible as depicted in fig. 8F and 8K.

Fig. 8C illustrates a top view of the docking body-tied cascode configuration (800C) schematically represented in fig. 8I in accordance with the present disclosure. It should be noted that the top transistor schematically represented in fig. 8I corresponds to and is by its associated gate length L depicted in fig. 8C_G1The first device identified, and the bottom transistor schematically represented in fig. 8I corresponds to and is passed through its associated gate length L depicted in fig. 8C_G2An identified second device. As can be seen in FIG. 8C, the gate length L is correlated_G1A source region (120) of the first device is represented with an associated gate length L_G2The drain region (130) of the second device is shown as being common, thereby electrically connecting such source and drain regions.

As shown in fig. 8C, a butted body bond to a second device may be provided by such polysilicon protrusion (510): the polysilicon protrusion (510) is connected to (via L)_G2Identified) and extending over the source region (120) of the second device to a body contact region (540) (e.g., P + doped) formed within the source region (120) of the second device. As described in connection with fig. 4A-7B, such polysilicon ledges (510) may be used to create respective body ledges under the polysilicon ledges (510) that may provide an adjustable resistive conductive path between the body region of the second device and the body contact region (540). Since there is no body link, it is not (via L)_G1Identified) the first transistor is a three terminal transistor (top transistor in the figure) as shown in fig. 8I.

According to another exemplary embodiment of the present disclosure depicted in fig. 8D, the same may be provided to (by) the structure depicted in fig. 8D via such two polysilicon protrusions (510)L_G2Identified) a docking body attachment of a second device: the two polysilicon projections (510) are connected to the gate polysilicon structure (110) of the second device and extend over and beyond the source region (120) of the second device to a body contact region (440) (e.g., P + doped) adjacent to the source region (120) of the second device. Thus, as described above, such polysilicon projections (510) may provide respective body projections to resistively connect the body region of the second device to the body contact region (440). A schematic representation of the docked body-tied cascode configuration of fig. 8D is also provided by fig. 8I, where (via L)_G1Identified) the first transistor is a three terminal transistor (top transistor in the figure) as shown in fig. 8I.

According to some embodiments of the present disclosure, as represented in fig. 8E, fig. 8C-8D may also be followed (by L)_G1Identified) first device provides one or more docking body joints. As shown in fig. 8E, a butt-body bond to the first device may be provided via such a first polysilicon protrusion (510): the first polysilicon plug (510) is connected to (via L)_G1Identified) of the first device and extending over the common drain/source region (130/120) of the two cascode devices to a body contact region (540) (e.g., P + doped) formed within the common drain/source region (130/120). As described in connection with fig. 4A-7B, such polysilicon protrusions (510) may be used to create respective body protrusions under the polysilicon protrusions (510) that may provide an adjustable resistive conductive path between a body region of the first device and a body contact region (540). A schematic representation of the docked body-tied cascode configuration of FIG. 8E is represented by FIG. 8J, where (by L)_G1And L_G2Identified) are four-terminal transistors each having a butted body junction.

Those skilled in the art will appreciate that various combinations of the structures described with respect to fig. 4A-7B for providing a butt-body join to any of the first and second devices of the cascode configuration (or more devices for larger stack sizes) in accordance with the present disclosure discussed above are possible. For example, a first device may be provided with a docking body joint according to any of the structures represented in fig. 4A-5A and 7A-7B, and a second (latter) device may be provided with a docking body joint according to any of the structures represented in fig. 4A-7B, independently of the docking body joint provided to the first device.

Fig. 8F and 8K represent extensions of the exemplary embodiment depicted in fig. 8C and 8E according to the present disclosure, wherein the cascode configuration comprises n transistor devices electrically connected in series, the source (120) and drain (130) of two adjacent devices being merged as is the case for the embodiment depicted in fig. 8C. It should be noted that in the cascode configuration according to the present disclosure and represented in fig. 8C-8K, only the last device (e.g., the second device of fig. 8C, and the nth device of fig. 8F) may be provided with a butted body tie according to the structure represented in fig. 6.

According to yet another embodiment of the present disclosure, the desired performance of a stack (e.g., fig. 8C-8K) may be optimized by providing different or the same body attachment structures to different devices of the stack, thereby providing different or the same value of resistance between the body and the contact for each of the devices of the stack. Fig. 10A to 19 described later show individual device performance in relation to the body bonding structure.

According to some embodiments, not all devices of the stack are provided with a butt-body structure, and thus, for example, as depicted in fig. 8C-8D and 8I-8J, the stack may include a combination of three-terminal and four-terminal devices. Fig. 8G and 8H are further such exemplary embodiments, where some (four-terminal) devices of the stack are provided with docking body coupling structures according to the present teachings, and other (three-terminal) devices are not provided with docking body couplings. According to the exemplary cascode configuration depicted in fig. 8G, only the last one (via L)_GnIdentified) device is provided with a butt-body joint according to the present teachings, and according to the exemplary cascode configuration depicted in fig. 8H, only (by L)_G2Identified) second device and (by L)_GnIdentified) last device is provided with a docking body joint according to the present teachings. It is to be understood that such exemplary embodiments should not be considered as limiting the scope of the invention, as variations of such embodiments having stacked devices joined by abutting bodies according to the present disclosure are well within the ability of those skilled in the art in view of the present teachings.

The above embodiments of the present disclosure in accordance with the butted body joint describe the electrical connection of the body (channel) region of the transistor device to the respective source region and thus to the potential present at the source terminal of the device. According to yet another embodiment of the present disclosure, a butt-body-tie connection decoupled from the potential at the respective source terminal may be provided. Such embodiments allow the opposing body tie to be coupled to a potential independent of the potential at the source terminal of the respective device. Corresponding structures are depicted in fig. 9A and 9B, and corresponding schematic representations are depicted in fig. 9D.

Fig. 9A depicts a top view of a butted body-tied device (900A) that may be used to resistively tie the body region of the device to any potential, in accordance with an embodiment of the disclosure. The transistor device (900A), e.g., a thin film SOI device, comprises a similar structure for providing a butted body tie as described with respect to fig. 5A, with the difference that the body contact region (540) is now isolated from the source region (120) via an isolated P-region created under the polysilicon structure (910) connected to the polysilicon protrusion (510). Similar to the polysilicon protrusion (510), the polysilicon structure (910) may allow for the creation of a corresponding isolated P-region (912) underneath the polysilicon structure (910), the isolated P-region (912) abutting the body protrusion created via the polysilicon protrusion (510) and thus being electrically connected to the body region underneath the gate polysilicon structure (110). The isolation P-region (912) surrounds the body contact region (540) within the source region (120) to not provide any contact between the regions (540) and (120) as depicted by the cross-sectional view in fig. 9B. Note that like reference numbers (numerals) in the figures represent like items and thus may be further described with respect to other figures of the present disclosure.

Fig. 9B shows a cross-sectional view of the docking body coupling device (900A) of fig. 9A along line F. As can be seen in fig. 9B, the source region (120) is isolated from the body contact region (540) via an isolation P-region (912) associated with the polysilicon structure (910) and the BOX layer (150), the BOX layer (150) providing a common basis for all active areas of the device, including the regions (120, 912, 540) shown in the cross-sectional view of fig. 9B.

Those skilled in the art will appreciate that, due to the isolation from the source region (120), the body contact region (540) may be coupled to any desired potential during operation of the inventive butted body tie device (900A) while providing a conductive path of tunable resistivity to the body region of the device. Such coupling of the isolated body contact region (540) to a desired potential may be provided, for example, via a metal contact connected atop the region (540).

According to yet another embodiment of the present invention, as depicted in fig. 9C, the teachings related to fig. 9A and 9B may be extended to adjacent fingers, where through (L)_G1、L_G2) The identified fingers sharing the common source region (120) may provide an isolated abutting body link within the common source region (120) to allow body contact with any desired potential. Those skilled in the art will appreciate that the body contact region (540) may be provided in any active region of the device (900C) other than the body region, including in the drain region (130), due to its isolation relative to adjacent regions.

It should be noted that any configuration of interfacing with the docking body of the source in accordance with the present disclosure and depicted in the previously described figures (e.g., fig. 4A-8H) may be provided with an equivalent isolated docking body coupling as illustrated in fig. 9A-9D. Thus, the stacked transistor structure depicted in fig. 8C-8K may also be provided with isolated body tie structures as desired. Those skilled in the art can further extend the teachings in accordance with the present disclosure to configurations that include isolated butt-body ties to the source and combinations of butt-body ties.

Where the transistor is in a non-conductive state (as opposed to a conductive state), the butted body joint according to the various embodiments represented above may provide a lower resistance (the first resistance described above) between the transistor channel and the body contact region (e.g., region (440, 540)). When the gate voltage Vg of a transistor with a butted body tie according to various embodiments of the present disclosure is close to or below the voltage of the transistor body (threshold voltage Vt), placing the transistor in an off/non-conductive state, the doping in the body overhang provides a resistive conductive path from the body contact region to the transistor body region under the gate polysilicon. The body protrusion conducts electricity from the surface of the silicon through the entire depth of the silicon. When the gate voltage Vg of such a transistor is close to or higher than the transistor threshold voltage Vt, thereby placing the transistor in an on/conductive state, there is a region depleted of mobile charge in the body protrusion. The region begins at the top surface of the active silicon layer and extends into the silicon. The depletion region becomes non-conductive and therefore reduces the cross-section of the conductive silicon in the body protrusion (thereby increasing the resistivity). Thus, a butted body bond according to various embodiments of the present disclosure may provide a higher resistance between the transistor channel and the body bond (disposed at the body contact region) when the transistor is in a conductive state (Vg > Vt) than when the transistor is not conductive. This higher resistance allows for reduced loss of RF characteristics performance of the transistor due to the provision of body ties. Those skilled in the art are well aware of the loss in RF characteristic performance of transistors associated with providing body tie to transistors, and thus may recognize the benefits of interfacing body tie in accordance with the present disclosure.

Fig. 10A shows a graph of the (effective) butted body coupling resistance Reff, the gate bias voltage Vg, and the body protrusion width (in μm). As can be seen from the graph of fig. 10A, for a given body protrusion width (width along the gate width), the body link resistance increases in accordance with the gate bias voltage Vg. Specifically, the effective body coupling resistance is 1M Ω for the case where the gate bias voltage Vg is-0.3V (the transistor is not conducting), and is greater than 1000M Ω for the case where the gate bias voltage Vg is 1V (the transistor is conducting). Furthermore, as can be seen from the graph of fig. 10A, for a given gate bias voltage Vg, the effective resistance decreases as the width of the body protrusion increases.

Transistors with butted body ties according to various embodiments of the present disclosure may exhibit performance advantages over transistors without body ties (floating bodies) or transistors with conventional (H-gate, T-gate) body ties. Such performance advantages include, but are not limited to, improved control of majority carriers and potential in the body region of the transistor without the drawbacks of conventional (H-gate, T-gate) body-tied transistors.

In contrast to floating body transistors, the butted body tie according to the present invention provides: higher breakdown voltage, lower drain-source current (Ids) in the off-state (non-conductive state) at elevated drain-source voltage (Vds), less reduction in output impedance with increased Vds in the on-state (conductive state), and improved HCI (hot carrier injection) performance for RF applications.

In contrast to conventional (H-gate, T-gate) body-tied transistors, the butt-body-tie according to the present invention provides: less total gate parasitic capacitance (sum of all capacitances attached to the gate), less drain-gate capacitance (not increased compared to floating body transistors), higher f (due to reduced drain-gate capacitance)_maxAnd no limitation on channel width to preserve body-tied device characteristics. Furthermore, the present butted body tie invention provides a simpler manufacturing process, lower manufacturing cost, and higher process yield than the prior art source body tie structure shown in fig. 3A.

The above characteristic benefits of the docking body coupling according to the present invention enable higher peak Power Added Efficiency (PAE) for RF power amplifier applications, in addition to all other applications that benefit from improved output impedance and breakdown voltage.

FIG. 10B shows the programming of two floating body transistors: (T_1A、T_1B) And two transistors (T) coupled with a butted body according to various embodiments of the present disclosure_2A、T_2B) Is in an off state (for example, the gate-source voltage Vgs is 0), is compared with the drain-source current (Ids). Transistor T_1AAnd transistor T_2AThe same (e.g., the same gate length), and transistors T_1BAnd transistor T_2BThe same (e.g., the same gate length). The diagram of fig. 10B clearly shows: for transistors with butted body connections (T)_2A、T_2B) In the case of (2), the off-state current Ids (leakage current) is low at the rising value of the drain-source voltage Vds. Further, based on the diagram of fig. 10B, it is also clear that for the transistor (T) having the butted body connection_2A、T_2B) The effective breakdown voltage (voltage Vds when the current Ids reaches a certain level) is higher because at all points of the curve, (T)_2A、T_2B) Is less than (T)_1A、T_1B) Ids current of (1).

Fig. 11A and 11B show plots of Ids versus Vds for the same transistor device with and without a butted body tie, respectively, where the gate-source voltage Vgs changes (varies) in steps of 25 mV. As can be seen from these figures, the transistor with the butted body tie exhibits a smooth Ids versus Vds curve regardless of Vgs voltage, and does not exhibit the well-known warpage (kink) characteristic of a floating body transistor as seen in fig. 11B. The location of the warpage seen in fig. 11B depends on the Vgs voltage applied to the floating body transistor. As known to those skilled in the art, such warping represents a sudden drop in the output impedance (Vds/Ids) of the transistor and is undesirable in many RF applications as well as low frequency analog applications. As can be seen in fig. 11B, the warpage occurs at a Vds voltage of 0.6V to 0.8V depending on the applied Vgs voltage.

Fig. 12A-12C show graphs representing the effect of the number of body protrusions of a butted body-tied transistor according to the present invention on the Ids versus Vds response of the same transistor device (e.g., same channel length and channel width). The butted body joint device in fig. 12A (which isShown) has one polysilicon protrusion (branching off from the corresponding gate polysilicon structure), the butted body tie device in fig. 12B has 4 polysilicon protrusions, and the butted body tie device in fig. 12C has 7 polysilicon protrusions, each connected to a corresponding body contact region. As can be seen from the graphs of fig. 12A to 12C, by increasing the number of polysilicon protrusions of the butt-body-tied device, the output conductance and the breakdown voltage are improved. Fig. 12D shows a graph representing a fixed gate width W for a fixed gate bias voltage Vg of 0.6V_GOutput conductance g of the butt-joint body connection device of (1)_dsAnd the number of body projections.

Fig. 13 and 14 show graphs representing the effect of abutting body junctions with respect to hot carrier injection on the same transistor device with body junctions during the lifetime of the transistor when used in RF applications. This is measured by monitoring the change in bias current at a fixed bias input voltage for the same transistor with and without a butt-body tie, operating as an amplifier output transistor under RF power stress. Fig. 13 shows a graph representing the reduction of bias current over time due to hot carrier injection for the case of a transistor without a body tie (floating transistor). As can be seen from the graph of fig. 13, hot carrier injection causes the bias current to drift gradually and decrease over time. This in turn may lead to undesirable performance of RF amplifiers using such transistor devices. In contrast, the graph of fig. 14 shows that the same transistor with body tie (same transistor) does not exhibit a change in bias current over time when operated under the same conditions. The results show that the inventive butted body junction provides an effective exit for minority carrier charges generated in the transistor channel over time due to hot carrier injection phenomena. Those skilled in the art will appreciate the superior performance of a butted body bond in accordance with the present disclosure as represented by fig. 14, and will appreciate the importance of such curves to the reliability and design capability of butted body bond transistors.

FIG. 15A shows a graph representing Vg for a gate bias voltage0.5 v and transistor width W_GA plot of the measured normalized total gate capacitance Cgg for the butted body-tied transistor (T2) versus the same transistor (T1) without the body tie (floating body), 10 μm. Fig. 15B shows a graph representing the measurement normalization Cdg for the same transistor/condition as the graph of fig. 15A. As can be seen from the figures or fig. 15A and 15C, with the addition of the body tie, the total capacitance increases only slightly, and the measurement Cdg is actually lower.

16A-16B illustrate f representing a butted body-tied pair transistor according to the present disclosure_TFrequency sum f_maxA comparison of the effect of frequency. FIG. 16A shows f for a floating body transistor_TData graphs (top graph) and f for three different configurations of butted body tie transistors_TThe data plot, floating body transistor and butted body tie transistor are otherwise identical (e.g., same channel length and width). As can be seen from the graph of FIG. 16A, f is observed_TA slight decrease in frequency. This may be due to the increased C obtained by the docking body joining configuration as seen in fig. 15D_GSAnd (4) a capacitor. FIG. 16B shows f corresponding to the same transistors/conditions as in the case of the data diagram of FIG. 16A_maxAnd (6) data graphs. As can be seen from the data diagram of fig. 16B, f_maxFollowing f visible in the graph of FIG. 16A_TReduced without further degradation.

Fig. 17 shows a comparison graph representing the effect of a docking body connection according to the present invention on RF power amplifier applications. As known to those skilled in the art, one figure of merit for an RF power amplifier is peak Power Added Efficiency (PAE) at a given level of Adjacent Channel Power Ratio (ACPR), also known as ACLR (adjacent channel leakage ratio). The linearity and frequency requirements in RF applications do not allow the use of conventional T-gate transistors or H-gate transistors. However, the butt-body joint configuration according to the present invention can be used, since it does not increase the drain-gate capacitance C as can be seen from the previous figures_DGAnd also adds less total gate capacitance C_GG. Thus, as can be seen from the graph of fig. 17, the ACLR in transistors with butted body connections achieves compression (c) due to the transistorsompression) until it increases, the ACLR is low enough. A typical curve for ACLR is shown in fig. 17 for the same floating body device and abutting body bonded device. Note that both transistors have ACLR less than-40 dBc until rapidly increasing due to compression. Both the floating body configuration and the butted body tie configuration provide an ACLR (dB relative to the corresponding RF carrier) of less than-40 dBc for a wide range of device sizes and bias conditions.

The higher bias voltage may allow the transistor to operate at a higher output power Pout until the transistor reaches compression, so the higher breakdown voltage provided by the butted body tied transistors may enable operation of the transistor at a higher bias voltage and hence a higher Pout. Fig. 18 shows a data plot representing the gain versus Pout of the same floating body transistor and butted body-tied transistors at the same bias at a relatively high voltage bias. As can be seen from the data plot of fig. 18, the butt-body joint device can be operated at higher power before going into compression, which is represented by a reduction in gain (droop).

As is well known to those skilled in the art, a lower bias current (Ibias) reduces the power lost in the transistor, which is wasted power and thus reduces the efficiency of the transistor. When operating at high bias voltages and high RF power, the voltage of the body region of the transistor may increase due to the generated carriers. For a floating body device, the bulk potential increases as shown by the warpage in fig. 11B discussed above. In the case of the butt-body-tied device according to the invention, these generated carriers are removed via the provided body protrusion conducting channel. For RF applications, the bias current may increase with increasing power due to an increase in the body potential of the floating body transistor, particularly for operating conditions that cause transient operation in the region shown to be affected by the increased body potential (warpage), while for the butted body-tied transistors the bias current still performs well. This is shown in fig. 19.

Exemplary and non-limiting applications of transistor devices joined using a butted body according to various embodiments of the present disclosure may include: general purpose analog circuits with body tie, Power Amplifiers (PAs), Low Noise Amplifiers (LNAs), analog-to-digital converters (ADCs), Voltage Controlled Oscillators (VCOs), and voltage reference circuits with frequency ranges from DC to 100GHz and higher.

With the teachings according to the present disclosure, the gate length can be further optimized (the gate length can be made shorter). For example, as can be seen from the previously described fig. 10B, a greater breakdown voltage can be obtained with a body-tied transistor according to the present disclosure as compared to a floating body transistor. Thus, the butted body-tied transistor (T) of FIG. 10B_2,A、T_2,B) And floating body transistor (T)_1,A、T_1,B) Than can be at a higher V_DSOperate safely at voltage because of the higher V_DSHigher I associated with floating body transistors at voltage_DSCurrent may break down the transistor. As known to the skilled person, the transistor (T) may be controlled by varying the gate length of the transistor_1,A、T_1,B) Wherein a larger gate length may allow a higher breakdown voltage of the transistor and thus a higher operating voltage V_DS. In other words, a floating body transistor (T)_1,A、T_1,B) Via a transistor (T) connected to the body via the butt joint_2,A、T_2,B) Compared to a larger gate length. Furthermore, the requirement of an overlap region between region (110) and region (340) may dictate a larger gate length than the prior art body tie depicted in fig. 3A.

As discussed above with respect to fig. 8C-8F, the abutting body tie of the present invention may be provided to a cascode configuration including a plurality of stacked transistors. FIG. 20A schematically shows two stacked transistors (T)_A、T_B) Fig. 20B schematically shows three stacked transistors (T)_C、T_D、T_E) In a cascode configuration (2000B). As discussed above, to the transistor (e.g., T)_B、T_D、T_E) May be connected by a body-tied interface disposed in a source region of the transistorIs provided, the source region being common to the drain regions of adjacent transistors of the cascode configuration. Throughout this document, T is used_ATo T_ETo represent transistors in circuit arrangements as shown, for example, in fig. 20A and 20B, respectively. This is shown in fig. 21A, fig. 21A depicting the transistor T to fig. 20A_BAccording to the present disclosure.

As shown in fig. 21A, is connected to the transistor T_BThe polysilicon protrusion (510B) of the gate polysilicon structure (110B) is in the transistor (T)_B、T_A) Extends over the common source/drain region (120B/130A) to a body contact region (540B) (e.g., P + doped) formed within the common source/drain region (120B/130A). In some cases, the transistor (T) is due to a desired physical size of the polysilicon protrusion (510B) and a desired physical size of the body contact region (540B)_A、T_B) The spacing between the respective gate polysilicon structures (110A, 110B) may be large, and thus the spacing of the respective body regions defined by such gate polysilicon structures may be large. This is illustrated in fig. 21A, where a common source/drain region is created with the transistor T_BAnd a transistor T and a drain region (130B) of the transistor_ATo provide spacing for interfacing body ties (510B, 540B) as compared to a wider common region. Such a wider area results in two transistors (T)_A、T_B) Larger spacing between the gate polysilicon structures (110A, 110B), which may therefore result in an overall increase in the overall physical size of the cascode configuration (2000A) of fig. 20A. According to embodiments of the present disclosure, the overall physical size of the cascode configuration (2000A) may be reduced while providing a docking body junction (e.g., the desired physical size of the structures (510B, 540B)) having the same desired physical size discussed above. It should be noted that in fig. 21A and subsequent figures, the various structures for implementing various docking body coupling configurations in accordance with the present disclosure are represented by corresponding top view structures, wherein such may be readily understood by one skilled in the art in view of the above discussion relating to fig. 1-9DCorresponding alternative views of various structures.

According to an embodiment of the present disclosure, as shown in fig. 21B, the transistor T may be formed by a bottom transistor T_ATo create a break-away region in a gate polysilicon structure (110A) to reduce the gate to top transistor T_BThe overall physical size of the butted body tied cascode configuration (2000A). In the butted body tie (2100B) of fig. 21B, the presence of the break region allows the polysilicon protrusion (510B) to extend through the break region, over the area that would normally contain the gate polysilicon structure (110A), and thus, allows for a smaller spacing between the two gate polysilicon structures (110A) and (110B) while maintaining the desired physical dimensions of the polysilicon protrusion (510B) and contact region (540B). Specifically, in order to isolate the source region (120A) from the common source/drain region (120B/130A), an isolation region (2090) is formed around the open region, the isolation region (2090) extending to the transistor (T)_B、T_A) And extends into the transistor T in the common source/drain region (120B/130A)_AIn the source region (120A). According to yet another embodiment of the present disclosure depicted in fig. 21D, the isolation region (2090) extends completely through the source region (120A) to reach the boundary (2090) of such region and thus divides the source region (120A) into two distinct (separate left and right) source regions (120A), wherein each source region is isolated from a common source/drain region (120B/130A). The isolation region (2090) of fig. 21B, 21D may be formed by removing (e.g., etching, oxidizing, etc.) silicon from the region, thereby forming a non-conductive region.

With further reference to the abutting body ties (2100B, 2100D) of fig. 21B, 21D, the breaking of the gate polysilicon structure (110A) provides a spacing for the polysilicon protrusion (510B) to extend beyond a distance corresponding to the spacing between the gate polysilicon structures (110A) and (110B), and the breaking of the source region (120A) formed by the isolation region (2090) provides a conductive channel for the body protrusion defined by the polysilicon protrusion (510B) that extends over the silicon region normally belonging to the source region (120A). Additionally, as depicted in fig. 21B, 21D, the body contact region (540B) is at the abutment spacerIs formed in a region away from the region (2090) to the transistor T_B(through 110)_B、120_B、130_BDefine) provides a docking body joint (2100B) according to the present teachings. The body contact region (540B) contacts the body protrusion (510B) at a distal end of the body protrusion, defined by the polysilicon protrusion, which distal end is distal from the transistor T_BA body region of the gate defined by the gate polysilicon structure (110B). The silicon region and polysilicon (gate and body protrusion) depicted in fig. 21B according to an embodiment of the present disclosure are shaped such that a transistor T is formed_AAnd a transistor T and a drain (130A) of_BAnd the transistor T and the silicon region of the source (120B)_AIs separated from the source (120A) but directed to the transistor T_BAnd into which the transistor T is inserted_BThe region of the body protrusion extending into the body contact region (540B) provides a continuous silicon region.

Fig. 21C, 21E illustrate an exemplary method of creating a (P + doped) body contact region (540B) using a target (2120) for implanting P-type dopants according to the present disclosure. Creating polysilicon protrusions (510B) and isolation regions without silicon for the implanted barrier of dopants means that only the common region between region 120B/130A and target (2120) is doped, creating the body contact region (540B) depicted in fig. 21B. Any other method known to those skilled in the art may be used to create the body contact region (540B) in accordance with the present teachings.

FIG. 22 shows transistor T for a cascode configuration (2000A)_AAnd T_BA butted body tie implementation (2200) according to yet another embodiment of the present disclosure, each including more than one finger (e.g., two fingers, such as defined by respective gate polysilicon structures (110A, 110B) of fig. 22). Those skilled in the art will appreciate that the docking body tie configuration (2200) depicted in fig. 22 in accordance with the present disclosure is for a transistor (T)_A、T_B) According to the teaching of the embodiment (2100B, 2100D) represented in fig. 21B, 21D, each of the cases having more than one finger. FIG. 22 shows a crystalBody tube T_ACentral line C of source electrode (120A)_LTwo transistors (T) of mirrored cascode configuration (2000A)_A、T_B) The source (120A) acting as a common source for both fingers of the transistor. As can be seen from FIG. 22, the transistor T_AHaving a central axis C_LTwo fingers that are mirror images (each finger being identified by a separate discontinuous region (110A), wherein each separate discontinuous region (110A) is broken at a region defined by an isolation region (2090)), each finger having a centerline C about the stack_LMirror image similar area (110A, 120A, 130A), center line C_LThrough the center of the region (120A). Further away from the center line C_LAnd the transistors T are arranged mirrored about the centre line_BEach finger has a similar region (110B, 120B, 130B), wherein the region (120B) is associated with the transistor T_AIs common to the regions (130A). Transistor T_BTerminates at the region marked by line (2095) (130E).

According to the embodiment (2200) depicted in fig. 22, the transistor T may be implemented by a transistor T at the bottom_ACreates a break area in the gate polysilicon structure (110A) of each finger to reduce the gate polysilicon structure having a top transistor T_BThe overall physical dimensions of the butted body tied cascode configuration (2000A), as shown in fig. 22. The off-region allows the transistor T_BExtends through the open area, past the area generally containing the transistor T_AAnd thus the off-region remains for the gate polysilicon structure (110A) of the adjacent finger T_BWhile providing the desired physical dimensions of the polysilicon protrusion (510B) and contact region (540B) joining the body, allows for a smaller spacing between the two gate polysilicon structures (110A) and (110B) of adjacent fingers. Thus, as depicted in FIG. 22, the top transistor T_BEach finger (defined by a gate polysilicon structure (110B)) is provided with a butt-body joint defined by a structure (510B, 540B), which structure (510B, 540B) is provided with a butt-body joint, in accordance with an embodiment of the present disclosureB) May surround a centerline C of the structure (2200)_LAre symmetrically arranged. It should be noted that fig. 22 only shows the top transistor T to the cascode configuration (2000A)_BThe finger of (a) is joined to the body. As can be seen, for example, in fig. 25-29B, the butted body ties to the fingers of the transistors of the cascode stack, except for the top transistor.

With further reference to the butted body tie (2200) of fig. 22, to connect the cascode configured bottom transistor T (schematically represented by fig. 20A)_AIs isolated from each common source/drain region (120B/130A) by a source region (120A) of each finger (110A) (common to both fingers), an isolation region (2090) being formed around the two open regions, the isolation region (2090) isolating the transistor T_AThe source region (120A) common to both fingers (110A) is split into two distinct (separate) source regions (120A), each source region being isolated from both common source/drain regions (120B/130A). The isolation region (2090) may be formed by removing (e.g., etching, oxidizing, etc.) silicon from the region, thereby forming a non-conductive region.

With continued reference to fig. 22, the breaking of the gate polysilicon structure (110A) provides a spacing for the polysilicon protrusion (510B) to extend beyond a distance corresponding to the spacing between adjacent gate polysilicon structures (110A) and (110B), and the breaking of the source region (120A) formed by the isolation region (2090) provides a conductive channel for a body protrusion defined by the polysilicon protrusion (510B) that extends over a silicon region that is generally part of the source region (120A). Additionally, a body contact region (540B) is formed in a region abutting the isolation region (2090) to face the transistor T_BProvides a docking body joint according to the present teachings. The body contact region (540B) contacts the body protrusion at a distal end of the body protrusion defined by the two polysilicon protrusions (510B), the distal end being distal from the transistor T_BA body region of the gate defined by the gate polysilicon structure (110B).

As can be seen from the configuration (2200) of fig. 22, the silicon region and the silicon oxide layer depicted in fig. 22 according to an embodiment of the present disclosureThe polysilicon structure (gate and body protrusion) is shaped so as to be specific to the transistor T_AEach finger of (1) and transistor T_BTo form a transistor T_AThe drain (130A) of the finger and the transistor T_BAdjacent finger source (120B) and transistor T_ASource (120A) (for T)_ACommon to both fingers) but simultaneously to the transistor T_BThe body projection of the finger and the region where the body projection extends into the body contact region (540B) provide a continuous silicon region.

The abutting body tie (2100B, 2200) according to the present teachings as depicted in fig. 21B and 22 may be extended to cascode configurations with more than two, e.g., three, four, and more stacks, wherein the disconnection of the gate polysilicon structure coupled with the isolation region (2090) as discussed above may be used to provide the abutting body tie to the cascode stacked transistors/fingers.

FIG. 23 shows a schematic diagram for the three transistors (T) depicted in FIG. 20B_C、T_D、T_E) A butted body tie implementation (2300) of a cascode configuration (2000B) according to yet another embodiment of the present disclosure, wherein each transistor has at least two fingers. FIG. 23 shows a diagram for a (bottom) transistor T_CCentral line C of source electrode (120C)_LThree transistors (T) of mirrored cascode configuration (2000B)_C、T_D、T_E) The source (120C) is a transistor T_CThe common source region (120C) is interrupted at a central region of the source (120C) by an isolation region (2090). As can be seen from FIG. 23, transistor T_CHaving a central axis C_LTwo fingers that are mirror images (each finger being identified by a separate discontinuous region (110C), wherein each separate discontinuous region (110C) is broken at a region defined by an isolation region (2090)), each finger having a centerline C about the stack_LSimilar regions (110C, 120C, 130C) that are mirror images (the center line passes through the center of region (120C) along the width of the region). Further away fromCore line C_LAnd about the centre line C_LMirrored is a (middle) transistor T_DEach identified by a separate discontinuous region (110D), wherein each separate discontinuous region (110D) is disconnected at a region defined by an isolation region (2090), is arranged at the (bottom) transistor T_CAnd (top) transistor T_EEach finger has a similar region (110D, 120D, 130D), wherein the region (120D) is associated with the transistor T_CIs common to the regions (130C). Additionally, at a distance C from the center line_LAnd mirrored about the centerline is the same as the transistor T_DFinger-adjacent (top) transistor T_EEach finger being identified by a separate continuous region (110E), each finger having a similar region (110E, 120E, 130E), wherein the region (120E) is associated with the transistor T_DIs common and the region (130E) terminates at the region marked by the line (2095).

According to the butted body joint implementation (2300) depicted in fig. 23, the junction may be formed by joining a transistor T to a substrate_CAnd T_DCreates a break area in the gate polysilicon structure (110C, 110D) of each finger to reduce the gate polysilicon structure having a top transistor T_EThe overall physical dimensions of the butted body tied cascode configuration (2000B), as shown in fig. 23. Transistor T_DThe off-region in the finger of (1) allows the transistor T_EThe polysilicon protrusion (510E) of the finger(s) extends through the open area, past the area generally containing the transistor T_DOf the gate polysilicon structure (110D) of the adjacent finger. The off region is maintained for the transistor T_EWhile providing the desired physical dimensions of the polysilicon protrusion (510E) and contact region (540E) joining the body, allows for a smaller spacing between the two gate polysilicon structures (110E) and (110D) of adjacent fingers. As can be seen in fig. 23, the break regions in the polysilicon gate structures (110D) and (110C) are located at substantially the same position along the width of the fingers and have substantially the same dimensions along the width.

With further reference to FIG. 23A bottom transistor T_COf each finger (110C) of_CThe common source/drain region (120C) of the two fingers is isolated from each common source/drain region (120E/130D) and (120D, 130C), and an isolation region (2090) is formed in the region surrounding the (four) disconnection regions, thereby disconnecting the source region (120C) from the common source/drain region (120D/130C). This can be seen in fig. 23, where the isolation region (2090) breaks each common source/drain region (120D/130C) and common source region (120C) into two different (and isolated) regions (one on each side of the isolation region (2090)), each different region being isolated from all other source and/or drain regions of other fingers in the stack. Although not shown in fig. 23, those skilled in the art will recognize that electrical continuity between regions that are disconnected by the isolation region (2090) may be provided by breaking contacts in the regions (e.g., as exemplified by contacts 154, 155 in fig. 6) and metal layers used to jumper such contacts, if desired. Furthermore, it should be noted that there is no need to provide electrical continuity across a disconnected region, e.g., disconnected common source/drain region (120D/130C) (see the cascode configuration of fig. 20B), that is not connected to an external signal, as the disconnected region cannot prevent the flow of current across the length of the respective fingers.

With continued reference to fig. 23, the breaking of the gate polysilicon structure (110D) provides a spacing for the polysilicon protrusion (510E) to extend beyond a distance corresponding to the spacing between adjacent gate polysilicon structures (110E) and (110D), and the breaking of the common source/drain region (120D/130C) and the breaking of the common source region (120C) formed by the isolation region (2090) to pass through the transistor T_EA body protrusion is defined by each polysilicon protrusion (510E) associated with each finger of the array, wherein the body protrusion extends over a silicon region that is generally part of a common source/drain region (120D/130C). Finally, a body contact region (540E) isolated from the regions (120D/130C) and (120C) is formed in the region abutting the isolation region (2090) to face the transistor T_EProvides a docking body joint according to the present teachings. Body contact regionThe domain (540E) is in contact with the body protrusion at a distal end of the body protrusion defined by the two polysilicon protrusions (510E), the distal end being distal from the transistor T_EA body region of the gate defined by a gate polysilicon structure (110E).

As can be seen from the abutting body joint configuration (2300) of fig. 23, the silicon regions and polysilicon structures (gate and body protrusions) according to embodiments of the present disclosure depicted in fig. 23 are shaped so as to be for transistor T_C、T_DAnd T_EOn the center line C of the arrangement (2300)_LThe fingers of the same side of the substrate forming a transistor T_DAnd a drain region (130D) of the finger and a transistor T_EThe source region (120E) of the finger, forming a transistor T_CAnd a drain region (130C) of the finger and a transistor T_DAnd forming a transistor T_COf (T)_CCommon to both fingers) of the source region (120C) are separated from each other but simultaneously towards the transistor T_EThe body protrusion (defined by the polysilicon protrusion (510E)) of the fingers and the region in which the body protrusion extends into the body contact region (540E) provide a continuous silicon region.

With further reference to fig. 23, because the disconnection of the gate polysilicon structure (110C) creates an isolated gate body region, a vertical polysilicon structure (2320) may be used to join adjacent gate polysilicon structures on each side of the disconnection and within the isolation region (2090). According to some embodiments of the present disclosure, such vertical polysilicon structures (2320) may be made wide enough to mate with contacts to a metal layer (not shown in the figures) used to restore continuity of the disconnected gate polysilicon structure (e.g., via a jumper of the contacts) and thereby restore transistor T_CA continuous gate channel. Various methods and structures for creating such contacts to metal layers are apparent to those skilled in the art.

FIG. 24 shows a schematic diagram for the three transistors (T) depicted in FIG. 20B_C、T_D、T_E) Top transistor T in cascode configuration (2000B)_EAccording to yet another embodiment of the present disclosure, a docking body coupling implementation (2400). FIG. 24 shows a diagram for a (top) transistor T_ECentral line C of drain region (130E)_LThree transistors (T) of mirrored cascode configuration (2000B)_C、T_D、T_E) The drain region (130E) is a transistor T_EA common drain region of the two fingers. As can be seen from FIG. 24, the transistor T_EHaving two fingers, each identified by a respective zone (110E), each having a center line C_LSimilar regions (110E, 120E, 130E) that are mirror images (the center line passes through the center of region (130E) along the width of the region). Further away from the center line C_LAnd about the centre line C_LMirrored is a (middle) transistor T_DArranged on (bottom) transistor T_CAnd (top) transistor T_EEach finger has a similar region (110D, 120D, 130D), wherein the region (130D) is in contact with the transistor T_EIs common to the regions (120E). Finally, at a distance C from the center line_LAnd mirrored about the centre line is the (bottom) transistor T_CAnd transistor T_DEach finger has a similar area (110C, 120C, 130C), wherein the area (130C) is associated with the transistor T_DIs common and the region (120C) terminates at the region marked by the line (2095). It should be noted that fig. 24 only shows the top transistor T to the cascode configuration (2000B)_EThe finger of (a) is joined to the body. As can be seen, for example, in fig. 21A-21E, 22, and 25-29B described above, the butted body ties to the fingers of the transistors of the cascode configuration, except for the top transistor.

The butted body joint (2400) according to the present disclosure depicted in fig. 24 is a transistor T_EThe body regions of the fingers provide a common contact region (2450) (e.g., P + doping). As can be seen in fig. 24, the two gate polysilicon structures (110E) do not each extend through a silicon region and across a silicon region (defined by outline (2095))The boundaries of the domains enter the region (2490) but they are joined within the region of the silicon region by a vertical polysilicon structure (2410), the vertical polysilicon structure (2410) defining a common body region for the underside of the two body regions defined by the structure (110E). A horizontal polysilicon protrusion (2420) is then formed at (or near) the midpoint of the structure (2410) and extends horizontally towards the edge of the silicon region (the region contained within the profile (2095)) to form an underlying region of the same type of doping as the body region. Similar to the body protrusion discussed above, the horizontal polysilicon protrusion (2420) provides a low resistivity conductive path (e.g., body protrusion) between the body region underlying the gate polysilicon region (110E) and the body contact region (2450). According to an exemplary embodiment of the present disclosure, the silicon region surrounding the horizontal polysilicon protrusion (2420) near the boundary of the silicon region defined by the contour (2095) is extended to provide an extended region (2460) in which the body contact region (2450) is formed. As can be seen in fig. 24, the body contact region (2450) is formed at the distal end of the extension region (2460) and abuts the non-silicon region defined by the contour (2095) while in contact with the body protrusion defined by the horizontal polysilicon protrusion (2420). The dashed line to one side of the extension region in fig. 24 defines the normal boundary of the silicon region without the extension region (2460).

Although the above-discussed butted body tie in accordance with the present teachings is described as a top transistor configured to the cascode of stacked transistors, e.g., transistor T of fig. 20A_BAnd a transistor T of FIG. 20B_EThe (fingers of) provide a butted body tie, but such butted body ties may also be used together in the same cascode configuration of stacked transistors (e.g., fig. 8I-8K and 20A-20B) including two, three, four, or more stacked transistors to provide a butted body tie to the fingers of the stacked lower transistors as described with reference to fig. 25-29B described below. In case the cascode-stacked transistor comprises more than one finger, one or more fingers of the same transistor may be provided with such a butt-body tie, and/or one or more fingers of the same transistorThe fingers may be provided without a docking body connection. The teachings in accordance with the present disclosure provide methods and structures for forming such a docking body joint using standard manufacturing steps known in the art that may be used by a person skilled in the art to meet his/her design requirements. Where space efficiency is required, the spacing between adjacent fingers may be reduced using the butt body joint (2100B, 2200, 2300, 2400) according to the present disclosure depicted in fig. 21B-24.

Fig. 25 illustrates a portion of a two transistor cascode stack (e.g., fig. 20A) with the above-described butted body tie in accordance with the present teachings. FIG. 25 shows a diagram for a (bottom) transistor T_ATransistor T having a mirror image of the centre line of the source region_AAnd T_BTwo fingers of each of the two. As can be seen from fig. 25, a butt body bond (2200) according to fig. 22 described above is provided to the top transistor T_BThe fingers (defined by the gate polysilicon structure (110B)), the abutting body joint is formed by the structures (510B, 540B, 2090). As previously described, the structure (510B) defines an underlying (low resistivity) conductive region of the same doping as the body region of the finger, which electrically connects the body region of the finger to the body contact region (540B). The butted body tie (800B) according to fig. 8B described above is provided to the bottom transistor T of the cascode stack_AThe docking body coupling is defined by a structure (510A, 540A).

Fig. 26 illustrates a portion of a three transistor cascode stack (e.g., fig. 20B) with the above-described butted body tie in accordance with the present teachings. FIG. 26 shows a diagram for a (bottom) transistor T_CTransistor T having a mirror image of the centre line of the source region_C、T_DAnd T_ETwo fingers of each of the two. As can be seen in FIG. 26, a butted body tie (2300) according to FIG. 23 described above is provided to the top transistor T_EThe fingers (defined by the gate polysilicon structure (110E)), the abutting body joint (2300) is formed by the structures (510E, 540E, 2090). As previously described, the structure (510E) defines a body region with the fingersAn identically doped underlying (low resistivity) conductive region electrically connecting the body region of the finger to the body contact region (540E). The butted body bond (2200) according to fig. 22 described above is provided to the intermediate transistor T_DThe abutment body connection (2200) is formed by structures (510D, 540D, 2090). Finally, the butted body tie (800B) according to fig. 8B described above is provided to the bottom transistor T of the cascode stack of three transistors_CThe docking body coupling (800B) is defined by structures (510C, 540C).

Fig. 27 shows the full width structure (2700) of the three transistor cascode stack of fig. 20B equipped with abutting body ties to reduce the physical size of the cascode stack in accordance with various teachings of the present disclosure. FIG. 27 shows a diagram for a (top) transistor T_ETransistor T having a mirror image of the centre line of the drain region_C、T_DAnd T_EFour fingers of each of the top transistors are defined by a gate polysilicon region (110E). As can be seen from FIG. 27, the transistor T_C、T_DAnd T_EFurther with respect to the bottom transistor T_CIs mirrored by the centre line of the source region comprised by the bottom transistor T_CAnd the transistor T is formed in a region defined by the two gate polysilicon structures (110C)_C、T_DAnd T_EFurther with respect to the bottom transistor T_CIs mirrored by the centre line of the source region comprised by the bottom transistor T_CWithin the region defined by the two gate polysilicon structures (110C).

With further reference to fig. 27, the top transistor T of the cascode stack_EEach finger (defined by structure 110E) is provided with a butt-body joint structure (2300), with an intermediate transistor T_DEach finger (defined by structure 110D) is provided with two abutting body tie structures (2200), and a bottom transistor T_CIs provided with four docking body coupling structures (800B) per finger (defined by structure 110C), wherein docking body coupling structures are provided above with reference to fig. 26Details of the structure (800B, 2200, 2300).

With continued reference to fig. 27, a butted body tie (2400) in accordance with the teachings of the present disclosure, discussed above with reference to fig. 24, is provided to the top transistor T_EThe finger of (2700) defining a centerline of the drain region of the (cascode) structure of fig. 27. Such docking body coupling (2400) includes the structures (2410, 2420, 2450, 2460) described above with reference to fig. 24. Thus, the top transistor T_EHas one abutting body tie structure (2300) at a midpoint of a width of the structure (2700) and two abutting body tie structures (2400) at opposite ends of the width.

FIG. 28 shows the same full width structure as FIG. 27, except that the butted body tie structure (2400) is removed, thereby leaving the top transistor T_EEach having a single abutting body joining structure (2300).

Fig. 29B shows a full width structure (2900B) of the four transistor cascode stack (2900A) of fig. 29A equipped with body ties to reduce the physical size of the cascode stack according to various teachings of the present disclosure. FIG. 29B shows the transistor T (top)_ECentral line C of drain region_LMirrored transistor T_B、T_C、T_DAnd T_EFour fingers of each of the top transistors are defined by a gate polysilicon region (110E). As seen from FIG. 29B, the transistor T_B、T_C、T_DAnd T_EFurther with respect to the bottom transistor T_BIs mirrored by the centre line of the source region comprised by the bottom transistor T_BAnd the transistor T is formed in a region defined by the two gate polysilicon structures (110B)_B、T_C、T_DAnd T_EFurther with respect to the bottom transistor T_BIs mirrored by the centre line of the source region comprised by the bottom transistor T_BWithin the region defined by the two gate polysilicon structures (110B).

Further referenceFIG. 29B, top transistor T of cascode stack_EEach finger (defined by structure 110E) is provided with a butt-body joint structure (2400), a transistor T_DEach finger (defined by structure 110D) is provided with a butt-body joint structure (2300), transistor T_CEach finger (defined by structure 110C) is provided with two abutting body tie structures (2200), and a bottom transistor T_BEach finger (defined by structure 110B) is provided with four docking body coupling structures (800B), wherein details of the docking body coupling structures (800B, 2200, 2300, 2400) are provided above with reference to fig. 26 and 24. In contrast to the full width structure (2700) depicted in fig. 27 described above, the full width structure (2900B) depicted in fig. 29B provides only one type of butted body tie structure (structure 2400) to the top transistor of the cascode stack, in contrast to the two butted body tie structures (2300, 2400) provided to the top transistor of the stack corresponding to structure (2700).

As can be seen in fig. 27, 28 and 29B, to the transistor (e.g., T)_E、T_D) The body protrusion of the butted body joint structure of the finger (e.g., body protrusion (510B, 510E) of body joint structure (2200, 2300) as shown in fig. 22-23) passes over the next (lower) transistor (e.g., T)_D、T_C) Is provided by forming a break in the gate polysilicon structure of adjacent fingers. Then to the next transistor (e.g., T)_D) By passing the next (lower) transistor (e.g., T) over the body protrusion (e.g., 510D) of the docking body link_C) Is provided by forming a break in the gate polysilicon structure of adjacent fingers, and so on. Thus, for each level, starting from the top transistor of the cascode stack of multiple transistors and down to the bottom transistor of the cascode stack, the number of body protrusions in the fingers of the transistors of the cascode stack doubles, since each segment of the disconnected gate polysilicon structure (110D,..., 110C) may be provided with one body protrusion (abutting body tie), which may require a disconnection in the adjacent gate polysilicon structure. This is done in FIG. 28Exemplifying, among others, a top transistor T_EThe finger of (A) is provided with a butt body joint structure (2300) with a body protrusion (510E) on the next lower transistor T_DIs formed in the break region of the gate polysilicon structure (110D) of the finger, thereby forming two different gate polysilicon structures (110D) on each side of the break, each gate polysilicon structure in turn having a butted body tie structure (2200). Intermediate transistor T_DThen the two abutting body ties (2200) of the finger(s) cause the gate polysilicon structure (110C) to open, thereby turning off the lower transistor T_CTogether with the breaks formed by the body protrusions (510E), form four different (broken) gate polysilicon structures (110C). Those skilled in the art will recognize that for large cascode stack heights, there may be a large difference in the number of breaks in the gate polysilicon structures of the fingers of the lower and upper transistors in the stack. If desired, such as described above with respect to fig. 21A, this large difference can be reduced by inserting a butting body tie without breaks in the adjacent gate polysilicon structures, which effectively resets the doubling of the number of body projections described above for each transistor level.

Finally, those skilled in the art will appreciate that the various semiconductor structures depicted in the above figures may be physically laid out in various patterns, some of which may include symmetry with respect to various axes, such as the center line C discussed with respect to fig. 22-24, 27, 28, and 29B_LThe symmetry of (a). According to some exemplary embodiments of the present disclosure, such semiconductor structures may be (also) relative to centerline C ', as depicted in fig. 29B'_LSymmetry, center line C'_LThrough the center region of the fingers of the cascode transistor along the length of the fingers.

Those skilled in the art will recognize the cost advantage of the physical size reduction of the cascode configuration brought about by the smaller spacing allowed by the various docking body ties described above with reference to fig. 20A-28. This reduction in physical size may also provide performance advantages for the RF circuitry. For applications requiring a large number of transistor fingers, the closer proximity of the fingers allows for shorter interconnect lengths to connect them. The excessive interconnect length required to connect a large number of transistor fingers may introduce parasitic capacitance, resistance, and inductance, which may degrade RF performance.

Such semiconductor devices, including the cascode configurations discussed above, equipped with improved body tie constructions according to the various teachings of the present disclosure may be used, for example, for Radio Frequency (RF) amplifiers, including but not limited to RF power amplifiers and cellular RF power amplifiers operating under various operating classes, including but not limited to switch classes D, E and F, saturation classes B and C, and linear classes a and a/B.

It should be noted that while various exemplary embodiments according to the present disclosure are provided using the exemplary case of an N-type SOI MOSFET, such exemplary cases are provided primarily for clarity. Various embodiments of a butted body joint according to the present invention may be equally suitable for other transistor types and other transistor technologies, particularly where the source and/or drain regions extend down to an insulating layer, such as the "BOX" layer of an SOI device.

The term "MOSFET" technically refers to a metal oxide semiconductor; another synonym for MOSFETs is "MISFET", i.e. metal insulator semiconductor FET. However, "MOSFETs" have become a common label for most types of insulated gate FETs ("IGFETs"). Nevertheless, it is well known that the term "metal" in the names MOSFET and MISFET is now often misnomed because the previous metal gate material is now often a polysilicon layer (polysilicon). Similarly, the designation "oxide" in a MOSFET may be misnomed because a different dielectric material is used in order to obtain a strong channel at a smaller applied voltage. Thus, the term "MOSFET" as used herein should not be understood as literally limited to a metal-oxide-semiconductor, but instead generally includes IGFETs.

As should be apparent to one of ordinary skill in the art, various embodiments of the present invention may be implemented to meet a wide variety of specific requirements. Unless otherwise noted above, selection of appropriate component values is a matter of design choice, and various embodiments of the present invention may be implemented in any suitable IC technology, including but not limited to MOSFET structures and IGFET structures. Integrated circuit implementations may be fabricated using any suitable substrate and process, including but not limited to standard bulk silicon, silicon-on-insulator (SOI), silicon-on-sapphire (SOS), GaAs pHEMT, and MESFET technologies. However, the inventive concepts described above are particularly useful for SOI-based manufacturing processes (including SOS) as well as manufacturing processes having similar characteristics. Fabrication in CMOS on SOI or SOS achieves low power consumption, ability to withstand high power signals during operation due to the FET stack, good linearity, and high frequency operation (over about 10GHz, especially above about 20 GHz). Monolithic IC implementations are particularly useful because parasitic capacitances can often be kept low by careful design.

The voltage levels may be adjusted or the voltage polarity and/or logic signal polarity reversed depending on the particular specification and/or implementation technology (e.g., NMOS, PMOS, or CMOS and enhancement or depletion transistor devices). Component voltages, currents, and power handling capabilities may be adjusted as needed, for example, by: device sizing, series "stacking" of components (particularly FETs) to withstand higher voltages, and/or use of multiple components in parallel to handle higher currents. Additional circuit components can be added to enhance the capabilities of the disclosed circuits and/or to provide additional functionality without significantly altering the functionality of the disclosed circuits.

Applications that may include the novel apparatus and systems of various embodiments include electronic circuitry for high-speed computers, communication and signal processing circuitry, modems, single-processor or multi-processor modules, single or multiple embedded processors, data switches, and application-specific modules, including multilayer, multi-chip modules. Such apparatus and systems may also be included as sub-components within a variety of electronic systems, such as televisions, cellular telephones, personal computers (e.g., laptop computers, desktop computers, handheld computers, tablet computers, etc.), workstations, radios, video players, audio players (e.g., mp3 players), vehicles, medical devices (e.g., heart monitors, blood pressure monitors, etc.), and so forth. Some embodiments may include a number of methods.

The actions described herein may be performed in an order other than the order described. Various acts described with respect to the methods presented herein may be performed in repetitive, serial, or parallel fashion.

The accompanying drawings that form a part hereof show by way of illustration, and not of limitation, specific embodiments in which the subject matter may be practiced. The embodiments shown are described in sufficient detail to enable those skilled in the art to practice the teachings disclosed herein. Other embodiments may be utilized and derived therefrom, such that structural and logical substitutions and changes may be made without departing from the scope of this disclosure. This detailed description, therefore, is not to be taken in a limiting sense, and the scope of various embodiments is defined only by the appended claims, along with the full range of equivalents to which such claims are entitled.

These embodiments of the inventive subject matter may be referred to herein, individually or collectively, by the term "invention" merely for convenience and without intending to voluntarily limit the scope of this application to any single invention or inventive concept if more than one is in fact disclosed. Thus, although specific embodiments have been illustrated and described herein, any arrangement calculated to achieve the same purpose may be substituted for the specific embodiments shown. This disclosure is intended to cover any and all adaptations or variations of various embodiments. Combinations of the above embodiments, and other embodiments not specifically described herein, will be apparent to those of skill in the art upon reviewing the above description.

The abstract of the present disclosure is provided to comply with 37c.f.r. § 1.72(b), which requires an abstract that will enable the reader to quickly ascertain the nature of the technical disclosure. The abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In the foregoing detailed description, various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted to require more features than are expressly recited in each claim. Rather, inventive subject matter may be found in less than all features of a single disclosed embodiment. Thus the following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.

Claims

1. A semiconductor structure, comprising:

a first gate polysilicon structure defining a first body region, the first body region having a first conductivity type;

a second gate polysilicon structure defining a second body region, the second body region having the first conductivity type;

a first drain region adjacent the first body region having a second conductivity type;

a first source region adjacent to the first body region having the second conductivity type;

a second source region adjacent to the second body region and having the second conductivity type;

a second drain region adjacent to the second body region and having the second conductivity type,

the first source region and the second drain region defining a first common source/drain region having the second conductivity type;

a break region in the second gate polysilicon structure, the break region configured to form a break in the second body region;

a first non-conductive isolation region formed in the interrupted region and configured to divide the second body region into two separate second body regions;

at least one first body contact region of the first conductivity type formed within the first common source/drain region, separate from the first and second body regions and abutting the first non-conductive isolation region; and

at least one first polysilicon protrusion defining at least one first body protrusion of the first conductivity type extending across the first common source/drain region in contact with the first body region and the at least one first body contact region,

wherein the first non-conductive isolation region, the at least one first body contact region, and the at least one first body protrusion define a first mating body joining structure.

2. The semiconductor structure of claim 1, wherein the first non-conductive isolation region is further configured to extend a silicon region of the first common source/drain region to provide a continuous silicon region for the at least one first body contact region and the at least one first body protrusion.

3. The semiconductor structure of claim 1 or claim 2, wherein the first non-conductive isolation region is further configured to form an interruption in the second source region to divide the second source region into two separate second source regions.

4. The semiconductor structure of claim 1 or claim 2, wherein a length of the at least one first body protrusion is greater than a length defined by a spacing between the first body region and the second body region.

5. The semiconductor structure of claim 1, wherein the first body protrusion extends in a direction perpendicular to a direction defined by the first and second body regions along widths of the first and second body regions.

6. The semiconductor structure of claim 1, further comprising:

at least one second body contact region of the first conductivity type separate from the first and second body regions; and

at least one second body projection of the first conductivity type extending into the second source region and contacting one of the two separate second body regions and the at least one second body contact region.

7. The semiconductor structure of claim 6, further comprising:

a further second body contact region of the first conductivity type separate from the first and second body regions; and

a further second body projection of the first conductivity type extending into the second source region and contacting the further second body contact region and the other of the two separate second body regions.

8. The semiconductor structure of claim 6 or claim 7, wherein the at least one second body contact region is formed within the second source region so as to be laterally surrounded by the second source region.

9. The semiconductor structure of claim 6 or claim 7, wherein the at least one second body contact region abuts the second source region.

10. The semiconductor structure of claim 7, wherein the at least one second body contact region and the additional second body contact region form a continuous silicon region.

11. The semiconductor structure of any of claims 1, 2, or 6, wherein the first and second gate polysilicon structures define first and second gate fingers, respectively, of a first transistor and a second transistor arranged in a cascode configuration.

12. The semiconductor structure of claim 11, further comprising:

a further first gate finger of the first transistor;

a further second gate finger of the second transistor; and

another first mating body coupling structure includes:

i) a further first body contact region;

ii) a further first body projection; and

iii) the first non-conductive isolation region,

wherein the further first gate finger, the further second gate finger and the further first butt body tie structure are mirrored about a centerline of the semiconductor structure relative to the first gate finger, the second gate finger and the first butt body tie structure, wherein the centerline is defined by a central region of the second source region along a width of the second source region, the second source region being a common source region of the second gate finger and the further second gate finger.

13. The semiconductor structure of claim 1, further comprising:

a third gate polysilicon structure defining a third body region having the first conductivity type;

a third drain region adjacent to the third body region and having the second conductivity type, the third drain region and the second source region defining a second common source/drain region having the second conductivity type; and

a third source region adjacent to the third body region and having the second conductivity type;

wherein the first non-conductive isolation region is further configured to form an interruption in the third body region and the second common source/drain region to divide the third body region and the second common source/drain region into two separate third body regions and two separate second common source/drain regions, respectively.

14. The semiconductor structure of claim 13, further comprising a second docking body attachment structure, the second docking body attachment structure comprising:

a second non-conductive isolation region configured to form an interruption in one of the two separate third body regions;

a second body contact region of the first conductivity type formed within the region of the second common source/drain region, separate from the second and third body regions and abutting the second non-conductive isolation region; and

a second body protrusion of the first conductivity type extending across a region of the second common source/drain region, contacting one of the two separate second body regions and the second body contact region,

wherein the region of the second common source/drain region is one of the two divided second common source/drain regions adjacent to the one of the two divided second body regions.

15. The semiconductor structure of claim 14, wherein the second non-conductive isolation region is further configured to extend the silicon region of the second common source/drain region to provide a continuous silicon region for the second body contact region and the second body protrusion.

16. The semiconductor structure of claim 14 or claim 15, wherein the second non-conductive isolation region is further configured to form an interruption in the third source region to divide the third source region into two separate third source regions.

17. The semiconductor structure of claim 14 or claim 15, wherein a length of the second body protrusion is greater than a length defined by a spacing between the second body region and the third body region.

18. The semiconductor structure of claim 14, wherein the second body protrusion extends in a direction perpendicular to a direction defined by the second and third body regions along widths of the second and third body regions.

19. The semiconductor structure of claim 14, further comprising an additional second docking body tie configuration associated with the other of the two separate second body regions.

20. The semiconductor structure of claim 19, wherein the additional second docking body coupling arrangement comprises:

a further second non-conductive isolation region configured to form an interruption in the other of the two separate third body regions;

a further second body contact region of the first conductivity type formed within the region of the second common source/drain region, separate from the second and third body regions and abutting the further second non-conductive isolation region; and

a further second body protrusion of the first conductivity type extending across a region of the second common source/drain region, in contact with the further second body contact region and the other of the two separate second body regions,

wherein the region of the second common source/drain region is one of the two divided second common source/drain regions adjacent to the other of the two divided second body regions.

21. The semiconductor structure of claim 20, wherein the additional second non-conductive isolation region is further configured to extend the silicon region of the second common source/drain region to provide a continuous silicon region for the additional second body contact region and the additional second body protrusion.

22. The semiconductor structure of claim 20 or claim 21, wherein the additional second non-conductive isolation region is further configured to form an interruption in the third source region to further divide the third source region into further separate third source regions.

23. The semiconductor structure of claim 20 or claim 21, wherein the length of the further second body projection is greater than a length defined by a spacing between the second and third body regions.

24. The semiconductor structure of claim 20, wherein the additional second body protrusion extends in a direction perpendicular to a direction defined by the second and third body regions along their widths.

25. The semiconductor structure of claim 19, further comprising at least one third butt-body tie structure associated with one of the separate third body regions, the at least one third butt-body tie structure comprising:

a third body contact region of the first conductivity type separate from the second and third body regions; and

a third body projection of the first conductivity type extending across the third source region and contacting one of the spaced apart third body regions and the third body contact region.

26. The semiconductor structure of claim 25, further comprising a plurality of third butt-body tie structures, each third butt-body tie structure associated with a different one of the separate third body regions.

27. The semiconductor structure of claim 25 or claim 26, wherein the third body contact region is formed within the third source region to be laterally surrounded by the third source region.

28. The semiconductor structure of claim 26, wherein at least one third body contact region of the plurality of third butted body tie structures abuts the third source region.

29. The semiconductor structure of claim 28, wherein two or more third body contact regions of the plurality of third butted body tie structures form a continuous silicon region.

30. The semiconductor structure of any of claims 14, 19, 25 and 26, wherein the first, second and third gate polysilicon structures define a first finger of a first transistor, a second finger of a second transistor and a third finger of a third transistor, respectively, arranged in a cascode configuration.

31. The semiconductor structure of claim 30, further comprising:

a further first finger of the first transistor;

a further second finger of the second transistor;

a further third finger of the third transistor;

at least one other first docking body coupling structure comprising:

i) a further first body contact region;

ii) a further first body projection; and

iii) the first non-conductive isolation region; and

at least one additional second docking body coupling structure, comprising:

iv) a further second body contact region;

v) a further second body projection; and

vi) the second non-conductive isolation region;

wherein the first further finger, the second further finger, the third further finger, the first further butt body tie structure and the second further butt body tie structure are mirrored about a centerline of the semiconductor structure relative to the first finger, the second finger, the third finger, the first butt body tie structure and the second butt body tie structure, wherein the centerline is defined by a central region of the third source region along a width of the third source region, the third source region being a common source region of the third finger and the third further finger.

32. The semiconductor structure of claim 11, wherein the transistor of the cascode configuration is a Metal Oxide Semiconductor Field Effect Transistor (MOSFET).

33. The semiconductor structure of claim 32, wherein the transistor is fabricated using a technique according to one of the following: a) silicon On Insulator (SOI) technology, and b) Silicon On Sapphire (SOS) technology.

34. The semiconductor structure of claim 30, wherein the transistor is a Metal Oxide Semiconductor Field Effect Transistor (MOSFET).

35. The semiconductor structure of claim 34, wherein the transistor is fabricated using a technique according to one of the following: a) silicon On Insulator (SOI) technology, and b) Silicon On Sapphire (SOS) technology.

36. The semiconductor structure of claim 32, adapted for use as a Radio Frequency (RF) amplifier, the RF amplifier comprising an RF power amplifier comprising one or more of a cellular RF power amplifier, a switching RF power amplifier, a Complementary Metal Oxide Semiconductor (CMOS) RF power amplifier, and a cellular CMOS RF power amplifier.

37. The semiconductor structure of claim 36, wherein the operational categories of the amplifier are one or more of the following categories: i) linear class a, ii) linear class a/B, iii) saturation class B, iv) saturation class C, v) switching class D, vi) switching class E, and vii) switching class F.

38. The semiconductor structure of claim 34, adapted for use as a Radio Frequency (RF) amplifier, the RF amplifier comprising an RF power amplifier comprising one or more of a cellular RF power amplifier, a switching RF power amplifier, a Complementary Metal Oxide Semiconductor (CMOS) RF power amplifier, and a cellular CMOS RF power amplifier.

39. The semiconductor structure of claim 38, wherein the operational categories of the amplifier are one or more of the following categories: i) linear class a, ii) linear class a/B, iii) saturation class B, iv) saturation class C, v) switching class D, vi) switching class E, and vii) switching class F.

40. A semiconductor structure, comprising:

at least two semiconductor structures including a first semiconductor structure and a second semiconductor structure each according to claim 12, the first and second semiconductor structures being mirrored about a centerline of the first drain region of the first gate finger of the first and second semiconductor structures, the centerline being along a width of the first drain region defining a common first drain region, the semiconductor structures further comprising:

a first vertical polysilicon structure joining the first gate polysilicon structure at a first end of the first gate polysilicon structure of the first and second semiconductor structures, the first vertical polysilicon structure defining a lower common body region to the first body regions of the first and second semiconductor structures; and

a first horizontal polysilicon structure extending from a midpoint of the first vertical polysilicon structure through a first edge of a silicon region of the semiconductor structure, the first horizontal polysilicon structure extending the lower common body region to the first edge of the silicon region.

41. The semiconductor structure of claim 40, further comprising:

a second vertical polysilicon structure joining the first gate polysilicon structure at a second end of the first gate polysilicon structure of the first and second semiconductor structures, the second vertical polysilicon structure defining a lower common body region to the first body regions of the first and second semiconductor structures; and

a second horizontal polysilicon structure extending from a midpoint of the second vertical polysilicon structure through a second edge of the silicon region of the semiconductor structure opposite the first edge, the second horizontal polysilicon structure extending the lower common body region to the second edge of the silicon region.

42. A semiconductor structure, comprising:

at least two semiconductor structures including a first semiconductor structure and a second semiconductor structure each according to claim 31, the first and second semiconductor structures being mirrored about a centerline of the first drain region of the first finger of the first and second semiconductor structures, the centerline being along a width of the first drain region defining a common first drain region, the semiconductor structures further comprising:

43. The semiconductor structure of claim 42, further comprising:

44. A semiconductor structure comprising a plurality of transistors, the semiconductor structure comprising:

an insulating layer;

a silicon layer covering the insulating layer;

an active region formed in the silicon layer, the active region extending through the silicon layer to contact the insulating layer, the active region including a body region, a source region, and a drain region of one or more fingers of each transistor of the plurality of transistors, the plurality of transistors configured as a cascode stack arranged from top to bottom, wherein, for each two consecutive transistors of the cascode stack, the source region of the finger of the top transistor and the drain region of the finger of the bottom transistor of the each two consecutive transistors are formed in a common source/drain region of the silicon layer; and

at least one abutting body tie structure associated with fingers of the top transistor, comprising:

i) a non-conductive isolation region;

ii) body contact regions formed within the common source/drain regions of the fingers of the top and bottom transistors of two successive transistors, separate from the body regions of the fingers of the top and bottom transistors and abutting isolation regions of the non-conductive isolation regions; and

iii) a body protrusion region formed in the silicon layer in contact with the body contact region and the body region of the finger of the top transistor,

wherein at least one of the non-conductive isolation regions is configured to:

forming a discontinuity in a region of the silicon layer defining a body region of the finger of the bottom transistor to divide the body region of the finger of the bottom transistor into separate body regions, an

Extending a discontinuity in such region of the silicon layer to divide the region into separate regions, wherein the regions define a body region and a common source/drain region of fingers of one or more successive transistors adjacent the bottom transistor.

45. The semiconductor structure of claim 44, further comprising:

additional butted body tie structures associated with fingers of the bottom transistor, wherein a body protrusion region of each of the additional butted body tie structures is in contact with a separate body region of the fingers of the bottom transistor.

46. The semiconductor structure of claim 45, wherein:

each finger of a transistor of the plurality of transistors includes a number of associated abutting body tie structures equal to the number of separate body regions of each finger, and

the body projection region of each of the associated docking body coupling structures is in contact with the separate body region of each finger.

47. The semiconductor structure of claim 44 or claim 45, wherein:

the cascode stack includes a first top transistor and a last bottom transistor,

each transistor of the plurality of transistors of the cascode stack comprises two or more fingers; and is

The regions of any two fingers of each transistor are mirrored about a centerline defined by the central region of a common source region along the width of the common source region, the common source region being the source regions of the two fingers of the last bottom transistor.

48. The semiconductor structure of claim 47 wherein the semiconductor structure is symmetric with respect to the center line.

49. The semiconductor structure of claim 47, wherein each finger of the first top transistor comprises one and only one associated butted body tie structure.

50. The semiconductor structure of claim 47 wherein each finger of a transistor adjacent to the first top transistor comprises one and only one associated butted body tie structure.

51. The semiconductor structure of claim 50 wherein the regions of any two fingers of each transistor are further mirrored about a centerline defined by a central region of a common drain region along a width of the common drain region, the common drain region being the drain regions of two fingers of the first top transistor, the two fingers including a first top finger and a second top finger, the semiconductor structure further comprising:

a vertical polysilicon structure joining the gate polysilicon structures of the first and second top fingers, the vertical polysilicon structure defining a lower common body region to the body regions of the first and second top fingers; and

a horizontal polysilicon structure extending from a midpoint of the vertical polysilicon structure through an edge of a silicon region of the semiconductor structure, the horizontal polysilicon structure extending the lower common body region to the edge of the silicon region.

52. The semiconductor structure of claim 51, wherein the semiconductor structure is symmetric with respect to a center line passing through a center of the one or more fingers along a length of the one or more fingers of each transistor of the plurality of transistors.

53. The semiconductor structure of claim 48, wherein the semiconductor structure is symmetric with respect to a center line passing through a center of the one or more fingers along a length of the one or more fingers of each transistor of the plurality of transistors.

54. The semiconductor structure of claim 49, wherein the semiconductor structure is symmetric with respect to a center line passing through a center of the one or more fingers along a length of the one or more fingers of each transistor of the plurality of transistors.

55. A method for providing body tie to transistors arranged in a cascode configuration, the cascode configuration comprising:

a second drain region adjacent to the second body region and having the second conductivity type, an

the method comprises the following steps:

forming a break region in the second gate polysilicon structure, thereby forming a break in the second body region;

forming a first non-conductive isolation region in the interrupted region, thereby dividing the second body region into two separate second body regions;

forming at least one first body contact region of the first conductivity type within the first common source/drain region, the at least one first body contact region being separate from the first and second body regions and abutting the first non-conductive isolation region; and

forming at least one first body protrusion of the first conductivity type by a first polysilicon protrusion, the at least one first body protrusion extending across the first common source/drain region, contacting the first body region and the at least one first body contact region,