DE2255633A1 - ELECTRONIC MEMORY CIRCUIT, IN PARTICULAR FOR ELECTRONIC DISTANCE COUNTERS IN MOTOR VEHICLES - Google Patents

Description

Patent Attorneys., 2255633 Dipl.-Ing. W. Beyer Dipl.-Wirtsch.-Ing. B. Jochem.

Prankfurt am Main Freiherr-vom-Stein-Str, 18

In matters:

Ford «Works Public Company
5 K ö In / Rhine
Ottoplatz 2

Electronic memory circuit, in particular for electronic odometers in motor vehicles.

The invention relates to an electronic memory circuit, in particular for electronic odometers in motor vehicles. , ...-, '".- ■"

Recent proposals for automotive instrument kits contain systems in which the conventional electromechanical Instruments are replaced by electronic instrumentation systems in which the vehicle speed darr information and other operating conditions of the Vehicle and the prime mover by electroluminescent films, gas discharge devices and other devices that have no moving parts. One instrument that poses particular problems is that Odometer, since the display of the entire distance covered by the odometer must be retained even if all electrical systems of the vehicle are used are switched off and only when the battery removed from the vehicle

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The object of the invention is to provide an electronic memory circuit in particular to create for this purpose, through which the aforementioned condition, namely the maintenance of the stored count is also guaranteed is when the supply voltage is switched off or on other way is not applicable. According to the invention, this object is achieved by

(a) a counting circuit for registering a specific Number of input pulses arriving at a counter input as a combination of the states of a plurality bistable transistor circuits,

'(b) a multitude of bistable magnetic core memories, from each of which is connected to a bistable transistor circuit in such a way that the magnetic core memory It is switched every time the associated transistor circuit changes its switching state, whereby the magnetic core memory also counts the number of pulses received as a combination of states save, and

(c) a data recovery circuit that comes into operation when the electrical power supply for the circuit is available again after disconnection or other omission, to the transistor circuits in the same Bringing a combination of states like the magnetic core memory.

An embodiment of the invention is explained in more detail below in connection with the drawing, in the only one FIG. 2 shows a circuit diagram of an electronic memory circuit for use in an odometer in FIG a motor vehicle is shown.

According to the exemplary embodiment, the odometer of a motor vehicle contains an electrical storage circuit 10,

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which counts the input pulses arriving at a counter input 11. These impulses occur every time that Vehicle has traveled a predetermined distance and you can use one of the vehicle wheels or the Transmission of the vehicle coupled pulse generator are generated. .

A digital display device (not shown) is used from the output of the electronic memory circuit in such a way that a visible digital display of the in the memory circuit stored count is caused, so that the display ^ shows the total distance traveled by the vehicle. The display device does not have any moving parts and works by electro-luminescence, gas discharge or some other physical phenomenon that converts electrical signals into light. One conventional embodiment of such a display device employs a layer of DC responsive luminescent material between two Electrodes is packed, which in turn are arranged so that different areas of the electro-luminescent Materials to be excited. Such a display has the advantage that the odometer in a two-dimensional flat construction with the other vehicle instruments, such as the speedometer, fuel gauge, etc. can be included to provide an instru to create ment set that can be easily accommodated in the vehicle and takes up little space.

The memory circuit 10 includes a plurality of bistable ones Transistor circuits 12A to 13D, which are so interconnected are that they have a binary coded decimal counter form. This circuit, which uses J-K bistable elements, is known per se ("Electronic Counters - circuits techniques devices "by Mullard, published 1967» page 113). The drawing figure shows only one decade of the counting circle.

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Further identical decades can be added if necessary.

Each bistable circuit has two outputs Q and 1 £, which according to the logic current condition of the circuit is selectively energized will.

A plurality of bistable magnetic core memories 13Α-13Ϊ · are each connected to a bistable transistor circuit 12 by a pair of write windings 14-A to 14D and 15A to 15D. All write windings 14-, 15 are connected to a common feed line 16, which via a delay switch 17 a certain time after connection of the circuit to the supply voltage V _x . can be excited via a main switch 16. The other end of the write winding 14A is connected to ground via a switching transistor 19A, which normally blocks, but can be switched into the conductive state instantaneously by the appearance of a signal at the Q output of the bistable transistor circuit 12A. Similarly, the other end of the write winding 15A is connected to ground via a switching transistor 20A to the Q output of the bistable transistor circuit 12A. The write windings of the other magnetic core memories 13 are connected in a similar manner to the outputs Q and TJ ″ of the associated bistable transistor circuit.

Each time one of the bistable transistor circuits 12 changes its state, one of the associated write windings becomes energizes and switches the relevant magnetic core memory 13 into a corresponding state, so that the states of the bistable circles are held by the magnetic memory.

If the circuit is switched off, the count stored by the bistable transistor circuits is lost,

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however, the magnetic core memories remain in the same state.

When the supply voltage returns, the bistable circuits receive the supply voltage at once through the Line 21, and the reset inputs of the bistable circuits 12 are energized by an RC circuit 22, a level detector circuit 23 and gate 24 for a limited reset period. The supply voltage V is provided by the magnetic core ' store held back by a signal in a line 23, to ensure that the states of the magnetic core memories do not change during this reset period will. . '

When the signal in the line 23 ends, the delay switch 17 applies the write windings 14 and 15 to the supply voltage Yy, and a pulse generator circuit 24 generates a pulse on an interrogation line 25 'which is connected to all magnetic core memories 13. This pulse has the correct polarity in order to switch all those magnetic core memories which are in the 1 state to the O state, while it leaves all magnetic core memories in the O state unaffected.

Generate those magnetic core memories that were in the 1 state a pulse in their sense windings 26A to 2GD by switching to the 0 state. Each reading winding 26 is via an amplifier 27A and a blocking and delay circuit 28 to the setting input S of the associated bistable transistor circuit 12 connected. The delay circle 28 delays the forwarding of the read pulse to the setting input S until the interrogation pulse arrives at the Line 25 has ended. After the end of the interrogation pulse, the bistable circuits are therefore switched to states which correspond to the states of the magnetic core memory before the interrogation signal was applied.

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Every bistable circuit that starts from an O-state (return state) switches to the 1-state (set-up status), generates a signal at output Q, which the associated ^ Magnetic core switches back to "1". The circuit is then exactly in the same state as before, as the Supply voltage was interrupted and the pulse counting can continue.

The outputs Q and ~ C [of the bistable circuits 12 are connected to the display device.

Patent claims /

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Claims (1)

Claims / 1.' Electronic memory circuit, in particular for electronic odometers in motor vehicles, characterized by (a) a counting circuit for registering a certain number of input pulses arriving at a counter input (11) as a combination of the states of a multiple number bistable transistor circuits (12A-12D), (b) a multitude of bistable magnetic core memories of which nin, yoder to a bistable Trnnrn storkkreis (12A-12D) is connected so that the magnetic core memory is switched every time the associated transistor circuit changes its switching state, whereby the magnetic core memory also reduces the number of as . store a combination of states recorded pulses, and (c) a data recovery circuit that comes into operation when the electrical power supply to the Circuit is available again after shutdown or other omission, to the transistor circuits in the same. To bring a combination of states like the magnetic core memory. • 2. Memory circuit according to claim 1, characterized characterized in that the data transmission circuit consists: (n) Tfuekntollnri tfcoln, din come into action when the »oil olitrinoho energy supply is re-established to keep all transistor circuits (12A-12D) in the same state Fo 84Ο6 / 13.11.1972 3 0 9 8 2 3/0705 BATH ORIGINAL zn turn, (b) Interrogation means that come into action after the Tranrdstorkkreis (12A-12D) by the reset means are set to excite an interrogation winding of the magnetic core memory in such a way that these memories are in the state corresponding to the state in which the transistor circuits were set, no output signal generated on the interrogation or read windings and each magnetic core memory of a different state in the corresponding State is switched and an output signal is generated on its query or read winding, and ■ '' * ' (c) a plurality of data transmission circuits, each of which is the interrogation or reading winding of the associated Magnetic core memory connects to the associated transistor circuit, each of which reacts to an output pulse from the interrogation or reading winding to which it is connected, responds to the associated To switch the transistor circuit to its other state. 3 · Memory circuit according to Claim 2, characterized in that each data transmission circuit has delay means for delaying the switching of the associated transistor circuit contains until the query winding is energized. 4. Memory circuit according to one of the preceding claims, characterized in that that each bistable transistor circuit (12A-12D) has two outputs (Q and Q), which are optionally in accordance with the State of the circuit are energized, with both outputs connected to the associated magnetic core memory (13A-13D) and the magnetic core memory is in the one state reversed Po 8406 / November 15, 1972 309 3 23 / 070B 'is switched when the one output is energized, and in the other state is switched when the other output is energized. 5. Memory circuit according to one of the preceding claims , characterized in that the counting circuit is a binary encoded decimal counting circuit. 6. Memory circuit according to one of the preceding claims, characterized by its application in connection with a digital display device, 3 0 9 B 2 3/0 7 0 5 Blank page