DE2242912A1 - DATA PROCESSING ARRANGEMENT - Google Patents

Description

13500 North Central Expressway
Dallas, Texas . .
V.St.A.

Our reference: T 1264

Data processing arrangement

The invention relates generally to a data processing arrangement and in particular to a data processing arrangement having a monolithic on a wafer integrated.Zentralunit, which is combined with external storage devices · and on a method for their Activity.

There are numerous combinations of central units in industry and external storage, each with a variety of advantages in terms of size, speed, cost, etc. Recently, it is particularly special from the standpoint of cost has become advantageous to use a memory circuit in the predominantly field effect transistors with insulated gate electrode can be applied. 3? For most

Black / Pe

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£ 242912

Applications must be the memory with circuits in Transistor-Transistor-Logilc (TTL) compatible eein. the typical difficulties of such a memory are the speed of operation, the flexibility of use, of the general size, it being desirable to have the area of the semiconductor material required for the arrangements to reduce. From the. From the standpoint of reliability and manufacture, it is desirable to have the number to minimize the external connections between different platelets in the array.

It is accordingly an object of the invention to provide an improved central processing unit and associated memory system create.

Furthermore, a central unit is to be created with the help of the invention, which either with external series - or Random access memory can be used without changing the circuit.

In addition, the central unit to be created by the invention can be interrupted so that an external command can be entered by applying a single input signal.

Furthermore, a data processing arrangement is intended with the aid of the invention can be created in which two separate central processing units are used, one external Share memory at the same time

In the data processing arrangement to be created with the aid of the invention two separate pro-

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programs can be executed.

According to the invention, a parallel central unit produced in integrated technology on a single monolithic plate. In a preferred embodiment sform, the central unit contains an eight-bit character-oriented general-purpose unit, the is designed as a single, large-scale integrated metal-oxide-semiconductor circuit (MOS / LSI). 'The The central unit is connected to the external storage units, which can store data up to 65K Bytes allow. Pure the connection between the central unit, A coupling circuit is provided for the external memory and peripheral devices. The central unit contains, combine via a common parallel bus, a parallel arithmetic unit, program and Memory address register and a command register. A control circuit of the central unit synchronizes both the time control for the internal processes of the central unit as well as for the coupling circuit between the central processing unit, the memory and the peripheral devices. Internally, the central unit is time-controlled in such a way that that a cycle has a four-state retrieval sub-cycle, in the course of which an access to the external memory and contains a four-state execution sub-cycle in which Process history data or commands found from external memory during the partial polling cycle have been.

A feature of the data processing arrangement according to the invention is that two separate central units

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used together with a single external storage will. The central units are synchronized in such a way that one central unit is in the retrieval sub-cycle, if a memory access is required while the other central processing unit is currently in the execution sub-cycle is located. The two central units share a coupling circuit in which system inputs and system outputs be treated. Each central unit has its own external memory holding circuits for storage of the command you have just executed to selectively save your accumulator contents, if Results of arithmetic operations are desired. In particular, the synchronization circuit receives a Input signal indicating that one of the central processing units is starting the execution of a first program target. At the same time, a program is executed by the second central unit. The input signal delivers a Low logic signal to the second central unit, so that it is ensured that it is in waiting mode records. A detector circuit provides a trigger output to the first central processing unit when the second Central unit goes into waiting mode. The first central unit then runs through the retrieval sub-cycle, wherein the finding of addressed data from the shared memory at the end of the retrieval sub-cycle of the first Central unit enables this to begin its sub-cycle for the execution of its program.

The operation of the data processing arrangement with two central units sharing a memory offers numerous options Operating speed advantages ", since two programs can be run at the same time, as well as,

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in terms of costs, since there is only one coupling circuit is needed because the operating time of the arrangement is reduced will.

According to one feature of the invention, devices are provided with the aid of which an optional input signal can be synchronized at selected time intervals during operation of the central unit. The operation of the central unit according to the invention is completely synchronous. Certain signals are inherently asynchronous, for example an external command to interrupt the operation of the central unit so that an external command can be entered. A timing control circuit is provided for sampling a transition of the logical signal value of this type of input signal. A plank detector is used which provides a single output pulse. This pulse is stored up to a point in time or time frame in the operating cycle of the central unit during which an interrupt signal can be accepted. According to a feature of the invention, a programmable logic field is used to determine the time interval during the course of which a pulse from the KLank detector causes the operation of the central unit to be interrupted. This offers the advantage of flexibility when setting up different central processing units, since the time frame can be changed by simply entering a gate mask. In accordance with this feature of the invention, a single input signal provides means for entering external commands. This is in contrast to conventional techniques which typically use programs to store everything in the central processing unit's external memory. Such techniques require multiple inputs and outputs.

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Another feature of the invention relates to a Circuit in the central unit that enables external memories with serial or random access to use. A signal is generated every time the desired memory location matches the selected memory location is equivalent to. There is always a correlation in random access memory and the signal is always true. For serial memories, however, a step-by-step run through successive memory locations must be carried out until the desired memory location is selected, at which point the signal is generated. This signal triggers the logic circuit of the central unit, so that a normal sequence is allowed. That way is the operation of the central unit with a random access memory is continuous. With a serial memory goes the central unit, however, in a waiting state at the end of the polling sub-cycle (in a preferred embodiment) until the signal indicating that the correct address has been selected is present. It's a programmable EeId which can be used to vary the interval during which the signal is sampled to determine whether the central processing unit is on hold should pass over.

According to a further feature of the invention, a contains Dali The processing arrangement has a central processing unit with data registers, which are obtained from a single dynamic random access memory matrix are formed. The matrix is divided into first and second groups of data registers, respectively linked to form pairs. In this way, there is an increased possibility of data addressing. In the preferred embodiment, the registers each have

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eight bits in length, making a register pair sixteen Can store bits of address information. A pair of the two register groups is called a bidirectional one static counter selected to act as a program addressing register. The remaining register pairs form a multi-level program address stack based on the principle works so that the information entered last is output again first. This creates hardware facilities for absolute 16-bit addressing for subroutine calls. The counter counts for subroutine call commands one direction, and he chooses for the program address Select a new pair of registers. The previous register pair saves the address for a return to the previously executed program. In response to a return order the counter counts in the opposite direction.

The memory matrix also contains a third group of data registers, that work as a multipurpose register »On this In this way, all data storage registers of the central processing unit are formed as part of a single matrix. This has the advantage the reduction of the required on the platelet. Place. For the selective coupling of the matrix to the internal Further logic units are provided on the collecting line. The. · Logic devices can either be the first or the second or select the third group of registers to connect to the manifold · Palis none of the registers selected is, a renewal counter is triggered, which renews a row of the memory cells. The renewal counter is counted during triggered each operating cycle of the central unit at least once. -

An additional feature of the invention is a

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Form arithmetic unit (ALU) that is used to carry out separate Logic operations and arithmetic operations share a common logic circuit used.

According to the invention, the arithmetic unit of the central unit contains a common one for use in a data processing arrangement Logic circuit for performing arithmetic operations. In the preferred embodiment, this leads Arithmetic unit through eight punctures, namely the addition, the Addition with carry, the subtraction, the subtraction with borrowing, the AND link, the non-equivalence link and the comparison function. Three bits of an instruction are coded to determine the desired operation. A decoding circuit receives these three inputs and provides a group of output fire signals to the logic circuit. The logic circuit contains a complex or and not gate for negating the subtrahend in subtraction operations, a NAND gate for performing an AND operation and for forming a carry generation signal a first for addition and subtraction operations Logical gate, that of the inverse execution of a non-equivalence gate corresponds to, or that for the execution of an exclusive equivalence operation and for the generation of the carry expression for addition and subtraction operations, a second logic gate, that of the inverse Execution of a non-equivalence gate for controlling the output signal in the non-equivalence operation corresponds to and which forms the sum output of a bit of the arithmetic unit, and a carry circuit for generating a carry signal within a bit and for transmitting a carry signal intermediate bit for addition, subtraction and comparison operations.

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The arithmetic unit offers the advantages of a reduced number of gates for performing the arithmetic operations and the logical operations with a corresponding reduction in size and an increase in operating speed.

According to a feature of the invention, a parity circuit with precharge generally contains two columns of interconnected field effect transistors (PET), the columns each being provided with outputs corresponding to even parity and odd parity. In the column for the odd parity, two ν series-connected field effect transistors with insulated gate electrodes (IGFET) are connected in parallel between a first node and a first phase of a clock signal a logical signal value or the negated signal value of a second input signal are applied. The other transistor pairs contain gate electrodes for receiving a second signal with a logical signal value or the inverted signal value of the first input signal. The first circuit point is connected to a negative voltage source via a field effect transistor with an insulated gate electrode, the gate electrode being this. Field effect transistor is connected to this one phase of the clock. The input signals are applied while the first phase of the clock generator receives the logical signal value 0, the logical signal value 1 corresponding to the most positive value of the signal. During this first stage is precharged to the node via the IGFET, to the gate electrode of the first phase is applied. Since the parallel circuits of the field effect transistors with insulated gate electrodes are connected to the first phase of the clock generator

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the switching point independent of the logical signal values of the first and second input signals. At the end of the first phase, the circuit point discharges, when the input signals were opposite to one another, i.e. when one input signal had the logical signal value 0 and the other input signal had the logical signal value 1. This makes the odd at the switching point Signal value 1 indicating parity is generated.

In the same way, the second column contains a parallel connection of field effect transistors connected in series with an insulated gate electrode, which are connected to a second node and are connected to the first phase of the clock. The input signals are in this column for the field effect transistors, however, in such a way that the node discharges when the input signal have the same logical signal values. The logical signal value 1 thus corresponds to an even parity.

By adding more pairs of insulated gate field effect transistors for each additional input signal and means for precharging the resulting node can have as many logical inputs checked for parity as desired. For checking of a third input signal. its parity can, for example, an IGFEO? between the first node and a third node in the first column and inserting the second node into a fourth node in the second column. Bitee field effect transistors with an insulated gate electrode would have a gate input for receiving the third signal, In addition, field effect transistors with insulated gate

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Electrode can be inserted between the first and fourth and the second and third circuit points, and they could have gate electrodes to receive the negated sig- ' have the values of the third signal. That way will either the third or the fourth node is discharged so that an odd or an even parity is indicated will.

According to a further feature of the invention, an over- Carrying transport circuit provided with field effect transistors with an insulated gate electrode. The circuit includes Means for precharging the carry terminal each Bits of the arithmetic unit during a phase of the clock. The terminal is dependent on the logical signal value of the optionally unloading the result resulting from an addition or subtraction operation. When a carry transport is required, the output signal allows one to discharge between the carry terminal and the first phase of the clock generator inserted field effect transistor with isolated Gate electrode to »As the field effect transistor to discharge the carry terminal to the first phase of the clock is connected, the control signal containing the result of an arithmetic operation can be applied simultaneously with the precharge cycle. This enables maximum operating speed.

It also contains a data processing arrangement according to the invention a central unit that has a 'common external Manifold is connected to multiple storage units. Circuit devices are connected to the external collecting line, which determine the output signal it has just delivered and an input voltage signal for the collective ;:

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generate line. In the preferred embodiment, the central unit of the data processing system is on a formed individual platelets. The central unit contains a parallel arithmetic unit, a random access memory forming the data registers of the central unit, a command register and a control circuit. The functional elements the central unit are via a common parallel bus connected with each other. The operation of the central unit is based on a sequential use of the internal manifold.

According to one feature of the invention, a circuit speaks for precharging the internal collecting line and for selective unloading in response to control signals from various puncture elements of the central unit. The discharge circuit essentially forms logical OR circuits of which the number of those circuits that are on the buses Have access, changed according to design considerations can be. Any number of these OR circuits can be used in accordance with the invention.

The central unit works with a two-phase clock system. As usual, there is a slight time interval between the two phases. The Vorladungsschaltuög works during the first phase of the clock, simultaneously charging the bus and the logic circuit for the selective discharge can be set. To block the discharge of the manifold for the duration of the first phase of the Logical control devices are provided at the clock cycle. As soon as the first phase of the measure ends and is positive Value returns (for arrangements with positive logic), the busbar is dependent on the logic of the input

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Discharge signals optionally before the second phase. This The pre-charging process has the advantage of increased operating speed, since access to the manifold is extremely quick.

According to a further feature of the invention, a circuit is provided for determining the current output signal of the external bus line during the first phase and for generating a voltage signal on the bus line during the subsequent phase. The circuit contains devices for switching on circuits in the bus from a selectable data source during the first phase. This current is detected by a differential amplifier which, at the end of the first phase, sets a hold circuit according to the logic signal value of the detected current. A logic gate receives the output signal of the holding circuit and switches it during the second phase of a ÜJaktsignals. This signal is applied to an emitter follower transistor connected to the bus. The emitter resistance of the transistor generates a voltage on the bus line, \ This voltage is clocked into a selectable data source during the second phase.

Embodiments of the invention are shown in the drawing shown. Show in it:

Fig. 1 is a functional block diagram of one on one central unit attached to a single plate »which is connected to external storage systems,

Fig, Z is a functional block diagram one on one

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-H-

Plate attached central unit, which after the Invention can be used,

Pig. 3 a is a block diagram of the coupling device for the internal manifold of the central unit,

Pig. 3 b a logic diagram of the central unit, in the connections of the internal manifold with the various puncture elements of the Central unit are shown,

Pig, 4 a is a schematic circuit diagram of a dynamic Random access memory cell that can be used in the invention

Pig. 4 b the implementation of the dynamic random access memory cell by Pig. 4 a) in the form of an integrated circuit,

Pig. 5 a logic circuit diagram of a bit of the arithmetic unit the central unit according to the invention mounted on a plate,

Pig. 6 an overview of commands for the various classes of Commands issued by the central processing unit according to the invention be executed, ■

Pig. 7 is a functional block diagram of the sequence control the central unit,

Pig. 8 is a logic circuit diagram of a state time control circuit, in the sequence control circuit of the Central unit can be used,

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Fig. 9 shows a logic circuit which is all input / output circuit can be used for the central unit,

Pig. 10 is a logic diagram of the command register of FIG
Central unit according to the invention,

Fig. 11 shows the logic circuit of the instruction decoding section

the central unit,.

Pig. ' 12 is a logic diagram of the in Pig. 7 shown Cycle timer,

Pig. 13 a logic implementation of the internal control circuit of the central unit,

Pig. H the logic circuit of the state decoder for the Arithmetic operations of the arithmetic unit,

Pig. 15 is a logic diagram of the restart operation;

Pig. 16 a functional block diagram of the arithmetic unit the central unit,

Pig. Figure 17 is a logic diagram of the compute control section of the arithmetic unit,

Pig. 18 the logic circuit of the buffer register, the shift circuit and the increase logic,

Pig. 19 a logic diagram of the arithmetic unit j - "''" -

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Fig. 20 is a schematic circuit diagram of an eight-bit circuit diagram Parity precharge circuit used in conjunction with the invention

21 shows a logic circuit assigned to the arithmetic logic unit of the arithmetic unit,

22 is a logic diagram showing the arithmetic addition operation;

23 is a logic diagram showing the arithmetic subtraction operation;

Fig. 24 is a logic diagram showing the non-equivalence operation ,

Figure 25 is a schematic logic circuit illustrating the operation of the random access memory based on central unit attached to a plate,

Figure 26 is a schematic diagram of a clocked inverter used in the logic circuit of the random access memory of Fig. 25 can be used,

27 is a logic diagram to illustrate the stack hint logic;

Fig. 28 is a circuit diagram of the logic circuit that controls the refresh counter of the random access memory on a Plate attached central unit is assigned,

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Pig. 29 is a logic circuit diagram of the flip-flop circuit used in the logic of circuit 25,

Fig. 30 is a functional block diagram for illustration the operation of the coupling circuit between the central unit und.dem external memory after the Invention,

Pig. 31 is a schematic representation of the elements used in the coupling circuit of FIG. 30;

32 & 32b a representation of the multiplex connection

Creation of the external, eight-bit parallel bus for 1K bytes the external memory,

Fig. 32 ο the conventional collecting line system, which in an arrangement without multiplexing for 1K. byte of the memory is necessary

33 is a schematic block diagram of the external. Storage manifold,

Fig. 34 is a logic diagram of the external timing, Fig. 35 is a logic diagram of the external timer,

36 is a logic diagram of the external memory coupling circuit;

37 is a functional block diagram of the external

Random access or serial memory and related Control devices,

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38 is a logic diagram of the externally controlled bus timer;

Figure 39 is a logic diagram of the circuit for sampling and holding the tile selection,

Fig. 40 is a logic diagram of the input / output "circuit for external storage,

Fig. 41 is an illustration of the address register logic of the external random access memory _t

42 is a logic diagram of the renewal counter of the external random access memory;

Fig. 43 a and 43 b logic circuit diagrams of the X and Y

Address decoding logic of the external memory,

Fig. 44 shows typical clock waveforms which, together with the

arrangement according to the invention can be used, and

45 shows an embodiment of the invention which combines two central units mounted on a plate with common external storage elements.

The invention relates to a central processing unit (CPU) integrated on a single die together with external random access memories (RAM) and read-only memories (ROM). The invention is initially in its function as

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System described. The individual functional units of the central unit are then described. This part of the description contains the definition of the instruction set that can be used together with the central processing unit. To the For the purposes of explanation, the central unit is described according to its puncture in such a way that it is a logical sequence control unit, "contains an arithmetic unit and a random access memory. These functional units are connected to one another via an eight-bit parallel bus. The various logic circuits, the sequence control logic, the arithmetic unit and the internal random access memory are assigned, together with explanatory operating examples for certain exemplary embodiments in individually described. Finally, the coupling logic for connecting the central unit to the is described external storage. ,

System description;

Fig. 1 shows in block form a central unit 10, a external memory 12 and a read-only memory I4. These three units 10, 12 and Η are shared via one eight-bit parallel bus 18 connected to one another. An input / output coupler is general represented by block 16. The coupling device enables external inputs and outputs to and from the central processing unit and the storage unit 12.

The central unit 10 is manufactured on a single plate. This has the advantage that a fast execution time is made possible and that for connection with other in-

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units of the data processing system a minimum number of lines are necessary. The memory 12 can be either random access memory or serial memory. As discussed below in connection with the detailed description of Figure 37, the logic is external Memory designed to be either a random access memory or a shift register memory can be used.

The read only memory (ROM) 14 is used in the arrangement for storing fixed sub-programs or control programs used. The central unit 10 of the memory 12 and the read-only memory 14 are connected to one another and to the input / output coupling device 16 are connected to one another via a common, 8-bit parallel bus line 18. In one phase of the clock, the central unit or the memory outputs data, while the central unit and the Memories accept an input signal during the other phase of the clock.

Organization of the central unit

Fig. 2 shows a functional block diagram of the organization of the central unit. The central unit exists in principle of three blocks, namely the control unit 20, the arithmetic unit 32 and the internal access memory 40. The Control unit 20 controls the operation and synchronization of the central unit in such a way that an exchange of information between the different blocks of the central unit via a common eight-bit bus 25, Das Control unit 20 contains a control decoder 26. This control decoder has an interrupt request as input signals.

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change signal (INT REQ) and a ready signal (READY). As output signals, the control decoder 26 emits a synchronization signal SYNCH, a request signal I ¹ ETOH, a cycle signal CYCLE, an interrupt confirmation signal (INT ACE) and a memory signal MEMORIZE. A main system timer and a cycle timer 24, which enables variable instruction lengths, are connected to the control decoder 26. An instruction register 28 also provides inputs to the control decoder 26 '. The control decoder has 18 outputs which control the internal value memory, the arithmetic unit, the system coupling device and the external memory units. An input / output block 30 forms part of the tail unit 20 and is connected to the internal collecting line 25. The exact logic circuits of the various blocks of the control unit 20 are described in more detail below in connection with FIGS. 8 to 15.

The block 32 shows the arithmetic unit in general. ALU of the central processing unit CPU. The arithmetic unit contains a buffer register 54 which contains the right and left shift circuits. Block 36 generally shows an eight-bit arithmetic circuit. This arithmetic circuit can perform eight different functions, namely addition, addition with carry, subtraction, subtraction with borrowing, the negated conjunction (NAND), the non-equivalence function, the disjunction function (OR) and the comparison function, Anyone? these arithmetic operations correspond to a code P. How will be described in connection with the command set of the central processing unit contain bits 5, 4 and 3 of the command register a binary one corresponding to these arithmetic operations

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Information. For example, subtracting with borrowing corresponds to a code P of 3. In binary code this is the Number 011.

The block 38 reproduces the four calculation codes which indicate the data states of an arithmetic operation. How to can be recognized, these four flags are the carry flag (C), the zero flag, (Z), the sign flag (S) and the parity flag (P). The too? Status code (CC), which corresponds to each of these status indicators, is indicated with 0, 1, 2 or 3. For the professional it is clear that two binary data bits can be used to uniquely select one of these four identifiers. The status flag code and the arithmetic operation code P are given in Table 7 shown below.

The internal random access memory 40 (RAM) of the central processing unit CPU contains 26 registers with a capacity of eight bits each. Two of these registers are selected for the program address. These two registers 42 and 42 correspond to the low-order address bits (Pt) and the high-order address bits (Pg). Taken together, these two registers allow an absolute 16-bit addressing of a memory location in the memory. By using the 16-bit memory addressing isjj It is possible to address up to 64K bytes of data in memory. The random access memory RAM also contains data registers A, B, C, D, E, H, L and M ^1. The data register A is used as an accumulator. The data registers B, C , D and E are general-purpose registers; the data registers H and L are combined and form the storage location of the memory address, the data register M · is only used internally. Fourteen of the data registers

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Registers in the internal random access memory form one seven-level stack (STACK), which works according to the principle that the data entered last is output first will. This has the advantage that it makes calling subroutines easier.

The exact, logic circuitry of arithmetic unit 32 is shown below described in more detail in connection with FIGS. 16 to 24. The exact logic circuits of the internal Random access storage is used in conjunction with the \. Figures 25 to 29 are described.

As will be explained below in connection with the command set of the central processing unit, one of the data registers A, B, 0, D, B, H or L of the internal random access memory 40 can be selected by source or destination codes in the command. Three data bits are required to select one of the registers as a source or destination register. To select the data register D, for example, the binary code 011 (3) is required. As already mentioned, the data register M ^{f is} only used for internal operations of the central processing unit. In the arrangement described here, the coding for the number 7, that is to say the binary coding 111, is used for the reference to an external memory.

FIG. 3a shows a block diagram of the various connections to the internal bus 25 of the central unit. It can be seen that the instruction register 28, the random access memory 40, the register 44 and the Computing block 32 are connected to the manifold 25. The selection of the various registers of the direct access

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Memory 40 is shown in block 4I. The 8-bit registers of random access memory are generally of three types of registers, namely general purpose data registers A, B, C, D, E, H, L, and M ¹ , high-order 8-bit address registers (Ρ _Η ), and low-order 8-bit Register (Pj ₁ ). In other words, 16 of the 8-bit registers are used to form address storage registers. An 8-bit register for the low-value information together with the 8-bit register for the high-value information form a hardware device for the absolute addressing of a TS-bit memory address. Two of these 16 8-bit address registers are selected by an up-down counter to function as program address registers. These registers are shown in block 4I as registers P1 and Pt. The other H registers form a seven-level stack memory that works on the principle that the data entered last are output again first. Whether one of the general-purpose registers, an address register for high-value information or an address register for low-value information is selected for access to the bus 25 depends on the binary coding of the input signals U and V. Which register level is selected depends on the address register coding. For example, if both input signals U and V have the logical signal value 1 and the address register code is 010, the general-purpose register C is selected. For a further example it is assumed that the input signal U has the logical signal value 1 and the input signal V has the logical signal value 1, and that the address register coding is 001. In such a pail, a selection of the high priority address bits would be in the sixth stage

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take place. In the same way, "for an input signal U with the signal value 1 and V with the signal _{value 1 and an address register coding of 011, the address register Pj 1 would be selected} for the least significant bits. If both the input signal ü and the input signal V had the logical signal value 1, that is, if none of the data address registers of the internal random access memory were selected for operation, then a column of the memory cells of the dynamic random access memory would be automatically renewed / This is explained in more detail in connection with Pig.

FIG. 3 b shows the logic gates of the bus connections of the central unit shown in FIG. 3 a. The block 46 ″ generally designates one of the eight internal precharged bus lines which are provided with the reference symbol 25 in FIG. 3a (assuming the use of P-channel field effect transistors with an insulated gate electrode) is charged to a negative voltage by the transistor 53. During phase 2 of the cycle, the bus 46 ″ is conditionally discharged. Input signals for the bus are generated from control signals preceded by an asterisk (*). An example of such a signal is the control signal * M which the bus generates from the input / output buffer 45 of the central processing unit. The reference symbol $ "denotes signals which scan the bus and which enable data to be entered into various sections of the central processing unit. For example, a bus signal is generated by the NOR gate 47. For explanations

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For purposes of this, positive logic is used in the exemplary embodiments described below. If the signal * M has the signal value 1, a signal at the input / output block 39 is thus transmitted to the NOR gate 47 when the phase 1 of the clock assumes the signal value 0. During phase 2 of the cycle, the signal is switched through to bus 46. When the signal $ M assumes the signal value 1, the bus is scanned and its output signal is transmitted to the input / output block 39. Another section connected to the bus is the command register 28 which is operated by control signals * I and f> 1. The control signals * I-. . _K enable bits 3, 4 and 5 of the command register to be transferred to the bus when a restart command is executed. The mode of operation of the command register (I) is described in more detail below in connection with FIG.

The command register is connected to the control unit 20 which contains the various control signals which the random access memory and control the arithmetic unit, as well as generating the Sämmelschienen expressions * and $. The tail unit receives two input signals, namely the interrupt request signal (INT REQ) and the ready signal (READY). Five output signals comprise the synchronization signal SYNCH, the request signal FETCH, the cycle signal CYCLE, the Interrupt acknowledge signal (INT ACK) and the memory signal MEMORIZE. The empennage 20 produces eighteen output signals. Seven of these output signals are control signals for the random access memory, three are output signals $ Output signals, that is, sample signals and eight output signals are ^ signals, that is, generation signals.

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The logic operation of the tail unit 20 is described below in connection with FIG.

The bus is also connected to a memory register (E), one bit of which is shown at 51. A buffer register goes directly to the bus and it allows a right or left shift or it supplies an input signal to the arithmetic unit 32. The logic for performing the left shift and the right shift is generally in blocks 57A and 57B, respectively. The buffer register will be described later in connection with FIG.

An arithmetic unit 32 receives both from the buffer register 51 as well as from the bus line 46 an output signal. If there is a valid result of an arithmetic operation in the arithmetic unit, the signal * F the logical signal value 1. This signal creates the bus connection from the arithmetic unit. The way of working the arithmetic logic unit is described in more detail in connection with FIGS. 19 and 21.

The internal random access memory of the control unit also scans the collecting line. During phase, 2 of the measure the bus is scanned, and depending on the state of the two control signals U and Y to the random access memory either the registers P ^ or Ρ ™ (for the program address bits with low significance or the program address bits with high significance) ,, the multipurpose data register or a renewal process is selected. A typical random access memory storage cell is shown at 48. If one of the data registers of the direct access

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If there is no access to the memory, the random access memory is automatically activated by the control signals from the control unit 20 renewed. The * RAM signal creates the bus connection from a memory cell of the random access memory. The logic of the memory cell circuit of a typical Memory cell 48 of the random access memory is described in connection with FIGS. 4 a and 4 b. the The operation of the random access memory is described below in connection with FIG.

FIG. 5 shows the section of the arithmetic logic unit 32 provided for one bit. The arithmetic unit contains inverter circuits 59, NAND gates 60, NOR gates 62, composite gates 61, non-equivalence gates 58 and MOS transmission gates 63 which are connected to one another in such a way that eight individual arithmetic operations can be carried out in response to selected control signals. The mode of operation of the logic circuit for carrying out the arithmetic operations of addition, subtraction and antivalence are described in more detail below in connection with FIGS. 22, 23 and 24, respectively. ^x

FIG. 4 a shows a schematic circuit diagram of a random access memory cell 48 with field effect transistors with an insulated gate electrode, as described here in the case of the one described here Arrangement can be used. In operation, the write line 15 is activated, and that from a field effect transistor with insulated gate electrode (IGFET) existing circuit element 17 becomes conductive, which leads to the fact that the Information present on the input line 19 is transmitted to the capacitor 21. When the write line becomes inactive, remains the information previously transmitted to the capacitor 21

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tion for one solely from the capacitance-leakage resistance product the memory cell dependent period of time stored. This time constant is not below the On the order of 1 millisecond for conventionally manufactured field effect transistors with an insulated gate electrode under normally expected ambient conditions. The IGFET circuit element 23 becomes dependent on the state of the stored information either conductive or non-conductive. If the read line 27 is activated, this will be IGFET circuit element 29 conductive, and consequently the State of the information present in the capacitor 21 by measuring the presence or absence of a conduction path from the output line 31 to Vgg via the circuit elements 23 and 29 can be determined.

The input line 19 can be from a normal IGFET circuit element of the ratio type or the precharge / discharge type can be activated.

The output line 31 can lead to a current sensing device lead, or it can lead to the control path of an IGFEI circuit element ratio type having a discharge path in a precharge / discharge type IGFET circuit element be.

Figure 4b shows a plan view of the arrangement of a Field effect transistor with insulated gate electrode for. the circuit of Figure 4 a. The circuit elements can using the in the manufacture of field effect transistor circuits produced with an insulated gate electrode conventional photolithographic masking and etching processes will.

309815/1039

Functional organization of the central unit

The central processing unit can generally be divided into four sections, namely a data section, a Address section, a tail section and an arithmetic unit section. The tail section is shown in FIG generally represented by block 20, while the data and address portions are designated 40 «Die Data and address sections are held by data registers which are contained in the internal random access memory of the central unit. The block 32 generally designates the arithmetic unit of the central unit,

As already described above, the internal random access memory of the central processing unit contains 24 registers with a capacity of eight bits each. Seven of these registers are data registers, namely an accumulator register A, four general purpose registers B, 0, D and B, and a storage register H, L. The general purpose registers B, O ₁ D .. and E can be used as index registers or secondary accumulator registers by a subroutine definition by the programmer be used. All seven registers including the memory address registers H and L can be arithmetically combined with the accumulator. As will be explained in more detail in connection with the command set of the central unit, the desired source and the desired destination (S ₁ D) are specified by three command bits, thus one of the data registers A, B, C, D, H or L or an external storage unit to be selected. The binary codes for these various registers are given in Table V.

309815/1039

The central processing unit's address portion is used by sixteen of the eight-bit random access memory data registers educated. A marker from an up / down counter selects two of these data registers so that they can be used as a program address register or as a Program counter P are used. The remaining fourteen registers form a seven-level program address stack (STACK), which works on the principle that data entered last are output again first. The purpose of the stack memory is to provide a hardware facility that allows absolute 16-bit addressing and subroutine address storage for 64K byte memory to enable.

In addition to the data and address registers, access can also be provided from the central unit's internal bus on an instruction register (I) and a temporary storage register (R). The tail section of the central unit is based on the sequential application of the bus with eight parallel bits between the internal function modules. To make this control easier, a main system timer 22 (Pig. 2) 'designed as a status counter with four states S1, S2, S3 and S4 and a cycle timer 24- working as a cycle counter (0) with cycles 1, 2 and 3 provided. The tail unit is characterized by the fact that it has two control states, namely the wait state WAIT and has the STOP state. The wait state WAIT is set by the control input signal READY of the control decoder 26 caused. The STOP state is set by the STOP command in program mode or in interrupt mode evoked. Interrupt these two control states the normal chain of circulation of the states S1, S2, S3, S4, S1.

309815/1039

224291?

The command register, the INTERRUPT and READY inputs, the status counter and the bind cycle counter are programmable Combined control decoder 26 so that the controls are mechanized, the arithmetic unit 32, the random access memory 40, the bus 25 operate and the main system timer 22 and operating as a status counter trigger the cycle timer 24 working as a cycle counter.

Command set of the central unit

The central processing unit is designed so that it executes five separate classes of commands, namely transfer commands, arithmetic commands, jump commands, input / output commands and control commands. All commands run in one, two or three machine cycles. Each machine cycle consists of a call part PETCH and an execution part EXECUTE. Call and execution require each execution. 5 microseconds. Command word ^{format 1} is shown in Table I.

309 815/1039

(Table I.

Beiehlsklasse O ^Z 5, ¹ A h ^X 2 ¹ I ¹ O Transfer
feefeftL. 2 B.
B. 5 teOhenbefehl O P. S. O P. 4 · 1 P. a Jump command O tec GTO toe Oil

lin / output command 1

xx %

It f

0 3C 0Ox 7th 7th O a 101

309815- ^ 1039-

As can be seen, an instruction consists of eight bits

I «was called I _n . According to Table I, bits I ₇ and jL 7 O 7 o

in the first example of a transmission command to form a binary 3, they have the data value 1. The bits Ic »* a and I ~ contain the binary code of D. This relates to the determination code of one of the seven data registers in the internal random access memory 40, that is to say to the data registers A, B, C, D, E, H, L or to an external memory. Table V gives the coding required for bits I ^, I ^ and Ia to specify one of these registers. According to Table V, for example, code 001 indicates register B. Bits I ₂ , I ^ and I _{Q of} the command designate the source code of the required register.

In the case of an arithmetic instruction, the P in the column of bits I, -, I ^ and I- of the instruction refers to the code of the arithmetic operation. These three bits can be encoded to select one of eight arithmetic operations that can be performed. These codes are also shown in table T with the corresponding arithmetic operation. For example, coding relates to a subtraction operation. An example of performing a subtract operation in response; logic circuit associated with such an instruction is described below in connection with FIG. The letter X in column Ic * I ,, I ₅ means "irrelevant ¹ " · If required, these bits can be used by the programmer.

Pig »6 graphically shows a command overview of the command set that can be used in the central unit described here. From Fig. 6 it can be seen that the

3098IS / 1839

Command overview contains four quadrants. These quadrants are each characterized by "binary coding of the command bits Ig and I _7. For example, the transmission command (eDS) specified in the upper right quadrant corresponds to the command bits I ₆ and I ₇ , both of which have the binary data value 1, ie express the number 3. In the same way, the quadrant on the top left in the overview corresponds to a binary 2, which results from the command bit I ₇ , which has the data value 1, and the command bit Ig, which has the data value 0. It can be seen that each quadrant of the command overview is from one In the case of the transfer commands specified in the upper right quadrant _{, the vertical registers labeled I 0} -, _n correspond to O to 7 source registers (S), such as the data registers A, B, 0, D, E, H, L or M ^{1 of} the random access memory of the central unit. The source determination S can assume one of the values 0 to 7. The horizontal axis of the quadrant is denoted by I, -. ·, net, and it can take one of the values 0 to 7 as the destination (D) of a transmission command *. Since the source and destination of a transfer command can change between 0 and 7, the entire upper right quadrant is required for the command class of the transfer commands. In addition, a transfer command labeled 0D6 is indicated by I ₇ and Ig, both of which have the data value O, in the lower left quadrant. The D can assume one of the values 0 to 7, so that it requires a whole row of the lower left quadrant. It should be noted, however, that the source determination code has the value of a binary 6. Thus, only one eight bit unit is required for this instruction. This results, together with the eight inputs each required for the class of transfer commands

309815/1039

eight bits in the upper right quadrant of the command transfer calibrates the result occupied by the class of transfer commands 9/32 of the command overview, with 32 blocks eight bits each are shown in the command overview.

In the class of jump instructions, the expression tee in columns Ic, I ₄ and I indicates a conditional real jump. If, for example, the code cc (which is one of the indicators for carry, zero, sign or parity in the arithmetic unit section of the central unit) has a value which is equal to t, then a jump takes place. These binary codes for the corresponding condition identifier codes are also shown in Table V.

In the class of the transmission commands, these transmission commands are specified by a source code S composed of three bits and a destination code D composed of three bits; it is thus possible to carry out transfers, from register to register, from memory to register and from register to memory. The term memory naturally refers to the content of the memory location specified by the memory address register H, L. In addition to the above process, a separate command is provided for direct loading or for alphanumeric loading. This command is encoded in two bytes and executed. The first byte only gives the loading _; mood code, while the second byte forms the alphanumeric source data.

The arithmetic commands take 5/16 of those shown in FIG Command overview on; they are similar to the transmit instructions except that the three-bit destination field is a three-bit opcode field

30981 5/1 039

P is. The accumulator A is implicitly specified as a determination. The source appears in the same way as above at denotes the transfer instructions including the register, memory and direct formats. The eight opcodes are the following codes: addition (AD), addition with Carry (AO), subtraction (SU), subtraction with borrowing (SB), conjunction (ND), disjunction (OR), antivalence (XR), and Comparison (OP). In all these arithmetic operations, with the exception of the comparison, the accumulator is used with the source combined and the result replaced in the accumulator.

In addition to the above arithmetic operations, shift right commands (SRC) and shift left commands are used in separate codes (SLO) formed. The shift commands act on the accumulator and the carry identifier * and they provide a mechanism for provisionally branching certain bits of the accumulator.

The arithmetic, logic and shift commands effect the implicit updating of the four assigned to the arithmetic unit Hardware identification. These flags are used as the conditional flag by conditional jump instructions. The compare operation updates the flags as does the subtract operation.

The jump commands take 3/8 of those in Pig. 6 command overview shown. To distinguish between eight different ones Jump types use a three-bit field. Another field of the command with two bits is available for selection a specific condition label for the four hardware labels used. The jump can be conditional or unconditional. If it is conditional, it can be conditionally real or conditionally

309815/1039

to be wrong. After all, it can be a sub-program check or not a subroutine jump. For all these mentioned jumps the address is used as that of the two immediately following the jump command Bits existing literal taken. When the jump is executed, these two bytes are in the program counter entered, and the program jumps to this memory location. When a subroutine jump is carried out the previous program counter is stored in the program address stack. In addition to the above A separate code is used that enables subroutine jumps to be returned. The return can also be conditional or unconditional with the real or false condition. Naturally If the return address is the last program counter address stored in the program address stack. Since the program address stack has seven levels, nested subroutine software is an expedient, powerful and effective alternative to indirect addressing.

I / O commands occupy 1/8 of the command overview shown in FIG. The external command contains a five-bit portion "irrelevant ¹¹ " which has no significance for the internal operation of the central processing unit. It can be used by the programmer and in the structure of the external operation codes to be executed by the peripheral system by the designer of the peripheral hardware. The external command does nothing more than output the internal command and accumulator registers to external hold circuits This is used to provide an efficient control unit for communications between peripheral devices and the central processing unit and between peripheral devices and the memory

309815/103 9

eixie subgroup of the external command, with only three "Irrelevant" - shares remain. In this case the central unit loads the internal accumulator register with selected dates. In this way, the hardware allows for direct program-controlled input and Output of characters from eight bits catered for.

The control commands occupy only a small part of the command overview, but with regard to the Convenience to the operator and programmer who render them is very important. The three important ones Control commands are the stop command HALT, the restart command RESTART and the. Port setting command CONTINUE. Of these commands, only the W command requires restart Multiple codes. A three-bit "don't care" part in the restart command, the three bits with the loaded with the highest priority of the program address register. So there are actually eight restarts for eight specific ones Storage spaces in sections of 8K bytes in the entire storage system of 64K bytes. All of these control commands are available for use under normal program control. In practice, their application is in interruption mode but much more significant.

The inclusion of an interrupt command in the normal course of program execution can be achieved very easily will. First, the interrupt identifier (or more generally the interrupt peripheral device) must be the one you want Code the instruction in the eight bit data selector. Then the signal value must be increased on the interrupt line, which is a direct input of the Command control decoder is. The command control decode f

309815/1039

will then recognize the interrupt command at the end of the current command execution.

The stop command and the continue command do not cause any disruption of the execution program. The restart command however, it is the direct termination of the current program flow. It is not a subroutine call; therefore must have some desired protection of the running program in the desired recognition of interrupt commands be handled by the interrupt program to the location designated by the restart instruction code is. A simple restart program would review the current contents of all central processing unit registers and the return address of a program that you can pick up again would. After completion of the handling of the interrupt command the interrupt routine would end and return to normal program flow. There are both (fast) Hardware and (slow) software devices of the priority interruption detection can be used. In the hardware facility would use an external priority encoder to select the most significant interrupt command present. The software facility would be at the location of the restart command include a software decision tree.

Table II contains a list of the * commands used in the central unit. These are the following commands: Load commands from register to Register, memory reference load instructions, direct load instructions, Arithmetic and logic register instructions, arithmetic and logic memory reference instructions, Direct arithmetic and logic commands, shift commands, Jump commands, subroutine commands, return commands, Input / output commands, restart commands and stop commands.

309815/1039

Table III contains the arithmetic and logic mnemonics and the condition codes of the central unit.

Table IV contains the command mnemonics and registers ermnemonic of the central unit

Table V contains the command coding · of the central unit,. . ......

The truth table of the instruction set is in the table VI shown. In the truth table, a horizontal line corresponds to the time, while the, input / output or Internal cells are printed in one column. The printed expressions are listed at the beginning of the truth table. The command table shows the changes to the internal registers, a memory location of the program stack and the Calculation and logic identifiers for each type of command, the number of bytes or cycles per command are indicated by the number of the lines printed for a command. The inputs, outputs, or registers printed in the truth table are listed below. The of ' The names given above and below are the names in the tables from left to right. Pur the instruction set the following is listed:

Instruction set

Ready command Interrupt command Execute command State 1 State 2 State 3

3 09815/1039

22 * 2912

State 4

entry

Command Register Register A Register B Register C Register D Register E Register H Register L Pr ogranunadre s se transfer

zero

Sign parity

309815/1039

- 43 - ■■.

22 * 2912

Table II Machine Instructions

Load command «from register to register (49 commands): '

d ^r s (r _d ) <r- (r _g ): Load register r _fl with the content

of register r. The contents of the register

r remains unchanged. s

Load command with memory reference (15 commands):

Lr., M (r _fl ) - * - (m): Load register r-, with the content

of the memory location addressed by registers H and L. The content of the memory location m remains unchanged.

LMr (m) ^ - (r): Load the from registers H and

L addressed memory location m with the content of the register r. The contents of the register r remains unchanged.

LM, B1 (m) «- (Bi): Load the from the registers H and

L addressed memory location m with B1.

Direct load command (7 commands):

Lr _d , Bi (r _d ) «- (Bi): Load Bi into register r _d · Calculation and logic command (56 commands):

r _s (A) - * - (A) @> (r _s ): The results of the arithmetic or logical operation (S) between register A and register r are stored in register A. The status of the operation is indicated by the condition flags.

309815/103 9

Continuation to Table II

• Arithmetic and logic command with memory reference (8 commands):

gM (Α) · * - (Α) @ (m): Results of the arithmetic

or logical operation (S) between the register A and memory location m are stored in register A. The status of the operation is indicated by the condition identifier.

Arithmetic and logical direct command (8 commands):

(©, El (A) - * - (A) @ (B1): Results of the arithmetic

or logical operations @ between registers A and B1 are stored in register A. The status of the operation is indicated by the condition indicator.

Shift command (2 commands):

SLC (A _{1 + 1} ) ^ (A ₁₁ ), (A ₀ ) MA ₇ ), (CK (A ₇ ): Misc

be the content of register A one bit to the left; move A ₇ into Aq and the carry-over identifier. The other characteristics are not changed.

SRC ( ^A _m ) ^ ( ^A m + i) »(A ₇ ) - * (A ₀ ), (CH (A ₀ ): Misc

be the content of register A one bit to the right} shift A _Q to A ₇ and the carry identifier. The other characteristics are not changed.

309815/1039

Continued from Table II

Jump command (9 commands):

JMP ₁ B1, B2 (P) * fe (B2), (Bi) i It is essential to jump to the command in memory location B2, B1.

JFc, B1, B2 (P) <r (B2), (B1) when cc = 0; (P) «r (P) +3

if cc = 1: if the content of the condition identifier is 0, jump to that of B2, B1 addressed storage space? otherwise execution of the next command in the sequence.

JIPc, BI, B2 (P) * s ~ (B2), (B1) if cc = 1 | (P) «r (P) +3

if cc = Os if the content of the condition identifier is 1 ', jump to that of B2, B1. Addressed memory location otherwise execution of the next command in the sequence.

Subprogram commands (9 commands):

CAL, B1, B2 (Stack) «e (P) +3, (P) -« * (B2), (B1): Transfer

the next one. Pr.ogram address in the _...... Stack * The · new program address

. is the storage space addressed by B2, Bi.

GFc, BI, B2 ... (Stack ^ CP) ^, (P) - ^ (B2), (Bi) if cc = Oj ', ._ : ... (P) - ^ (P) _; +3. if, cc »1: Transfer the next program address to the stack memory and set the program address ₁ to B2, B1 if the condition indicator is 0, otherwise execution of the next instruction in the sequence.

309818/1039

Continuation to Table II

CTc, B1, B2 (Stack) - * (P) +3, (P) <e (B2), (B1) if cc * 1J

(P) ^ - (P) +3 if cc * O: Transfer the next program address to the stack and set the program address to B2, B1 _t if the condition indicator is 1. Otherwise execution of the next command in the sequence.

Return commands (9 commands):

RET (P) ■ «· (Stack): Return to the last one in the

Stack memory Transferred command back in memory location,

RFc (P) - * - (Stack) if cc * Oj (P) » (P) +3 if

cc se 1: Return to the last one in the storage stack transferred command back in the memory location if the condition identifier is O. Otherwise execution of the next command of the

RTc (Pj- ^ Stackiwif cd * 1 * (P) +3 if cc = O:

Return to the last instruction in memory that was stacked, if the condition indicator is 1. Otherwise execution of the next command in the sequence.

Input / output command (32 commands - 8 are inputs):

EXT (A ') ** ■ (A): The content of register A is available

available for register A ¹ . Register A ¹ remains unchanged until the next external command.

309815/1039

Addition to Table II

INP (A ') - ^ (A); (Α) - «= (data entry): The

The content of register A is available for register A ¹ . Register A ¹ remains unchanged until the next external command. The data input lines are scanned and stored in register A during the data input time.

Restart command (8 commands):

RST (P ₁₅ P ₁₄ P ₁₃ ) ^ r (I ₅ I ₄ I ₃ ): The content of the

Command register bits 5, 4 and 3 are shifted into the upper program address bits.

Stop command (1? Commands):

STOP The activity of data processing

arrangement is suspended. The contents of all registers and the contents of the memory stay unchanged.

309815/1039

Table III Arithmetic and logic mnemonics

AB * Add the content of * · to the content of register A and save the result in register A. See condition indicator. **

AC * Add the content of * and the content of the carry identifier to the content of register A and save the result in register A. See condition identifier. **

SU * Subtract the content of * from the content of the register A and save the result in register A. See condition indicator. **

SB * Subtract the content of * and the content of the carryover identifier from the content of register A and save the result in register A. See condition indicator. **

ND * Save the result of the AND operation of the contents of * with the contents of register A in register A. See condition labels. **

XR * Save the result of the non-equivalence combination of the content of * and the content of register A in register A. See condition identifier. **

OR * The result of the inclusive disjunction link the contents of * and the contents of register A are stored in register A. Please refer Condition identifier. **

309815/1039

HS

1242912

Port set to Table III

OP * The content of * is derived from the content of register A subtracted. The registers A and * remain unchanged. See condition indicator «**

* * can be a source register, a memory reference. , or the first byte of a direct arithmetic instruction be"

** The condition indicators show the status. an arithmetic or logical operation

- ■. : .. * ■; at. . - .. ■■, ■ ■■. ■; ... "- ■ - ■

Condition indicator:

G The identifier 0 is the identifier for carry or borrow. It is set if an arithmetic operation results in a carry (AD ₁ AG) or a borrow (SU, SS, GP). The carry indicator 'is reset for the logical operations (ND, XR ₁ OR). The carry flag also denotes the state of the most significant bit in register A after a right shift command and the least significant bit in register A after a left shift command.

Z The Z indicator is set if the results an arithmetic or a logical operation (AD, AC, SU, SS, ND, XR, OR, GP) .. is zero.

30981E / 1039

so

Continued au lütoelle111

The prefix S indicates the state of the seventh bit of the register Ä after one arithmetic or a logical operation. (AD, AO, SU, SB, ND »XR,

The parity indicator 3? indicates the parity of register A after an arithmetic or logic command (AD ₁ AO ₁ SU ₁ Oi ₁ AO ₁ XR (OHi CP). If register A contains an odd number of bits with data value 1, then this is Parity indicator set.

309815/1039

Table IV

Command interior technology

Symbols B1, B2

³ V ^r d

c or cc

Stack

First and second bytes of data following a command;

One of the following source registers r or destination registers r ^: A, B, G, D, E, H, I;

Specified by the content of registers H and L. Storage space;

One of the following arithmetic or logical operations: AD, AC, SU, SB, ED, XR,
OR, CP;

One of the following condition indicators:
C, Z, S, P;

Content of a storage location or a
Register;

Bit m of register A;

Program address counter; .

Seven stack memory levels of the stored program address.

Register mnemonics

Register A is used as an accumulator for arithmetic or logical commands.
Programmed data transfers to or from the data processing arrangement are made via register A.

30981 B / 1039

Sl

224 7912

Table IV continued

B, C, D, E general purpose registers;

H. L. The registers H and L are for the bytes of the memory address with the highest priority or least significant when executing a memory reference command. If registers H and L are not used for memory reference, they can be used as general purpose registers be used.

309815/1039

. 53 ·

Table V Command coding

Command code cycles

^Lr d ^r s 11 d S. Lr _d M 11 d 111 IMr ₈ 11 111 S. LM 00 111 110 ¹ ^ d 00 d 110 @ ^r B 10 P. S. @M 10 P. 111 β OQ P. 100 JMP 01 XXX 100 JTc 01 1cc 000 Ji ¹ C 01 Occ 000 CAI 01 XXX 110 CTc 01 1cc 010 CPc 01 Occ 010 RET 00 XXX 111 RTc 00 1cc 011 RFc 00 Occ 011 SLC 00 XXO 010 SRC 00 XX1 010 309815/10 39

-5 *

Continuation to Table V

command

EXT
INP

01
01

code

XXX XX1 0OX XX1 cycles

2 2

101

STOP

00
11

XXX 0OX 111 111

Source and determination codes (s and d)

000 A register 001 B register 010 C register 011 D register 100 E register 101 H register 110 L register 111 Storage data

309815/1039

Port setting to table V

Operand codes (p) (bits

OOO AB addition

0.01 AC. Addition with carry

010 SU subtraction

011 · SB subtraction with borrowing

100 KD conjunction

101 XR antivalence

1.TO, OR Inactive disjunction

111. OP comparison

Condition indicator codes (cc):

OO transfer 01 zero 10 sign 11 parity

Restart code (a):

The restart code selects the high priority address bits from ν

309815/1039

R I E ZB- EIIIGABE COMMAND RES. A REB. B RE6. C REG. D RES. E REG. H RES. L PROGRAmADRESX CZSP ONX STAIR) T T

111111

123 * 765 * 3210 765 * 3210 765 * 3210 765 * 3210 765 * 3210 765 * 3210 765 * 3210 765 * 3210 765 * 3210 5 * 321098 765 * 3210

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RES. 0 RES. E 'RE6. H REG. I. PROGRAMfWDRESSE CZSP

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00000000 00000111 01100001 10110000 110100000000ii11 0001

00000000 00000111 01100001 10110000 1101000000010000 0100

OOOOOOOO 00000111 01100001 10110000 1101000000010001 0000

OOOOOOOO 00000111 01100001 10110000 1101000000010010 0010

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r— m

I Λ

The truth table of the instruction set given in Table VI shows the mode of operation of the possible instruction classes. I ¹ A cycle is printed for each horizontal line of the truth table * Time advances in a vertical column. The commands are designated in the column on the left. For the purpose of explanation, the restart will first be described incorrectly. It is assumed that the central processing unit is in a HALT state. From Table VI is to. recognize that at time 1 at the interruption input. and a transition of the logical signal value from 0 to 1 takes place at the ready input. This transition interrupts the HALT state of the central unit. During the first cycle, the restart command is called at the input. This is shown for input bits 7 to O. With reference to Table V it should be noted that the binary code at the inputs I ^ to I _Q corresponds to the code for the restart operation. The command register also shows that the command is being transferred from the input terminals of the register during the first cycle. During the second cycle in the third line of the truth table it can be seen that the three middle bits of instruction bits 5, 4 and 3 are transferred to high-value program address bits 15, H and 13 of the program address counter. At time 4, an ADA command is executed. The input shows the command ADA. From Table V it can be seen that the command 10000000 corresponds to the operand code AD, that is, bits 4 »5 and 3 correspond to 000 each. Referring to Table I, it will be seen that the instruction class of arithmetic operations is identified as? PS. Corresponding to the number 2, bits and 6 of the command have the logical signal value 1 and 0. The

309815/1039

Source designation (bits 2,1 and O) is corresponding to the Register A (according to Table V) 000. The command is transferred to the command register. It won't be another surgery except for increasing the program counter by 1. The purpose of this command is to set the flags for carry, Update zero, sign, and parity. This is from the change in the logic signal value of the parity indicator. The identifier now reflects the status of register A.

The next instruction is a load instruction into register B from memory. Bits 2, 1 and 0 of the command (the Data source) are each 1,1,1} that is the numerical value 7, which corresponds to the memory. The command is during the first cycle time, time 5, present at the input; it is entered in the command register during this first cycle time transfer. The program counter is also increased. During the second cycle time, at the point in time 6, the data to be transferred to register B are available at the input. The command register changes to not to receive the next command. It can be seen that at time 6 the input signal to register B is transmitted.

The program address counter was not incremented because the instruction was a memory instruction that did not use the Program address, but for the memory space the Register H and L of the internal height access memory used.

The fourth command executed in the program is an input command. The command is executed during the first cycle time in

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Transfer time 7 to the command register. Register B does not change will * The identifiers are only brought up to date by a computation command or a shift command. »The fifth command, namely the return command with incorrect parity, indicates that a return command is being carried out * The command is transferred to the command register. The memory location of the program counter can be seen from the examination of the premium address register. Because the program address counter is a fixed memory location in the random access memory, the change in the address memory location is not shown. The address space remains the same until a call command is executed. This takes place, for example, at time 15. The right shift command at time 10 shows that register A is shifted to the right by one bit and that the carry flag is set by bit A ₇ after the shift.

In the way described above it is possible to follow the commands of the command set and the changed binary ones Observe data in the various registers of the central processing unit.

Sequence control:

FIG. 7 shows a functional block diagram of the sequence control logic of the central unit. Every block is open a figure is referred to in which the implementation

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logic circuits suitable for the respective puncture are precisely specified. The logic names of the central unit are described with their punctures in table VÜ.

State timer

The state timer, its logic circuit related described in greater detail in Pigur 8 below, acts as the master system timer for the system Central unit / external storage. It does all the time control in the central unit, and it controls the Coupling timer and the externally controlled timer in the external random access memory. (See Figure 35 Referenced). There are four status outputs of the stand timer s, namely S1, S2, S3 Uiid S4 * De * Status timer generates an automatic index output signal P, which the address register after execution of a command up to date «The state timer also receives input signals, the ready signal READY and the break request signal INT REQ indicating the input of an interruption command enable. In the arrangement described here, these signals are also used for the purpose of using a serial external memory or a memory with direct access to enable. This feature of the here described Arrangement is discussed in more detail below in connection with the description of Pigur 8.

As already mentioned above, a cycle includes both a call section and an execution section, each of which is characterized by having four

30 * 115/1039

S242912 kV

Has states, namely, states S1 to S4 · each State has two phases, phase 1 and phase 2. During the polling section, a command is issued from the external Retrieving memory. A logic circuit diagram of the input / output circuit (I / O) is shown generally in FIG. An instruction is executed during the execution section. The state timer also includes a programmable logic field (PLA) that does the programming different etc proportions of state time or of Allows partial cycle time for execution and retrieval by simply entering a gate mask. By application a versatile data processing arrangement can be created using this method. Am a programmable logic field is described in greater detail in U.S. Patent 3,541,543.

fr

Input / output device

The input / output device contains the coupling device for the common eight-bit external bus. During the retrieval section of an instruction cycle, the program address memory location, that is to say the memory location ■ of the desired command in the external memory, is output by the input / output coupling device of the central unit. During state 1, the low address bits Pt are output from the internal random access memory, and during state time S3 the high address bits Ptt are output. This allows sixteen bits to be output over the eight bit common bus, thereby enabling a memory system of up to 64K words to be used. During phase 2, the state '4 of the retrieval portion, the output of the command is carried out by

309815/1039

i? 242912

the external memory location addressed by the sixteen bits (FIG. 1, block 12).

Command register

During state 1 of the execution section, the Command entered into the central processing unit via the input / output device. The command is stored in the command register (Figure 10). ' The fetched instruction is executed during the four states of execution. If the Instruction requires more than one cycle, the address is either obtained from the program address counter during the next fetch section or output from registers H and L of the internal random access memory. The data will be during the end of the polling section the second or third command cycle issued from random access memory.

Command encoder

A command stored in the command register is converted to a programmable logic field, which forms the command decoder. The use of the programmable logic field in the command decoder enables the decoded commands by reprogramming the gate mask to change.

Cycle timer

The cycle timer receives inputs from the instruction decoder and the state timer. The cycle timer

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determines whether an instruction has a length of one, of two or of three cycles. The command cycles can be programmed using a programmable logic field in the cycle timer circuit can be changed.

Tail unit

The cycle timer information, the instruction decoder information and the status timer information are combined in a master unit which contains a read-only memory (ROM) which generates all the internal timing signals of the central processing unit. The outputs of this read-only memory lead either to the collecting line, to the internal direct access memory or to the arithmetic unit. The outputs marked with an asterisk (*) produce a bus signal, while the control signals marked with a ^ mark enable the bus data to be sampled. Two further outputs of the tail unit are the outputs * I,, p- and * RS. These two control signals are used when executing a restart command. During a cycle at a state time, the * RS signal discharges the bus so that all O characters can be entered into the program stack. This can be seen from FIG. 15, where the signal * RS generates a signal with the signal value 0 at the output of the NAND gate 71. This signal discharges lines 0 to 7 of the internal bus line to ground. The signal * I.,,, -Transmits the command bits I _{x A κ} to the corresponding high-quality address _{storage locations P 11} ^ - r ". The operation of the restart command and the transfer of bits 3, 4 and 5 to the address _{storage locations P 1x K} c η can be found in the truth table at time 2 of the table

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VI recognize. The $ 1 signal is used to key in the command used in the command register.

Control of random access memory

Three output signals from the control unit, namely the signals A1, A2 and A3, go to the internal random access memory. These signals define the memory location as register A, B, C, D, E, H, L or M ¹ . Two other control signals for the random access memory, namely the signals U and V, select either the previously mentioned registers, the low-order address registers P ₁ or the high-order address registers Ρ according to FIG. 2; if none of the registers of the random access memory is addressed, the signals U, V trigger a random access memory renewal circuit. Another control signal for the random access memory is the * RAM signal. This signal creates the bus when an output from the random access memory is desired. Two other control signals leading to the random access memory are the control signals PUSH and POP. These control signals operate the stack memory in the random access memory. The stack memory is described in more detail later in connection with the explanation of FIG.

State decoder

The signal OZSP and ^ W are control signals that are sent to the arithmetic unit. The CZSP signal is the signal that samples or updates the carry, zero, sign and parity flags. The outcome of this feature is the instruction bits I. _K

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combined with the arimetic output signals decoded to decide whether to execute a conditional call, return, or jump should when these commands are called.

Restart

The restart circuit enables a restart command to be carried out. This circuit causes the busbar to be discharged and enables all signals with the signal value 0 to be entered into the program stack. Then the command bits I ^, t- are enabled for input into the three bits of the register Ρ _Η with the highest priority.

Description of the input / output circuit

The input / output circuit of the central unit is in Figure 9 shown. The central processing unit has the internal eight-bit parallel bus 81 Lines 7 to 0. Inputs into the central processing unit and outputs from the central processing unit take place via the lines Aq to Αγ. The coupling device between the internal bus 81 and output lines includes a series of NAND gates 83 and FOR gates Insulated gate electrodes 8? of field effect transistors connect the output lines to corresponding logic gates connected to the internal bus 81 ,are. The system ground is denoted by the reference symbol 89. The input / output circuit works as follows: If the control signal $ M has the signal value 1, the Data sampled on internal bus 81. Be it

309815/1039

as an example, assume that the data signal on line 1 of the internal bus has the logic signal value 1. If the control signal $ M assumes the logic signal value 1, then both inputs of the NAND gate 83 A are also at the signal value 1, so that as Output signal a signal with the logical signal value 0 is generated. This logic signal value 0 at the output causes a forward bias at the transmission gate gate 87A of the field effect transistor, so that the output line A ^ is connected to ground. This transistor then delivers a current to the external line A ^, which is scanned as an indication of a signal on line 1 of the busbar. As a further example, it is assumed that a signal with the logic signal value 0 is present on line 2 of the internal bus. In this case, when the control signal $ M changes to the logic signal value 1, the input signals at the NAD gate 83B have the signal values 0 or 1. This generates an output signal with the logic signal value 1 so that the transmission gate 87B is not energized will. Thus, no current flows through the output line A ₂ , and the logic signal value 0 is displayed for the line 2 of the common line.

During phase 1 of a state immediately after the data is _{sampled on the internal bus 81, an input signal is sampled from the same line A 1} or A ₂ as in the example above If, for example, the signal * M assumes the signal value 1 in the time in which the signal Φ1 changes to the signal value 0, the signal value 1 of the signal * M becomes one of the inputs of the NAND gate 91

309815/1039

transfer. As soon as the signal Φ 1 corresponds to the logical signal

I-

assumes value 1, the output of the NAND gate 91 goes on the signal value 0 via * which is at the output of the NAND gate 91 resulting signal value 0 is generated, for example, on a the inputs of the NOR gate 85 A have the signal value 0. Depending on the signal value of the sampled on line A- Input information is sent from NOR gate 85A to signal value 0 or signal value 1 to internal bus line 1 transfer. For example, if the sampled on line A ^ Input information has the signal value O, then both input signals of the NOR gate 85A have the signal value O. This results in signal value 1 at the output, which is transferred to line 1 of the collecting line. When the input information however, the signal value 1 on line A ^ then the NOR gate 85A generates the signal value O at the output. The NOR gates 85 transmit the input information on the individual lines of the manifold 81, which are preloaded to increase the operating speed will.

Description of the command register circuit .

Pigur 10 shows the command register of the central unit. The command register is a sample and hold register, and it works like this:

To clarify the explanation, only one bit, the block 54 »of the command of the eight-bit command register described. If the control signal 1Ϊ the logical Has signal value 0, bit 7 of the bus is entered in the memory register. It is given by the combination gate which is an inverting AND-OR gate. During phase 2 of the clock, this input signal becomes

300815/1039

to the input of the inverter 63 between the transmission gates transferred for phase 1 and for phase 2. The output signal of the inverter 63 is sampled during phase 1. If the control signal $ 1 now has the signal value 1, the bit is scanned back by the combination gate via the other input of the inverting AND-OR gate. This allows the bit to rotate until a new bit is entered in the command register. In particular, this means that an input signal of the NAND gate 35 the signal value 1 when the control signal IHf assumes the signal value 0. For purposes of explanation, it is now assumed that the data signal gated on line 7 of the internal bus has the signal value 1, Since both inputs of the NAND gate 35 have the signal value 1, the output is always present of the NAND gate 35 to the signal value 1. This ensures that the output signal of the NOR gate 39 has the signal value 0, since it would only output the signal value 1 if its two input signals had the signal value 0. The signal value O at the output of the NOR gate 39 is transmitted through the transmission gate for phase 2 to the input of the inverter 63. The output signal of the Inverter 63 with the signal value 1 is transferred to the input of inverter 65 by phase 1 of the clock. This Signal with the signal value 1 is a feedback signal to the NAND gate 37. If the control signal IT now has the signal value 1 assumes, both input signals of the NAND gate s 37 to the signal value 1, so that the holding circuit is set, since the output of the NAND gate 37 assumes the signal value 1, which ensures that the output signal of NOR gate θ 39 has the signal value 0. This data signal runs until the control signal FT assumes the signal value 0 again. In the same way can be shown that a signal with the logic signal value 0 is present

309815/1039

the line 7 of the internal bus from the NAND gate 35 is sampled. In this case the output signal of the NAND gate has the signal value O. Since one of the input signals of the NAND gate 37, that is, the control signal IT, the Has signal value O, the output signal of this gate also has the signal value O. This ensures that the output signal of the NOR gate 39 has the signal value 1. This signal is transmitted through phase 2 of the clock to the input of the Negators 63 transferred. During phase 1, the Transmission gate of this negated signal / to the input of the Negators 65. The signal is also fed back to one of the inputs of the NAND gate 37. When the control signal 1Ϊ has assumed the signal value 1 again, a dem runs Signal value 0 on line 7 of the internal busbar corresponding signal in the register until a subsequent scan signal indicates that new data are to be scanned. Since the internal manifold 81 the contains negated signals of the desired data information, the output signals of the command register correspond to, for example 64, the true value of the input data. <

Description of the command decoder

The command decoder of the central unit is shown in FIG. The instruction decoder contains 2 NAND matrices 65 and 67. These matrices are formed by programmable logic fields, as they are in the? US patent mentioned above are described. The decoding process can be better understood with an example. Consider the command signal JMP. This signal is obtained when _{signals are present on the output lines T Q} , I ₆ and T _{7 of} the command register. The output signals of the

309815/1039

various commands such as JMP, HALT etc. are encoded in matrix 65. For example, requires the command HALT the combination of 2 terms iii of the matrix 65. The two terms are at the gates 73 and shown. The matrices 65 and 67 form an AND-OR matrix. As can be seen, the central unit described here has great flexibility due to the use of programmable logic fields in the instruction decoder. Simply by programming the gate mask for the programmable ones Logic fields, new functions, command sequences, etc. can be achieved.

Description of the cycle time / encoder

A cycle timer like the one in the central unit described here can be used is shown in FIG. The cycle timer contains a NAND matrix 81, the negating function of which is represented generally by the symbol 69. The output of the NAND matrix is to a Terminal of a transmission gate 83 for phase 2 connected. During phase 2 of the clock, the output signals of the NAND matrix 81 in the NAND gates 85 a to 85 f, so that control signals C1, C2A, C2B, C2C and C3 are formed that are generated during phase 1 of the Clock are output through transmission gates 87. The cycle information is transferred to the phase 1 of the clock Matrix 81 returned. The cycle information is only changed if the one described in FIG Command decoder emits a new output signal or when the status counter described in FIG. 8 has an output signal S4 EX releases.

309815/1039

- f ί -

An example is shown by cycle 1 (01). If the signals EX and S4 have the signal value 1, the NAND gate 80 outputs a Signal.with the signal value 0 from. This signal is negated by the inverter 91 to form the signal S4 EX, which has the signal value 1. When the control signal Z has the signal value 1, the cycle timer generates a control signal · G1. It can be seen that these two gates _8, that is to say the gate formed by the control line Z and the gate formed by the control signal S4 EX, are all gates in the matrix which lead to the generation of a signal with the signal value on one leading to the NAND gate 85a Are directing the matrix. This signal value 1 is inverted in the gate 69, so that the signal value is generated at the input of the NAND gate 85a, so that the signal value 1 is ensured at the output of this NAND gate. The cycle signal C1 goes to, so long as it has the signal value 1 and the signal SE to the signal EX is 1 _p that is, when the signals SE and EX not the signal values have 1.

The next change to the cycle time control takes place, when the signal S4 EX assumes the signal value 1 and a new instruction from the instruction decoder of FIG. 11 denotes Signal value 1 assumes. An example of the second cycle command is cycle signal C2A. When the cycle signal C1 has the signal value 1, so that the signal value 1 is applied to the gate 93, then the control signal Z has the signal value 0, so that the NAND gate 85a does not have a signal with the Signal value 1 is generated at the output and the signal S4 EX denotes

Signal value assumes 1; the cycle signal G2A has the Signal value 1 if the command line from the command decoder, which the control signal EXT + IrM = ΘΜ + RST (external - or load memory to r or arithmetic memory or restart)

309815/1030

is at the signal value 1. The cycle signal C2A circulates until the signal S4 EX has the signal value 1 again, since the cycle signal C2A and the signal S4 EX the signal value 1, so that the signal value 0 is applied to one input of the NAND gate 85b, which ensures that at his Output a signal with the signal value 1 is emitted. "

Description of the internal tail unit

The internal control unit of the central unit described here contains a stage of a NAND logic 95, which in phase 2 of the clock is clocked to discrete MOS NAND gates 87a to 87k. The operation of the tail unit is based on the generation of the output signal * RAM. If the Control signals S4 and EX have the signal value 1 during phase 2 of the clock, then they are passed into the NAMD gate 97d is input to generate the control signal * RAM.

Restart

Another example of the generation of a control signal by the internal control unit can be found with reference to FIG recognize the programmable logic field 99 and the control signal * RS. This is a signal that can be used to induce a Restart operation is required. In the event that the restart command signal RSIT, the cycle signal C2A » the control signal EX and the state signal S3 of the state 3 have the signal value 1, the control signal * RS takes the true one Signal value, that is, the signal value 1. This signal value is determined by a NAND gate 101 in phase 2 of the clock is input to an inverter 103 which allows the execution of the restart command. The control signal * Rö

309815/1039

is linked to phase 1 of Takta 'via a NAND gate 71. The output of this NAND gate with the signal value O is applied to the gate _r electrodes of the equipped with an insulated Oate electrode field effect transistors 105, so that these ^ ransisto "ren in 'the conducting state are .vorgespannt" Badurcn, the wires O " to 7 of the internal bus line to ground, so that all signal values O can be entered in the program address stack »The other control signal for the restart command is the signal * I _{,, κ} · If this signal has the signal value 1, lines 4» 3 , 2, 1 and O of the bus. Instruction bits 3, 4 'and 5 are carried on lines 5, 6 and 7, respectively, of the bus to be stored in the three most significant bits of the high order program address register, as above has been described in connection with the command set of the central unit.

Description of the state decoder

The state decoder for the arithmetic tags. of the arithmetic logic unit is shown in FIG. The state decoder contains a NAITD matrix 111 which is in a MND-G afcter 113 is combined with nine inputs. For example, if the command bits I ~, I, and I / have the signal value 1 the matrix 111 decodes the negated value of the carry flag. The condition output signal is with all call commands, jump commands or return commands combined to determine if the command should be executed. If parity is true and a conditional call is made, bits 3, 4 and 5 have the value 1 and the command is executed.

309815/1039

- IP - *

State timer

The status timer of the central processing unit described here is shown in Figure 8; it is used to control the main clock of the central processing unit. The one from the central unit The control signals used and their puncture are shown in Table VII.

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- f § -

ν *

Table VII Logical definitions

Names used in the central unit; Entrances:

Interrupt signal INTERRUPT;

When the interrupt line is energized (with a transition from signal value 0 to signal value 1, where the signal value 1 stands for a state), then a Interruption detected. A command consisting of one byte can be inserted and the program counter does not switch any further. A stopped central unit can * again by means of an interrupt command be designed. -

Ready signal READY;

If the ready signal is during state 3 of the polling cycle has a low * signal value (the signal value O), the data processing arrangement occurs at the end of the State 4 into a waiting state. After the ready signal returns to a high signal level (the signal level 1) there is a delay of one state.

Signals A ₇ to A _n ;

The signals A ^ to Aq are data or command input signals during a low Φ1 execution state, if the central unit is not stopped «, The data is entered with the true data value.

309815/1039

Continuation to Table VII

Outputs;

SYIICH synchronization signal:

The data processing arrangement synchronizes the memory and the external counter during every state 1, if the central processing unit is not in a hold or wait state. "The synchronization signal has the signal _{value O 1} and it occurs during state 1 of every polling or execution cycle.

FETCH request signal;

The external time control takes place through the call and execution sections of a cycle. The polling signal (four states) has the signal value 1 during the fetch section and the signal value 0 during the execution section (four states). During a waiting state, the request signal has the signal value 1. The request signal has the signal value 0 when the data processing arrangement is stopped.

Cycle signal CYCLE:

The cycle signal has a high signal level during the first cycle of each instruction. It only has while of the second or third cycle of an instruction has a low signal value. The transition occurs during the second state of the polling signal.

Memory signal MEMORIZE:

If data is to be transferred to the external memory, the memory signal has the signal value 1. The signal changes

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2242S12

during the second request state of the transmission cycle, and it remains valid for a state after execution has ended.

Interruption confirmation signal IHO? AGK The interrupt acknowledge signal (with the signal value confirms that an interrupt request has been recognized. The signal value 1 occurs a state before the synchronization of the polling signal, and it remains valid until the end of the polling signal. The interrupt acknowledgment signal occurs between four states and twenty-eight states after an interrupt request.

Signals A ~

Signals A ^ - Aq are output signals during the low φ ₂ fetch states 1, 2, 3 and the low Φ p execution state 1. The low address appears during the low Φ p fetch state 1. Data is received during the low Φ ₂ fetch state 2 and the lower Φ ₂ -Α ^ ΐΰ] ιπ2η§3ζ ^ ΐ3ηα3 1 are output. The high value address is issued during the low Φ 2 ~ polling state 3. The output is negated.

30981 5/1 039

β O

The status timer contains a ^ bit shift register with the outputs S1, S2, S3 and S4. The output signals of the shift register with the cycle information and the status information from the READY and INT (INTERRUPT) lines are combined in order to determine whether an execution or a call should take place. These output signals are converted into one of a programmable Logic field existing matrix 604 entered, which allows a change in the state operation. The break circuit toggles an interrupt input signal and synchronizes it with the state cycle information, to determine when an interruption can occur. Another input signal RDY enables the use the shift register or the use of random access memories. If the signal RDY has the signal value 1, execution takes place immediately after a request. When the RDY signal assumes the signal value 0, the central unit leaves into a wait state until the signal #DY assumes the signal value 1, with execution up to the point in time does not occur. The state timer contains also the information that the output of an interrupt acknowledge signal (INT ACK) to the coupling device contains. According to a feature of the arrangement described here, it is possible to reprogram the matrix 604 so that that the wait state at the end of execution, at the end of the Retrieval or between these two cycles.

In general, the state timer includes a schedule detector 600, one made up of a programmable logic field Matrix 604 »a memory circuit 602 for storing an interrupt request signal until it is acknowledged Storage register 606 for storing an interrupt acknowledge signal for the duration of several states and one

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Series of shift register stages.

Edge detector 600 represents a transition from the signal level O to signal value 1 of the interrupt request signal fixed, When this signal has a transition from signal value 1 to signal value O, the circuit has no effect. This can of course be changed so that the opposite happens, by changing the one-shot detector circuit. ,

The synchronization of the inquiry request signal with the timing of the central unit takes place as follows: When a transition of the interrupt control signal occurs from signal value 0 to signal value 1, the NAND gate outputs 601 an output pulse of state 1 from phase 1 to phase 1 to memory circuit 602. this is achieved by the edge detector. For example, if Φ 1 has the signal value 0, or if the interrupt signal previously had the signal value 0, then the output signal has of the inverter 608 has the signal value -1. This signal forms an input to NAND gate 601 during of phase 2 of the clock. The other input signal of the NAND gate 601 has the signal value 0, that is, the same Signal value as the input signal · of the inverter 608. In this pail, the signal at the output 610 of the NAND gate has the Signal value 1. If the interrupt request signal during phase 1 changes to the signal value 1, then the input signal of the NAND gate 601 changes, and since the signal value 1 was previously stored at the other input of the NAND gate 601, the signal at output 610 to an iTull pulse. This zero pulse is sent to the transmission gate 611 for phase 1 and to NAND gate 612

309815/1039

transmitted so that an output signal with the signal value 1 is generated at this. During phase 2 of the clock, the signal value stored on inverter 608 goes to zero
the NAND gate 601 transmitted so that its output signal returns to the signal value 1.

During the zero pulse at the output of NAND gate 601 in response to the transition of the interrupt signal from signal value 0 to signal value 1 takes the output signal of the NAND gate 612 has the signal value 1. This signal value 1 runs so long through the NAND gate 613, during each other following phases 1 and 2 of the clock back through the NAND gate 612 until the signal at the input 614 of the MND gate 613 changes to signal value 0. The signal at input 614 had previously the signal value 1.

When following the circuit, it can be seen that before the transition of the signal at input 614 to signal value 1 the output signal of the inverter 616 has the signal value 1. This sets the gate electrode 624 in the matrix 604 consisting of the programmable logic field to the signal value 1. During the next period of time that the EX (execute) signal is true, the signal on the gate electrode also goes 626 of the matrix to the signal value 1. Similarly, the gate electrode 628 of the matrix is energized, v / if the signal S4 assumes the signal value 1. If the control signal HALT has the signal value 0, the guarantees Negator 621 that the signal at the gate electrode 619 assumes the .Signalwert 1. With this combination of signals the interrupt signal is confirmed. An output signal is generated via two stages of the NAITD logic, so that the output signal of the NAND gate 632 is sent to the shift register.

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that the four status signals are the output signals S1, S2, S3 iind S4 emits. To synchronize the control when an interrupt signal is detected, the gate electrodes go 634 and 636 to the signal value 1. This allows NAND gate 638 to provide an output signal that shifts a two-bit delay to allow the random access memory to be properly addressed. During the beginning of this two-bit delay, the flag shown generally at block 606 is set. * The inverter 641 negates the signal value 1 of the output signal of the NAND gate 638 to the signal value 0, which is an input variable for NAND gate 640. The output signal of the NAND gate 640 then assumes the signal value 1, the is transmitted through the phase 1 transmission gate to NAND gate 643. The NAND gate 640 sets the interrupt detection latch circuit, so that the external time control through the data terminal on the coupling device Can accept interruption data. During the next period of this 2-bit delay, the interrupt detection latch 602 is set to the signal value 1, since the signal at the input 6i4. From the inverters 641, 645 and 647, which process the output signal of the NAND gate 638, is converted into a signal with the signal value 0. This allows the hold circuit 602 to be reset. How to can be seen, this circuit arrangement causes a complete synchronization of the interrupt request and interrupt acknowledge signals and the state operation of the central processing unit.

Table VIII shows the control cycle signal timing for the bus to operate. As an an example consider the command signal RST (restart command). The first signal P ^, which is shown so that it

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is present during state 1 of the polling sub-cycle, the control signal is to ensure that the low-order address bits are transferred from the random access memory to the internal bus for use in retrieving the restart command Control signal P ^ be present. This signal causes the bus to discharge in phase 2 of the cycle, with the bus being precharged during phase 1. Another control signal is the signal M ¹ . In the course of the partial execution cycle in state 1 during phase 1, signal M ¹ must be present so that the restart command can be transmitted from the external bus to the internal bus. If the signal is present on the internal bus, it is sampled from the command register by the control signal I. (Please refer to the description of FIG. 10). The signal I is generated in the execution subcycle in state 1 during phase 2.

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Arithmetic unit ;

This section describes the operation and logic of the Arithmetic unit 32 (Figure 2) on the plate for the central unit described. A functional block diagram of the arithmetic unit is shown in FIG. In each function block the number of the figure is given in which the exact Circuit description of the function is carried out. The arithmetic unit contains a buffer register, a section for moving the accumulator, a section to increase the program address (Figure 18), the arithmetic operand control (Figure 17), the actual computing circuit (Figure 19) and the calculation code (Figure 2.1) with the parity circuit (Figure 20). ■ '·

Rake control:

The one in Figure 1? The arithmetic control section shown works as follows: As an example, the command bits I- I. and Ic are assumed to be true, that is, with the signal value This coding corresponds to the comparison command (see Table V). To update the address register after the application of an instruction as one of the input signals of the NAND gates 88, 98 and 102, a control signal #P is generated by the state timer of the central unit (described in FIG. 8). The bits I ,, I- and I ^ of the command register are at the other inputs of these NAND gates. If the control signal fiT has the signal value 1, the signal at the output of the NAIfD gate 88 has the signal value 0, since the signals #P and Ij- both have the signal value 1. The output signal of the inverter 90 has the signal value 1. The signal value 0 of the NAND gate 83 ensures the signal value 1 at the output of the

3 0 3 8 15/1039

NAND gate 941 there the signal on at least one of its Inputs has the signal value O. The NAND gate 96 receives thus an input signal with the signal value 1. The second input signal of the NAND gate 96 is from the control signal ^ Sf formed. This control signal must have the signal value 1 so that those connected in a bootstrapping circuit »that is, in a circuit with running charging voltage Last of the NAND gate 96 continuously renews its capacity. Those skilled in the art of MQS components are known that a bootstrap load circuit to drive a large capacitance can be used at the output of a circuit element. The capacity must be continuous be filled up, otherwise the logical value will deviate from its true value.

Since both the output of NAND gate 94 and the signal - $ - v7 have the signal value 1, determines the output signal of the NAND gate 92 the signal value at the output of the gate 96 (for the present example). The NAND gate 92 receives inputs from both inverter 104 and inverter 100, each of which is input from the NAND gates 102 and 98 input signals, respectively receive. In the present example, in which the command bits I ,, I. and I, - have the signal value 1, the signals at the outputs of the NAND gates 98 and 102 the signal value 0, so that at the inverters 100 and 104 output signals can be generated with the signal value 1. These signals with the signal value 1 control the NAND gate 92 such that this generates an output signal with the signal value 0. Thus, the output of the NAND gate 96 becomes the signal level 1 controlled, so that the control signal "SU or SB or CP or W" is selected to the signal value 1, which the Execution of the comparison command effected. For the others

3098 15/1039

22 * 291? it -

it

seven arithmetic operations. ' For example, similar examples can be given, that is, by indexing the signal values of instruction bits I ~, I. _{and I 1} -, the other arithmetic operations can be selected.

The control and operation of the arithmetic unit run continuously according to the "command code present in the command register (in bits 3, 4 and 5), although an arithmetic command does not have to be executed. The only point in time at which the results of the arithmetic operation are scanned is when a control signal * 3? is present from the control decoder. This can be seen from Figure 22, where a bit of the arithmetic unit is shown. The NAND gate 86 is the control element for generating the bus line from the arithmetic unit. If the control signal * 3? has the signal value 1, the bus connection is created during phase 2 of the clock. During the signal value 0 of phase 1, the transmission gate 106 transmits the signal value 1 of the control signal *]? to the input of the NAND gate 86 has, the output signal of the NAND gate 86 remains at the signal value 1 as long as the phase 1 maintains the signal value O. When phase 1 is on passes the signal value 1, the NAND gate 86 is triggered in such a way that it emits the signal value 0 at the output. The signal value 0 at the input of the NOR gate 84, which forms part of the precharged bus, causes the transmission of the signal at the output 108 (F) of the arithmetic unit to the bus during phase 2; that is, if F _{n has} the signal value 1, the signal F ^ has the signal value 0, so that a signal with the signal value 0 is generated at the input of the NOR gate 84. Since both input signals of the NOR gate 84 now have the signal value 0, the

309 815/1039

• II *

Collective line generates an output signal with the signal value 1.

Pa the control signal * F has the signal value O during the next phase 1 »the NOR gate 84 is not triggered, "until further control signals * F occur. The times at which the control signals * F occur are in the Table VIII. It is to be seen that that Signal F only during phase 1 of states 2 and 4 in both the execution and polling subcycles appear. The retrieval sub-cycle in state S4 during phase 1 is considered as an example. For simplification of the controller, the * F signal occurs with every command at this point in time. At some times for example in cycle C2A, the results of the Arithmetic unit not desired · This is due to the vacancy in Table VIII during phase 2 of this state displayed. The result from the arithmetic unit is not saved in any register at this point in time.

Buffer register:

The intermediate storage register of the central unit is shown in FIG. It's the logic circuit for one Bit of the memory register. Other bits of the buffer register are generally in block form shown in blocks 114, 116, 118, 120, 122, 124 and 126. The internal manifold contains lines Ό to 7. The signals on these lines are negated signals, as indicated by the designation BUS.

309815/1039

TABLE VIII

EH CM I. CM Ι T- ! CvI I. CvI I. I. m I.
I. Ph cd (- ^ approx 03 ^ - ^ - Ph St. approx / -> • <4 approx approx pi pi CM I CM I I. I H Ph "^ - ^ 03 Ph " Ph CQ- CM ^ - ^ ^ - ^ H i CvJ i CM I v— I. - Ph I. approx approx pi PI approx pi O pi ro pi PH τ- I.
* ", I. CvI I I. i * I. JXJ PI rs approx v— I. I.
CM I I. i I PH CQ <A Ph <^ Ph approx approx I. I. ν- I I. St. pi ^ - ^ ^ - ^ ν- I I ν. - * I. "rf 03 « PH - ^. EH pi I. I. I. I. I.
I. H H approx H H pi approx [Cq I hi pi _- ■ . · ■ - H Ph pi < /] I. I PH Ph _ N I * hJ Ph HI I - I. H Ph hT HI pi .cm
to ω ι I ** ■ "* I τ- H <H I Ι O W. Ui pi W. W. ω ι
W.
I. I. pi Ph r— Ph Ph U «4. I. Ph Ph O Ph Ph Ph O approx I. Ph I £ ~ i W. fr} W. W. I U
I St. Ph Ph- Ph Ph Ph W. Ph PH Ph W. St. St. EH St. Hi Ph EH Ph Ph approx Ph WAI Ph ' W. Ph Ph Ph Ph Ph Ph Ph Ph W. hT [Tl Ph Hi U .approx Ph Ph St. St. St. St. Ph St. Ph Ph W. Ph Ph St. approx Ph Ph Ph Ph St. Ph Hi Ph v— t— Ph r— Τ CM Ph St. εα O O O Ο O PH St. < EH approx EH ν- CM Ph O EH St. EH Ο O \ - -J i O CM O G) Ä •H CQ rf EH -P CO ra N H •H ■ Te

309815/1039

ti

TABLE VIII (continued)

Ph ■ ι
j CM I. I.
t Ό I. I.
I. Ph ί Ph I.
I. Ph I. I. Pd 03 CQ Pd Ό ι W. '■ a Pd ς CQ - "IB ■■
ν ** m
Ph • O CM I τ- I
I. I. I. I hi I. I. * » I. I. I. « ! Ph ■ pTi ! & Pd Pd Pd Pd Pd SJ Pd pq CQ I. CM I I. ^: H I.
I. ι ω τ- I I.
I. ! i Ph I. ί a CS CO Pd (Q Pd t * "I. I. I St. ι Pd Pd CQ I.
I. ί CO I Ph Pd Oi ω CQ S ^; CM I I. ¹ H Pd H Pd I. ι cti I. m
S. « Pd PH I. ■ I. Hi M. rn τ- I I τ- Pm I. Ο Pd H Pd CM I
I. S. O S. ^: -. Ί- I.
τ- I
I. a CM H '»■■ Pd CM I.
I.
I.
I. Pd O Pd OT I. W. W. W. I. Ph Ph Ph Ph G CM I O T- I.
I.
τ- I Ph Ph f. Ph Ph I. CQ I.
I. W. W. S. W. I. Ph Ph Ph CM I dd W. W. W. W. W. I. Ph Ph Ph Ph Ph Ph Ph Ph Ph τ- I
I. St. Hi St. Hi WAI I.
j PH Ph Ph Ph Ph Ph PH Ph U CM j W. M. I.
I. Ph Ph Ph τ- I St. PH Ph St. W. Hi Ph Ph m CQ I.
I. Ph Ph Ph Ph W. Ph CM I Hi Op St. I. St. Hi Ph St. St. Ph I. P = 4 Ph Ph Ph Ph Ph Ph M. Γ * ι
CQ τ- I I.
I.
CM I Ph Pd Ph I. Hi St. Hi PQ I. Ph C \ l Ph Ph T— CM W. CM τ- I
I. ° O Hi O O St. O CQ Wi Ph Hi Ph / I PQ a- Ph / I CM 'ft * ρ1 r— O τ— / s »I ü ω M. O O ft ft CQ "φ φ ' CM Ha * -3 I. O t O O I. HI
Λ ι H Ä Q) I
<H I a fa ω ι
PQ I I. ft I. S. CQ Hi H Ό S. (O H
■ H 2 (υ
EH

309815/1039

The toggle storage register works as follows: When the control signal $ R assumes the signal value 1, the composite gate 110, which contains NAND gates 110a, 110b and NOR gate 110c, is triggered via the input line O of the bus. The output signal is stored at the output node of the composite gate 110 until the following phase .1 of the lact signal. During phase 1, it is transmitted via the inverter 112. The output of the Ne-. gators 112 becomes NAND gate! 10b during phase 2. transmitted back when the control signal $ R now has the signal value O. If the control signal $ R has the signal value 0, then both input signals of the NAND gate 110b have the signal value 1, so that the signal value is generated at its output. This signal value 0 is negated in the inverter 112 and fed back. This transfer is continued until the control signal $ R assumes the signal value again. The inverter 113 negates the bus signal of the internal bus 25 so that a signal having the true signal value is applied to the composite gate 110.

The buffer register is also used for right shift and shift left commands and also used for normal operations. This is done under the control by the control signals * R, * RGT and * LP! D. When a right shift is desired, the data signal on the internal collective initiation line is shifted to line 1. After this the control signal * RGT has assumed the ^ signal value 1, the shift follows during phase 2 of the clock as follows: The data signal on line 0 of the bus is shifted to line 1 by transferring the logic signal value at the output of the inverter 112 to line 1 of the internal

309 815/1039

Busbar is given when the control signal of the Gate 130 has the signal value 0. For example, if there is a true on line 0 of the internal manifold Signal were present, it would be reproduced there with the signal value 0, since the bus 25 is negated. The signal value 1 would appear at the output of the inverter 110, which would correspond to the real data value. An input signal from gate 130 with the signal value 0 is thus present at the input of NOR gate 134a and an input from inverter 112 so that an output on line 1 of the negated bus with the signal value 0 is generated, which causes a right shift.

In the same way, if a left shift is required, an input signal * LFT with the signal value 1 would be a Cause output at gate 132 that would be applied to one of the inputs of NOR gate 134b. The other The input to NOR gate 134b would be the output of inverter 112. The output of NOR gate 134b is connected to line 7 of the internal manifold. With a left shift, the signal is on the line thus shifted to line 7.

If normal operation is desired, the input signal * R, which changes to signal value 1, generates an output signal of gate 128 which is applied to NOR gate 134c. This gate carries the data signal to the • Line O back to line O.

The circuit for increasing the program address is also shown in FIG. The signal to achieve the pro

309815/1039

Increasing the gramme address is the control signal # P. As above has already been mentioned, this signal is provided by the state timer generated, which is described in connection with Figure 8 ■ has been. If the control signal - ^ P the signal value 1 has the output signal of the ifOR gate 136 the signal value O, the output signals of the NAND gates 138, 14Q, 142, 144 »146, H8 and I50 have the signal value 1, since the control signal ^ P from the inverter 139 is negated. This ensures that the complement of the sig- - ■ nalwerts 1 is added by the computing circuit. This is done because the inputs to the computing circuit that Gates I36 through 150, are inverted inputs. The increase takes place during the partial polling cycle in state 1 and during the partial polling cycle in state 3. The increased output signal appears during states S2 and S4 of the partial polling cycle.

Arithmetic circuit:

In Figure 19, a bit of the computing circuit is in the form of a logic circuit 97a generally shown. The others seven bits of the computing circuit are shown in the form of blocks 6? b to 67i. The arithmetic circuit contains negators 59, composite gate 61, NAND gate 60, NOR gate 62, inverting exclusive OR gate 58 and transmission gates 63. These logic gates are interconnected in such a way that, in response to a preselected code, the Command bits I, -, I. and I, eight individual arithmetic operations carried out. The mode of operation of the logic circuit during the execution of an addition instruction is shown in FIG. The logic circuitry assigned to the subtraction command and the non-equivalence command

30981S / 1039

Connections are shown in Figures 23 and 24, respectively.

A description of a bit of the logic circuit of the arithmetic unit when an addition instruction is carried out is given with reference to FIG. If an addition command is desired, the control signal 152 has the signal value 0. This signal is labeled ^{»SU + SB + CP + W M.} It will be recalled that this signal is generated by the control unit of the arithmetic unit, which was described above with reference to FIG. It can be seen from FIG. T7 that if the command bits let I. and I ^ each have the data value 0, which corresponds to the code corresponding to the addition (according to Table V), the output signal of the NAND gate 96 has the signal value 0 Has. The control signal 152 thus has the signal value 0 when an addition instruction is desired. In the same way, the negated control signal 152, designated 154 in FIG. 28, has the signal value 1.

The signal 154 is applied to the OR gate 155a and to the inverter 73a. The output of the inverter 73a is connected to an input of the OR gate 155b. The input signal T ^ originating from the buffer register of FIG. 18 is applied directly to the other input of the OR-GATE 155b. The signal 3ζ is negated in the inverter 73b, so that the true signal X is generated, which is applied to the other input of the OR gate 155a and to one input of the negating antivalence gate 75. The signal value 1 of the control signal 154, that is to say the signal SU + SB + OP enables the computing circuit to operate. The output of NAND gate 74

309815/1039

- _f 4-

is the signal X _n . It is assumed, for example, that the signal X from the toggle storage register II4 of FIG. 18 has the signal value 1. In this EaIl, the input signals of the OR gate 155b have the signal value 0 when the control signal 154 changes to the signal value 1 from the inverter 73a and the signal X _n also has the signal value O. This produces a signal with the at the output of the OR gate 155b Signal value O, which is an input signal for the NAND gate 74. In addition, an input signal of the OR gate 155a has the signal value 1 corresponding to the control signal 154. The other input signal of the OR gate 155a has the signal value 1 corresponding to the true value of the signal X. This distorted a value at the output of the OR gate 155a Signal with the signal value 1, which is also an input signal for the NAND gate 74. In this way, input signals with the signal values 0 and 1 are applied to the NAND gate 74, so that it emits a signal at the output with the signal value 1, which in turn is the signal value assumed for the signal X ·. In the same way it can be shown that for the "Pail" that the signal X has the signal value 0, the signal value 0 is generated at the output of the NAND gate 74.

The negating non-equivalence gate 75 combines the signals X _n and Y _n in a negated non-equivalence function. One input to the gate 75 is the signal X taken from the output of the inverter 73b, and the other input is the true signal Ϊ. The output of the gate 75 is denoted by X Θ Y. This output is part of the sum and carry of sum X and carry C. Let us first consider the carryover. The output signal of the gate 70 is the sum of the signals X and Y formed by the NAND operation. This output signal

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is as X. Y _n shown. A carry signal must be generated in these signals X and Y, which have a signal value of 1. This is achieved because the signal value 1 at the inputs of the NAND gate 70 causes an output signal with the signal value 0, which actuates the transmission gate 158 and generates a carry signal C, since the phase of the clock normally has the signal value 1. If the carry signal is not generated, then a carry signal can be generated by the negated value of the non-equivalence comparison. linkage of the signals' X _n or Y _n transmitted, which is shown at the output of the negating non-equivalence gate 75. This occurs because the output signal X _n Θ Y _{n is} transmitted via gate 176 and gate 160. The carry signal is transmitted from node 92 via the gate to the next bit C _n. The input signal to gate 82 is either the signal C _n -1 or a signal derived from the NAND operation of X _n -I and Y _n -I.

The sum P _n results from P _n = X _n Θ ^γ _η ^{+ σ} _η _ι » ^σ _η ^{β X} n ^#Y ii ^{+ C} n"" ¹ (X _n Θ Y _n ). The sum P _n is generated by the inverting non-equivalence gate 78, and it results from the _{non-equivalence link of the carry signal C n} -J and the non-equivalence link of X or Y. The sum expression at the output of the gate 78 generates the collective connection if a signal * F appears at the NAND gate 86 in this time segment.

FIG. 23 shows the mode of operation of the arithmetic logic unit when performing a subtraction; As can be seen from the sum expression P _n = X _n © Y _n © C _n-1 , the difference for the subtraction is the same as for the addition. The only difference in the way the two switchgears work

309815/1039

-M- 2242972

St.

"is that the input signal X to the carry equation is negated. This can be seen at the output of the NAND gate 70, where the output signal is shown as Y ₁₁ .X ^. Otherwise, the operation of the subtraction logic is the same as the operation of the addition logic which has been described in connection with FIG.

The mode of operation of an exclusive equivalence command is shown in FIG. In this example, the sum Έ results from XO, Y. The signal XR must have the signal value 1 for a non-equivalence operation. This signal is generated when the command bits I ₅ , I, and I ^ have the fourth 1, 0 and 1, respectively. (See Table V). It can be seen from FIG. 17 that such a coding of the command bits I ₇ . Signal ND + XR is applied to transmission gate I64. This signal has the signal value O when the signal "ND + XR-tW" has the signal value T. The transmission gate 164 is activated by the signal 162 in such a way that the signal value 1 is transmitted to the input of the gate 168. The signal 166 is the negated signal of the signal formed from the non-equivalence operation of the two expressions X _n and Y _n . The negated non-equivalence signal is linked to the signal present at the input of the gate with the signal value 1. The signal at the output of the gate 168 is the signal formed from the non-equivalence combination of the expressions X and Y. This output signal is switched to the bus when the control signal * F at the NAND gate 86 has the signal value 1.

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38

In the same way can the other arithmetic operations assigned logic can be tracked by the logic circuit of the arithmetic unit.

Description of the parity circuit;

A parity circuit with pre-charging offers the advantage of an increased operating speed. This circuit is described in connection with FIG. The parity circuit contains precharged field effect transistors 174, which have an insulated gate electrode, and signals designated by Φ 1 are present at their gate electrodes. The input signals from the bus are labeled F and F *. For the eight-bit parity circuit of FIG. 20 there are eight signals F, namely the signals Fq to Fy and eight signals Ί?, Namely the signals F ″ _Q to ϊγ. These input signals are optionally to the gate electrodes of interconnected field effect transistors with an insulated gate electrode in order to generate output signals for the odd parity and for the even parity.

The parity circuit with precharge works as follows: During phase 1 of the clock, the nodes are charged to a reference voltage V ^ -p. During the high portion of the clock signal, that is, when the field effect transistors 174 are blocked, the node 170 is conditionally discharged as a function of the input signals F and F applied to the parity circuit. For example, the node 170a is discharged when the two signals F * .j and F _Q or the two signals F ₁ and F * _{Q have} the signal value 0. The opposite behavior applies to node 170b, that is to say that this node

309815/1039

-W- 22-2912

33

is discharged when the "two input signals Ej and E _Q or the" two input signals F-] and F _{Q have} the signal value 0. Thus, the functions of the input signals. at point 178 with Fq.Ij, at point 180 with Ej.Fq, at point 182 with EJ .E _Q and at point 184 with E ₁ . E _Q can be expressed. The punctures at points 178 and 180 are combined at circuit point 170a in such a way that the non-equivalence function Eq $ E ₁ results. Similarly, the functions at points 182 and 184 on _; Circuit point 170b combined in such a way that the function \ Fq © EJ results. In other words, the node 170a is only discharged when the signals F _Q and F ^ have opposite logical signal values. If both input signals have the signal values 1 or the signal values 0, the node is not discharged. The opposite behavior in each case applies to node 170b, that is to say that this node does not discharge when signals Eq and Ej have opposite signal values. The parity results from the non-equivalence link of all bits whose parity is to be checked. The circuit can be expanded to as many bits as desired. Parity is the non-equivalence expression. The negated value of the non-equivalence link is called parity.

Arithmetic symbols:

The arithmetic indicators transfer (o), zero (Z), The sign (S) and parity (P) will now be described in connection with FIG. The sign indicator gives indicates the state of bit 7 of an arithmetic sum. · If

309815/1039

bit 7 has the value 1, the sign is true. If, on the other hand, bit 7 has the value 0, then it is the sign not correct. The operating principle is as follows: First, the bit 7 with the value 1 is assumed as an example. Be it notes that the bus 25 is negated. Thus the signal value is 1 for the bit. 7 on line 7 as a signal the signal value 0 is present. This signal value O is negated in the inverter 700, so that a true data bit signal is generated will. This signal value 1 is transmitted in phase 2 of the clock through the transmission gate 701 so that it is an input signal for the AND gate 702 forms. The other input to AND gate 702 is control signal ^ CZSP. if If this control signal assumes the signal value 1, the output signal of the AND gate 702 changes to the signal value 1. Through this it is ensured that the output signal of the NOR gate has the signal value 0. In the following phase 1 of the clock the logic signal value 0 is negated by the inverter 708, so that the output signal is a signal with the true signal value 1 of the algebraic sign is created. This signal value 1 is via the transmission gate 709 in phase 2 of the clock retransmitted to form an input to AND gate 704. If the control signal ^ CZSP the signal value Assumes 0, the other input signal of AND gate 704 has the signal value 1. This ensures that the signal value 1 of the number sign rotates until the line 7 of the bus bus is scanned again. Likewise, if the data signal on line 7 of the bus has the true signal value 0, then it is the negated one Collective line to the negated signal with the signal value 1. This signal value 1 is negated in the negator 700, so that a signal with the signal value 0 arises at the output of the inverter 700. This signal with the signal value 0 becomes

309815/1039

is transmitted to an input of AND gate 702 via transmission gate 701 during phase 2 of the clock. An input signal with the signal value 0 at the AND gate ensures that the output signal of the AND gate 702 also has the signal value 0. When the control signal ^ CZSP assumes the signal value 1 and this control signal is applied to one of the inputs of the AND gate 704, becomes a signal at the output guaranteed with the signal value 0. Thus, both input signals of the NOR gate 705 have the signal value 0, so that an output signal with the signal value 1 is generated will. During phase 1, this signal has the signal value 1 via the transmission gate to the inverter 708 which has the sign identifier as the output signal with the signal value 0, which corresponds to the signal value of bit 7 of the bus.

The zero indicator indicates that all input signals of the arithmetic unit have the signal value 0, i.e. bits 0 to 7 have the value 0. Pause the bits O to 7 have the signal values 0, the signal values 1- are on the corresponding lines, since the bus 25 negates is. For this reason, the NAND gate 710 on his Output generate a signal with the signal value 0. This signal value 0 is negated in the inverter 712, so as an input signal a signal with the signal value T is generated for the AND circuit 714. The other input signal to the AND gate 7H also has the signal value 1 when the control signal ^ GZSP is true. Thus, the output signal of the AND gate 714 has the signal value 1, which ensures that the output signal of the NOR gate 716 has the signal value 0 Has. During phase 1 of the clock, the output signal is

309815/1039

of the NOR gate 716 with the signal value T) from the inverter 718 negated so that the zero flag has the signal value 1. If any of bits 0 through 7 of the bus is the Has the signal value 1 and not the signal value O, then that has The rise signal of the NAHD gate 710 has the signal value 1, and the zero flag has the signal value 0.

The parity indicator indicates that the eight-bit output signal of the arithmetic unit has an odd number Number of bits with the signal value 1 is present. The details of the parity circuit itself have been related described with FIG. 20. The logic circuit for generating the parity output signal (P) as a function of the the control signal ^ CZSP assumes the signal value 1 the circuit described in connection with the sign and the zero mark.

The carryover identifier is brought up to date, if a carry occurs on bit 7 of the arithmetic unit. The carry flag is also used for a right shift command or updated on a shift left command. The other characteristics are not affected. A left shift operation shows that. least significant bit of the eight bit Output signal after the shift. A shift right operation indicates the most significant bit of the eight-bit output signal. For example the control signal ^ JpSLC has the negated value of the Control signal * LFT that controls the left shift command. The way this signal works has been discussed in "with Figure 18 described. When the * LFT signal assumes the signal value, the shift left command is thereby generated.

309815/1039

The control signal SLC thus has the signal value O. This signal value O reaches the input of the NOR gate 722. As can be seen, the other input of the NOR gate 722 samples the least significant bit, the bit O, the
Collector line 25 from. If this bit has the signal value 1
it is present on line 7 of the bus as a signal value O, since the bus negates. The signal value 0 enables the NOR gate 722 to be off. output signal with the signal value 1. This output signal is used by OR gate 724 to provide a carry signal having a signal value of one. It can also be seen that the ITOR gate 726 scans the bit with the highest significance, that is, bit 7 of the bus, for a right shift command.

The carry-over indicator is also set if
a carry occurs on bit 7 in the arithmetic unit. In this case, the signal value 1 is applied to the input of the inverter 728. This inverter is connected to an input of the NOR gate 730 during phase 1 of the clock pulse, at which the signal value O is generated. The output signal of the · NOR gate 730 has the signal value 1 if another input signal has the signal value 0. From FIG. 17 it can be seen that the other input signal of the NOR gate 730 has the signal value 0 if the command bits "I-, L. And I. have the coding 110,010, 100 or 111,
these codings correspond to the arithmetic operations OR, SU, ND and CP. The signal value 1 at the output of the NOR gate 730 is negated in the inverter 732 so that the signal value 0 is generated for an input of the NOR gate 734. The negated signal value of the control signal ^ CZSP is at the other input of the NOR gate 734. Thus, the

309815/1039

When this control signal changes to signal value 1, its negated signal value, signal value O, is applied to NOR gate 734, so that this generates an output signal with signal value 1. This signal value 1 is sampled by the OR gate 724 so that a carry flag with the signal value 1 is generated. This signal is applied to the control section of the arithmetic logic unit shown in FIG. 17 so that the signal Cj ^ is generated. It can be seen that the signal Cj _n has the signal value 0 when the carry identifier has the signal value 1, the command bit I- has the signal value 1 and the command bit I ₁ - has the signal value O. The signal "cZZ" is applied as an input signal to the arithmetic and logic unit described in connection with FIG.

The status of the carry identifier is sent back to a converter by the NAND gate 736 in the following case: For purposes of explanation it is assumed that the carry identifier has the signal value 1. The output of the NOR gate 734 sends this signal value 1 back into one cycle if its two input signals have the signal value 0. One of its input signals is formed from the negated output signal of the OR gate 724. The output of the OR gate 724 has the signal value 1 when the carry flag has the signal value 1, so that its negated V / ert is the required signal value 0. The other input signal with the signal value 0 for the NOR gate 734 is formed by the NAND gate 736. The output signal of the NAND gate 736 has the signal value 0 when the signal values 1 are present at its inputs. One of its input signals is the negated control signal £ CZSP, if this control signal has the signal value O, that is, if the status of the identifier has not been updated.

309815/1039

is desired, then its negated signal having the signal value 1 is one of the input signals of the NAND gate 736. At the other two inputs of the NAND gate 736 are the signals ^ SLC and ^ SRC, which the left shift "or. Are signals corresponding to the shift right command. If no shifts are desired, have these signals have the signal values 1 because they are "with respect to the Shift commands characterizing control signals are negated. -If it is not desired, the states of the To bring license plates up to date, and if ' No shift commands are to be executed, then the NAND gate 736 outputs a signal with the signal value 0 from which the recirculation of the state of the carry flag allows.

Central unit random access memory

The internal random access memory of the central unit is shown in FIG. The random access memory contains 192 bits of data storage organized in 24 eight-bit registers are. Eight of these registers are the address registers (Pt) for the low-order address part, eight registers are the address registers (Ρττ) for the The high priority address portion and eight registers form general purpose storage registers, seven of which are general are available while one is used internally only will. The sixteen used for the program address Registers P ^ and P ^ enable 16-bit addressing. Only one program address register is used at a time and the other seven are used for a stack subroutine call operation be used.

309815/1039

224791?

Referring to Figure 25, there is shown a portion of random access memory at 200 which represents one bit of each of the three types of registers, namely the general purpose registers (A, B, C, D, E, H, L and M ¹ ) »the high level address registers P _H and the low-order address registers P ,. There are eight sections which are identical to block 200. The random access memory operates as follows: The random access memory control signals TJ and V, shown generally at 202, are encoded to _{select either the low order address register Py, the high order address register P H} , the general purpose register or a refresh counter. If, for example, both control signals U and V have the signal value 1, the transmission gates 201 transmit the signal value 1 to the inputs of the NAND gate 224 during phase 1 of the clock, the output signal of the NAND gate 224 has the signal value 0. This output signal is in Negator 226 negated to the signal value 1. This signal value 1 arrives at the input of the negating buffer 230 and at the input of the inverter 228. An output signal with the signal value 0 from the inverter 228 arrives at the gate electrode of the MOS components 216, so that these circuit elements are enabled to perform the address line selection as described below.

The output of inverter 226 becomes during phase 2 of the clock is switched through to the input of the inverter 230a. The output signal of this inverter has the signal value 0. This signal value 0 is passed on to the input of the inverter 23Ob during phase 1 of the clock pulse. It's closed recognize that in this way the output of inverter 226 is subjected to a two-fold delay.

309815/103 9

'224291? 40?

The input signal of the inverter with the signal value O 23 (Jb is connected to an input of the composite logic circuit 220 and in particular to an input of the NOR gate 220a created. The other input to NOR gate 220a is line 221 of the bus line.

The 0 signal on line 234, which is the input to inverter 230b, carries the data signal on line 221 of the bus to line 236, which is the output of OR gate 220b. This line 236 causes a column of the internal memory cells of the random access memory to be accessed. ¥ _e nn thus the signal value of 0 on the line 234 is present, it is possible to write data into the general-purpose register, represented by the signal value 1 v / ei send control signals TJ and Y are selected. With other selection values of the control signals U and V, the high-value address register Pjt or the low-value address register IV would of course have been addressed.

It can be seen that the. the negated line 221 of the Data present on the bus can be reproduced on the line 236. For example, assume that on the line 221 a true signal with the signal value 1 is present. Since the manifold is negated, it's up to the Bus with the signal value 0. This signal value 0 becomes with the signal value 0 on the line £ 34 from the NOR gate 220a linked in such a way that a signal with the signal value 1 arises at the output of this NOR gate. This output signal with the signal value 1 is received by the OR gate 22Ob so that it generates the signal value 1 on the line 236, which the Storage of the signal value enables.

309815/1039

For explanation, it is assumed that it is desired to store information in the internal memory cell 232 of the random access memory, which is bit D ^ of register D. The index “i” can of course be any of the bits 0 to 7 in the present example. In response to the signal value O on line 234, the data signal on line 221 is transmitted to line 236. This line has access to all registers A, B, C, D, E, H, L and M ¹ . To select the memory cell 232 for data storage, the input signals on the lines. A ^, Ap and A, which have signal values 1, 1 and O, respectively. This code corresponds, for example, to the source and destination codes for selecting register D, as set out in Table V; for the determination of the register D the command bits 2, 1 and O must be 0, 1 and 1 accordingly. This coding effects the selection of the register D as follows: The output signal of the inverter 228 has the signal value 0, which triggers the transmission gates 216. The signal values of the signals A 1, A 1 and A 1 are thus applied to the inverters 212a, 212b and 212c, respectively, so that corresponding output signals with the data values 0, 0 and 1 are generated. The signals A-, A "and A, or the complementary values of these signals are applied as input signals to the NAND gates 215, respectively. It can be seen that if the signals A ^, A ₂ and A have the signal values 1, 1 and 0, input signals which all have the signal value 1 are only present at the NAND gate 215a. The output signal of this NAND gate with the signal value 0 is negated to the signal value 1 by the inverter 217. In phase 1 of the clock pulse, this signal value 1 is transferred to the input of the ^{inverters 219, labeled Φ 1 'and Φ2 1} , which have the memory cell 232

309815/10 39

are coupled. The output of the inverter φ 1 'forms the read line 244, and the output of the hegator Φ 2 ¹ forms the visual line 242. As will be explained later in connection with Eigur 26, the inverters Φ 1' and Φ 2 'are clocked ITegators which can advantageously be used for addressing the memory cells.

During phase 2, the write line of the memory cell is activated. The _f read line of the memory cell is shown at 244, while the output line is shown at 248. A detailed description of the mode of operation of the dynamic memory cell 232 of the random access memory is given in FIG. Description of Figures 4a and 4b. During phase 1 of the clock, if the signal on line 234 is high, indicating the selection of one of the registers, the register output is selected via composite gate 260 to node 252. The NAND gate 254 is activated when the signal * RAM changes to the signal value 1, 'and the output signal is transmitted to the bus line. During phase 2, information may be written to memory cell 232 from the bus via line 236.

As an example it is assumed that the signal value O is stored in the memory cell and that this value has been read shall be. The line 244 is thus biased to the signal value 0 during phase 1, and that in FIG The signal value O stored in the memory cell is transferred to the outgoing line 248 transferred. This signal with the signal value O forms an input signal of the NOR gate 250a. The other input of the NOR gate 250a is formed by the line 234. The signal applied to this line

309 815/103 9

nal also has the signal value O. This results in am Output of the NOR gate 250a a signal with the signal value 1 * This signal value 1 is via the OR gate 25Ob to one of the inputs of NOR gate 254 during phase 1. This ensures that the The output signal of the NOR gate 254 has the signal value Q. This signal value O is on line 221 of the collecting line saved. Likewise, the output of the NOR gate 250a is at (Jem signal value 0 if in the memory cell 232 the signal value 1 was stored. Thus the output signal of the OR gate 250b would also have the signal value 0, which forms an input to NOR gate 254. In response to the transition of the * RAM signal to the signal value 1, the other input to NOR gate 254 takes the Signal value O on. This allows a signal to be sent to the bus with the signal value 1.

The high-value address register Ptj and the low-value address register Pt could also pass through in the same way a combination ul? or UV of the control signals U and V are addressed. -

Other puncture sections of random access memory include a stack indicator, a refresh counter, and registers P- ^ or Pj ₁ for the program address. The stack indicator always indicates a space on the stack. This memory location is the current program address. If the input signals U and V of the random access memory are coded as 01 or 10, a signal with the signal value 1 is produced at the output of the NAND gate 255. This signal value 1 is negated in the inverter 257, and it triggers the transmission gates 256. These transmission gates he-

309815 / 103a

possible output signals from the stack indicator S1, S2 and S3. These output signals are each sent to an inverter en 212a, 212b and 212c. Depending on the Signal values of the signals S1, S2 and S3 becomes one of the stages, that is to say, lines, in the registers P ^ or P- ^ of random access memory selected. Whether the register PjT or the register P ^. is selected depends depends on whether the coding of signals U and V was 10 or 01. If a call command or a return command is executed, the stack indicator address is changed by changing the count in the stack indicator.

The logic circuit of the stack indicator is shown in FIG 27 shown. The stack indicator contains an up / down counter and it has two POP inputs and PUSH. Whenever the input signal POP occurs the counter is increased by one count. An input signal PUSH lowers the count by one. The counter saves the new memory location of the program address until another return? or call command is performed. Call commands cause the Counting counter in one direction, while return commands cause the counter to count in the other direction. From this explanation it can be seen that the use of the stack indicator provides a useful massive and advantageous option for addressing is created by subroutines.

The operation of the stack indicator can be understood by referring to the truth table given in Table IX recognize better. The following inputs, outputs or registers are stored in the truth table

309815/1039

- 411.

prints if the names given here from top to bottom can be viewed from left to right in the table:

Ready

Interruption input

Command register Register A

Address level O Address level 1 Address level 3 Address level 6 address level 7 transmitted

zero

sign

parity

In Table IX, the first two commands are commands RST and ADA. These commands cause the program address value to be set to the value O and the carryover indicator to be set, so that the state of register A is reproduced. The next 'command is a jump with true' value O (JTZ). This command is transmitted during the period 5, since the zero flag is true. During the next two time segments, the address bits are initially with then entered the high priority address bits. These bits are in the program address level O shown during period 7. While A jump with true carry (JTC) is carried out after duration 8. Because the transfer signal is in the wrong state this command will not be executed. The next command is a true parity (CTP) call. This command is also not executed because the parity signal is not

309815/1039

STACK STORAGE STAGES

CN
YT

0
1 11
11 11111111
00000000 11111111
00000000 2RST
3 11
11 00110101
10000000 00110101
00110101 4ADA 11 10000000 10000000 CO 5 JTZ
6th
7th 11
11
11 01101000
11111111
10101000 01101000
11101000
01101000 39815/10 8 JTC
9
10
11 CTP
12th
13th 11
11
11
11
11
11 01100000
11111111
00001101
01111010
00110010
11101111 01100000
01100000
01100000
01111010
01111010
01111010 % **
CO 14 CAL
15th
16 11
11
11 11101110
01111110.
01001111 01101110
01101110
01101110 17 JHP
18th
19th 11
11
11 01010100
10100011
1100Ö111 01010100
01010100
01010100 20 CFC
21
22nd 11
11
11 01000010
01010110
11111101 01010010
01000010
01000010 23 CTZ
24
25th 11
11
11 01101010
11010111
00011111 01101010
0110101Q
01101010

INPUT COMMAND REG. A ADDRESS LEVEL 0 ADDRESS LEVEL 1 ADDRESS LEVEL 3 ADDRESS LEVEL 6 ADDRESS LEVEL 7 CZSP

111111 111111 111111 111111 111111

76543210 76543210 76543210 5432109876543210 5432109876543210 5432109876543210 5432109876543210 5432109876543210

11111111 1111111111111111 1111111111111111 1111111111111111 1111111111111111 111111111111.1111 1111

OOOOOQOO OOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOO 1101

00000000 00000000

oooooooooooooooo

1100000000000000

oooooooooooooooo oooooooooooooooo

oooooooooooooooo oooooooooooooooo oooooooooooooooo oooooooooooooooo

OOOOOOOOOOOOOOOO 1101 OOOOOOOOOOOOOOOO 1101

00000000 1100000000000001 OOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOO 0100

00000000 00000000 00000000

00000000 00000000 OQOOOOOO

00000000 00000000 00000000

00000000 00000000 00000000

00000000 00000000 OOOQOOQO

00000000 00000000 00000000

00000000 00000000 OQOOOOQd

1100000000000010 1100000000000011

10101Q0011111111

1010100000000000 1010100000000001 1010100000000010

1010100000000011 1010100000000100 1010100000000101

1010100000000110 1010100000000111 1010100000001000

1010100000001000 1010100000001000 1010100000001000

1010100000001000 1010100000001000 1010100000001000

1010100000001000 1010100000001000 1010100000001000

oooooooooooooooo oooooooooooooooo oooooooooooooooo

oooooooooooooooo oooooooooooooooo oooooooooooooooo

oooooooooooooooo

0000000000000000

oooooooooooooooo

oooooooooooooooo oooooooooooooooo

0000111101111110

0000111101111111 0000111110000000

1100011110100011

1100011110100100 1100011110100101 1100011110100110

1100011110100110 1100011110100110 1100011110100110

oooooooooooooooo oooooooooooooooo

oooooooooooooooo oooooooooooooooo

oooooooooooooooo oooooooooooooooo

oooooooooooooooo oooooooooooooooo

oooooooooooooooo 'oooooooooooooooo

oooooooooooooooo oooooooooooooooo

OOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOO '

oooooooooooooooo oooooooooooooooo

oooooooooooooooo oooooooooooooooo

oooooooooooooooo oooooooooooooooo

OOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOO

oooooooooooooooo oooooooooooooooo

oooooooooooooooo oooooooooooooooo

oooooooooooooooo oooooooooooooooo

oooooooooooooooo oooooooooooooooo

oooooooooooooooo oooooooooooooooo

oooooooooooooooo oooooooooooooooo

oooooooooooooooo oooooooooooooooo

000000000000.0000 OOOOOOOOOOOOOOOO

oooooooooooooooo oooooooooooooooo

000111111101Q111 0Q0Q00OO00QOQ00 &

OOOOOOOOOOOOOOOO 0100 OOOOOOOOOOOOOOOO 0100 OOOOOOOOOOOOOOOO 0100 OOOOOOOOOOOOOOOO 0100 OOOOOOOOOOOOOOOO 0100 OOOOOOOOOOOOOOOO 0100 OOOOOOOOOOOOOOOO 0100 OOOOOOOOOOOOOOOO 0100 OOOOOOOOOOOOOOOO 0100 OOOOOOOOOOOOOOOO 0100 OOOOOOOOOOOOOOOO 0100 OOOOOOOOOOOOOOOO 0100 OOOOOOOOOOOOOOOO 0100 OOOOOOOOOOOOOOOO 0100 OOOOOOOOOOOOOOOO 0100 OOOOOOOOOOOOOOOO 0100 OOOOOOOOOOOOOOOO 0100 OOOOOOOOOOOOOOOO 0100 OOOOOOOOOOOOOOOO 0100 OOOOOOOOOOOOOOOO 0100 OOOOOOOOOOOOOOOO 0100

m ^^

S it »

26th
27
28 CFS RI
ΛΙΙ INPUT COMMAND RES. A. AORESSE LEVEL O STACK STORAGE STAGES ADDRESS LEVEL 3 ADDRESS LEVEL 6 AORESSE LEVEL 7 CZSP I. 29
30th
31 CFP CH
η 76543210 76543210 76543210 111111
5432109876543210 ADDRESS LEVEL 1 111111
5432109876543210 111111
5432109876543210 111111
5432109876543210 f 32
33 INP 11
11
11 01010010
11111111
11111111 01010010
01010010
01010010 oooooooo
oooooooo
oooooooo 1010100000001000
1010100000001000
1010100000001000 111111
5432109876543210 0001111111011000
0001111111011001
0001111111011010 oooooooooooooooo
0000000000000000
oooooooooooooooo oooooooooooooooo
oooooooooooooooo
oooooooooooooooo 0100
0100
0100 M 4 34 ADA 11
11
11 01011010
11111100
00101001 01011010
01011010
01011010 oooooooo
oooooooo
oooooooo 1010100000001000
«10100000001000
1010100000001000 1100011110100110
1100011110100110
1100011110100110 0001111111011010
0001111111011010
0001111111011010 oooooooooooooooo
oooooooooooooooo
oooooooooooooooo oooooooooooooooo
oooooooooooooooo
oooooooooooooooo 0100
0100
0100 § J
• 35
36
37 CTC 11
11 01001011
11010001 01001011
0KJ01011 oooooooo
11010001 1010100000001000
1010100000001000 1100011110100110
1100011110100110
1100011110100110 0001111111011010
0001111111Q1101Q oooooooooooooooo
OQOOOOOOOOOOQOOC oooooooooooooooo
, 000000000000000 0100
0100 (O
OO 38
39
40 CFZ 11 10000000 10000000 10100010 1010100000001000 1100011110100110
1100011110100110 0001111111011010 0000000000000000 oooooooooooooooo 1011 41
42
43 CTS 11
11
11 01100010
00011010
10110110 01100010
01100010
01100010 10100010
10100010
10100010 1010100000001000
1010100000001000
1010100000001000 ιιοοοιιιιο «αιιο 0001111111011010
0001111111011010
0001111111011010 oooooooooooooooo
oooooooooooooooo
1011011000011010 oooooooooooooooo
oooooooooooooooo
oooooooooooooooo 1011
1011 ■
1011 O 44
45
41 CTP 11
11.
11 01001010
00101010
11111110 01001010
01001010
01001010 10100010
10100010
10100010 «10100000001000
10101O00O0001000
«« «0000001000 1100011110100110
1100011110100110
1100011110100110 0001111111011010
0001111111011010
0001111111011010 1011011000011011
1011011000011100
1011011000011101 oooooooooooooooo
oooooooooooooooo
1111111000101010 1011
1011
1011 eo 47
48
49 CFP 11
11
11 01110010
01011111
11111-BM 01110010
01110010
01110010- 10100010
«100010
10100010 «« «0000001000
1010100000001000
niii «ooioiiin 11000111W1Q0110
1100811110100110
1100010110100110 0001t11111011010
00011111110110 «
000111111 «110« 1011011000011101
1011011000011101
1011011000011101 1111111000101011
1111111000101100
1111111000101101 1011
1011
1011 11
11
ti 01111010
10H0010
11100110 01111010
01111010
01111010 10100010
«100010
"" 0010 1111110001100000
11111 "001" 0001
1111flQO01 «QO1Q 1100011110100110
1 «00111« 1Q0110
1 «0011110» 0110 000111111 «1« 10
000H11111011O1O
0001111111011010 «IittnooQfliiioi
1011011000011101
«1« 1tfOOO1t! O1 1111111000101101
1111111000101101
1111111000101101 1011
1011
1011 11
11
11 01011010
01111101
«Moii 01011010
01011010
01011010 10100010
10100010
10100010 11111100011000 «
1111110001100010
1111110001100010 1 «OO111« «O11O
1100011110100110
11 «01« «1« 010 0001111111011010
000111111 «110«
00011111110110 « «Ιιοι« οοοη «ι
"Iioi" ooon "i
«11011000011101 1111111000101101
1111111000101101
1111111000101101 1011
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1011 ri «oiio« iiooii
11 «0t! 0101« 100
1110011010110101

fsJ CO

; . · STACK STORAGE STAGES

RI INPUT COMMAND RES, · A AORESSENSTUFE O AORESSENSTUFE 1 ADDRESS LEVEL 3 ADDRESS LEVEL 6 ADDRESS LEVEL 7 CZSP CN

YT 111111 111111 ■ 111111 111111 111111 ''

76543210 76543210 76543210 543210987654321O 54321O9S76543210 5432109876543210 5432109876543210 5432109876543210 '

50
51
52 JFZ 11
11
11 01001000
01111111
10000000 01001000
01001000
01001000 10100010
10100010
10100010 1111110001100010
1111110001100010
1111110001100010 1110011010110110
1110O11O10110111
0000000001111111 0001111111011010
0001111111011010
0001111111011010 1011011000011101
1011011000011101
1011011000011101 1111111000101101
1111111000101101
1111111000101101 1011
1011
1011 53 RET 11 00101111 00101111 10100010 1111110001100010 OOOOOOOOiOQOOOOO 0001111111011010 1011011000011101 1111111000101101 1011 54 RTZ 1.1 00101011 00101011 10100010 1111110001100011 0000000010000000 0001111111011010 1011011000011101 1111111000101101 1011 ω
ο 55 RTC 11 00100011 00100011 10100010 1111110001100100 0000000010000000 0001111111011010 1011011000011101 1111111000101101 1011 co
on 56 .RFP 11 00011011 00011011 10100010 1111110001100100 0000000010000000 000111.1111011010 1011011000011101 1111111000101110 1011 57 RTS 11 00110011 00110011 10100010 1111110001100100 0000000010000000 0001111111011010 1011011000011101 1111111000101111 1011 B / 1039 58 STOP 11 00000000 00000000 10100010 1111110001100100 0000000010000000 0001111111011010 1011011000011110 1111111000101111 1011

true is. The following command call is an unconditional one Call being executed. The command counter is incremented further during the three cycles of this call · dies is shown at address level 0. Since it is a call, the address level on the stack becomes the address level 1 changed. The input signals during the time segments 15 and 16 are transferred to address level 1; they are shown in time segment 16. During the period of time 52 a jump is executed with an incorrect zero value. This jump with a false zero value is in the address level 1 to see. During the next time period 53, an unconditional return command is executed. It is recognizable, that the address level 1 is brought up to date, with the program address control signals, however, to the address level 0 return. This can be seen by looking at the address counter at time segment 54. The counter of the Address level 0 has been updated and address level 1 remains the same. The next command was' a true zero return command. This command is not executed because the zero indicator has the signal value 0 and the control signal remains at the signal value 0. The next command is a return command with incorrect parity. This command returns control signals from address level 0 to address level 7, as can be seen in time segment 57 in which the address level 0 is not increased, but the address level 7 is increased. Because the stack indicator is an up / down counter, transmits an additional Control signals return to address level 7 when address level 0 is reached.

As can be seen in FIG. 25, there is a different combination the control signals U and V before when these two

309815/1039

2242312

"Control signals have the signal values O. In this case, the NAND gate 227 is triggered in such a way that it generates an input signal with the signal value 1 for the renewal counter and that it applies the signal value to the gate electrodes of the transmission gates 258 * This signal enables the direct application of the output signals R1, R2 and R5 of the renewal counter to the inverters 212a, 2i2b and 212c. This enables the renewal of an entire line of the random access memory. The renewal counter is increased each time both control signals U and Y with Signal values 0. The renewal counter counts from 0 to 7. This enables eight lines of the random access memory to be renewed after eight count pulses. The command control is designed so that at least one renewal process takes place during a command the central unit is in a waiting state or in a halting state The refresh counter continuously controls the dynamic random access memory to ensure that old data remains valid. Table VIII indicates when the renewal takes place in each instruction cycle. So It can be seen from Table VIII that at times S1, S2, S3 and S4 of the partial retrieval cycle, there is always an access to registers P ^ or Pg. This means that no renewal can take place during this time. It should be noted, however, that the random access memory is never accessed during access 1 of the sub-execution cycle. That is the time when the renewal occurs.

, Figure 26 shows a clocked inverter, the one here described random access memory is used. The .. negator is used for the read and write lines of the cells

30981571039

of the random access memory is used, the clock signal itself is used as the low voltage · When the clock signal is low, the output signal is valid and ea gives the negated value of the input signal again. If, on the other hand, the clock signal is high, that is, has the signal value 1, that remains The output signal always has the signal value 1, so that the memory cell not addressed we ^. The clocked negators here The arrangement described above offer numerous gate parts. encoder is not loaded with such a large capacity as conventional precharge methods. In addition, there will be clock signal noise decreased because the clock signal does not have a discharge current leads. This is an advantage over conventional methods, where circuits are very sensitive to clock signal noise are.

FIG. 27 shows the exact logic circuitry of the stack indicator. As can be seen, three outputs S1, 32 and 33 are indicated. These outputs come from blocks labeled Έ , each representing a flip-flop circuit, the logic of which is shown in FIG. The mode of operation of such a flip-flop circuit is known to the person skilled in the art, so that no further explanation is required here. The flip-flop circuit is also used in the renewal counter shown in FIG.

Bin / output coupling device

In this section, the input / output coupling device is described, which is shown in FIG. 1 in block 16. The functional block diagram showing the various element

309815/1039 U

of the system timing is shown in FIG. FIG. 31 shows the logic circuit elements in FIG 30 shown function blocks. The coupling device comprises the connection between the central unit and, for example, an external random access storage unit. These Connection is made via a parallel, 8-bit external bus. The connection of the central unit with 1K of the storage capacity of the external random access memory is shown in FIG. As above 'loading'

has already been described, the external random access memory have a storage capacity of up to 64K bytes, since sixteen bits are used for memory addressing. As those skilled in the art will recognize, when implemented at this size, the memory is fabricated on multiple wafers. A chip select signal is input from a memory coupling circuit shown in FIG for the external random access memory ζμΓ selection of the required Plate delivered.

The central unit controls the system time control. To this Time control signals are sent from the central unit an external timer is applied, which is shown in Figure 35 '. The external timer has an output that is on an external timing logic shown in FIG. 34 is applied. The external timing logic also receives' an input signal from the central unit. The output of the external timer logic is to the timing interface block connected, the mode of operation between the central processing unit, the random access memory and the peripheral devices synchronized. External system inputs and the system outputs are applied to this block shown in FIG. 33 are derived from him. This circuit delivers

309815/1039

Outputs to the external memory and to the memory coupling circuit.

The truth table given in Table XI shows the five output states corresponding to changes in the input signals READY or 'INTERRUPT. The input lines A ₇ to A _Q are divided into input and output terminals in the truth table. In FIGS. 32a and 32b, the connection of the central unit with 1K of the storage capacity of the random access memory is shown. As can be seen, only eight external bus wires are required for these connections. The input / output section of the central unit was described above in connection with FIG. As has been described, the input / output to the central unit takes place on lines Aq to A ". These eight connection lines are connected to the various units of the external random access memory. The various units of the random access memory are generally designated by the reference numeral 301. These memories are preferably dynamic iO24x 1 random access memories. Processes for producing random access memories are known to the person skilled in the art, so that they do not require any further explanation here. Circuits for coupling the random access memory, for renewing its content, etc. will be described later in connection with FIGS. 37 to 44.

As can be seen, a tile selection signal is applied to each of the units 301, which indicates the selection of the correct one Unity enables. An advantage of the connection system shown in Figures 32a and 32b is that

309815/1039

TABLE XI

EXIT

ROY * INPUT R. I. OUTPUT S. E. C. H I. D. H Y X Y E. N .Y T N C. H T C. L. H E. S. 76543210 ■ » 76543210 T Y O 00100000 O O oooooooo O O 1 1 1 1 OOOOOOOO 1 O oooooooo O O 1 1 1 2 INT OOOOOOOO 1 O 11111111 1 1 1 1 O 3 OOOOOOOO 1 O oooooooo O 1 1 1 O 4th oooooooo 1 O oooooooo O 1 1 1 O 5 oooooooo 1 Q oooooooo O 1 1 1 O 6th oooooooo 1 O oooooooo O 1 1 1 O 7th oooooooo ■ 1 O oooooooo . O 1 1 Q O β oooooooo 1 O oooooooo O 1 1 O O 9 11111111 1 1 oooooooo O 1 1 O O 10 11111111 1 ,1 oooooooo O 1 1 O O 11 11111111 1 1 oooooooo O 1 1 O O 12th 11111111 1 1 oooooooo O 1 1 O 1 13th 11111111 1 1 oooooooo 1 O 1 O 1 14th 11111111 1 1 oooooooo O O 1 O 1 15th 11111111 1 1 11111111 O O 1 O 1 16 11111111 1 1 oooooooo O O 1 O 1 17th 11111111 1 1 oooooooo 1 1 1 O O 18th INT 11111111 1 1 oooooooo O 1 1 O O 19th 11111111 1 1 oooooooo ■ Q 1 1 O O 20th 11111111 1 1 oooooooo O 1 1 O O 21 11111111 1 1 oooooooo O 1 1 O O 22nd IHT 11111111 1 1 oooooooo O 1 1 O O 23 11111111 1 O oooooooo O 1 1 O O 24 11111111 1 O oooooooo O 1 1 O O 25th 11111111 1 1 oooooooo O 1 1 O O 26th 11111111 1 O oooooooo O 1 1 O O 2? 11111111 1 O oooooooo O 1 1 O O 28 11111111 1 O oooooooo O 1 1 O 1 29 11111111 1 1 oooooooo 1 O 1 O 1 30th 11111111 1 O oooooooo O O 1 O 1 31 11111111 1 O 11111111 O O 1 O 1 32 11111111 1 O oooooooo O O 1 O 1 33 00111110 1 O oooooooo 1 1 1 O O 34 11111111 1 O oooooooo O 1 1 O O 35 11111111 1 O oooooooo O 1 1 O O 36 11111111 1 O oooooooo O 1 1 O O 37 11111111 1 O oooooooo 1 O 1 O O 38 11111111 1 O oooooooo O O O O O 39 11111111 1 O 11111111 O O O O O 40 11111111 1 O oooooooo O O O O O 41 11111111 1 O oooooooo 1 1 O O O

309815/1039

TABLE η (Continuation)

ROY INPUT R. I. OUTPUT S. E. C. N I. O N t X Y E. N • y I. I. C. H T C. L. M. E. S. 76543210 76543210 T r 42 11111111 1 O 00000000 O 1 O O O 43 11111111 1 O 00000000 O 1 O O O 44 11111111 T O 00000000 O 1 O O O 45 11111111 1 O 11111111 1 O O O O 46 ROY 11111111 1 O 00000000 O O O 1 O 47 11111111 1 O 11111111 O O O 1 O 48 11111111 1 O 00000000 O O O 1 O 49 11111111 1 O 00000000 1 1 O 1 O 50 ROY 11111111 1 O 00000000 O 1 O 1 O 51 ROY 11111111 O O 00000000 O 1 O 1 O 52 11111111 O O 00000000 O 1 O 1 O 53 11111111 O O 00000000 O 1 O 1 O 54 11111111 O O 00000000 O 1 1 O 1 55 11111111 O O 11111111 1 O 1 O 1 56 INT 11111111 O O 00000000 O O 1 O 1 57 11111111 O O 11111110 O O 1 O 1 58 11111111 O O 00000000 O O 1 O 1 59 11111111 O O 00000000 O O 1 O 1 60 11111111 O O 00000000 O O 1 O 1 61 11111111 1 O 00000000 O O 1 O 1 62 01000100 1 O 00000000 1 1 1 O O 63 11111111 1 O 00000000 O 1 1 O O 64 11111111 1 O 00000000 O 1 1 O O 65 11111111 O O 00000000 O 1 1 O O 66 11111111 1 O 11111111 1 O 1 O O 67 11111111 1 O ooocoooo O O O O O 68 11111111 1 O 11111110 O O O O O 69 11111111 1 O 00000000 O O O O O 70 11111111 1 O 00000000 1 1 O O O 71 11111111 1 1 00000000 O 1 O O O 72 11111111 1 O 00000000 O 1 O O O 73 11111111 1 O 00000000 O 1 O O O 74 11111111 1 O 11111110 1 O O O O 75 11111111 1 O 00000000 O O O O O 76 11111111 1 O 11111110 O O O O O 77 11111111 1 O 00000000 O O O O O 78 00111111 1 O 00000000 1 1 O O O 79 00000000 1 O 00000000 O 1 O O O 80 00000000 1 O 00000000 O 1 O O O 81 oocooooo 1 O 00000000 O 1 O O O

309815 / 1.039

-433

TABLE XI (continued)

EXIT

INPUT R. I. OUTPUT S. E. C. H I. O N Y X Y E. N Y T N C. H T C. L. K E. S. 76543210 76543210 T Y 82 00000000 1 O 00000000 O 1 O O O 83 00000000 1 O 00000000 O 1 1 O 1 84 00000000 1 O 00000000 1 O 1 O 1 85 00000000 1 O 00000000 O O 1 O 1 86 00000000 1 O 11000000 O O 1 O 1 87 00000000 1 O 00000000 O O 1 O 1 88 11000000 1 O 00000000 1 1 1 Ό O 89 11111111 1 O 00000000 O 1 1 O O 90 11111111 1 O 00000000 O 1 1 O O 91 11111111 1 O 00000000 O 1 1 O O 92 11111111 1 O 00000000 1 O 1 .0 O 93 11111111 1 O 00000000 O O 1 O O 94 11111111 1 O 11000000 O O 1 O O 95 RDY 11111111 O O 00000000 O O 1 O O 96 ROY 11111111 1 O 00000000 O O 1 O O 97 00111101 1 O 00000000 O O 1 O O 98 00111101 1 O 00000000 1 1 1 O O 99 00111101 1 O 00000000 O 1 1 O O 100 00111101 1 O 00000000 O 1 1 O O 101 00111101 ■ 1 O 00000000 O 1 1 O O 102 00111101 1 O 11111111 1 O 1 O O 103 00111101 1 O 00000000 O O O O O 104 00111101 1 O 11111111 O O O O O 105 00111101 1 O 00000000 O O O O O 106 00111101 1 O 00000000 1 1 O O O 107 00111101 1 O ooonoooo O 1 O O O 108 00111101 1 O 00000000 O 1 O O O 109 00000000 1 O 00000000 O 1 O O O. 110 00000000 1 O 11111111 1 O O O O 111 00000000 1 O oooooooo O O 1 O O 112 00000000 1 O 00011111 O O 1 O O 113 00000000 1 O oooooooo O O 1 O O 114 00000000 1 O oooooooo 1 1 1 O O 115 00000000 1 O oooooooo O 1 1 O O 116 00000000 1 O oooooooo O 1 1 O O 117 00000000 1 O OOOOOQOO O 1 1 O O 118 00000000 1 O oooooooo O 1 1 O O 119 00000000 1 O oooooooo O 1 1 O O 120 00000000 1 O oooooooo O 1 1 O O

309815/1039

Interleaving the address input and output signals simplifies the connection, since there are only eight in total Memory lines "are required. If multiplexing is not used, it is necessary to run 26 connecting lines. This is shown in FIG. 32c which shows the conventional way of accessing external storage.

The process of die selection is shown in FIG. By using four decoding units with 16 outputs it is possible to store 1K to 65K of the memory platelets to select. .The chip select input signal of the random access memory is clocked so that it is in right time is sampled. At all other times, the platelet select output is invalid.

FIG. 34 shows the external timing logic for the input / output control. The timing is from the output signal the central unit and the output signal of an external, described in more detail in connection with FIG State timer caused. These signals are combined so that either one of the external storage registers or data inputs to the system are selected from an external peripheral device.

Figure 35 shows the logic circuit of the external timer. This timer counts the four states of the central unit. An output signal is used to ensure the synchronous running of the external clock of the central unit the central unit a synchronization signal that resets the timer at each state 1; The external timer also synchronizes the external one

30981 5/1039

Memory with the same time frame as the central unit. This ensures that the inputs and outputs of the external storage in the correct state.

Figure 33 shows the coupling logic used with the current sense / voltage input of the central unit. The connection to the central unit is shown at circuit point 300 (A ^). For example, this connection can lead to any of the input lines A _Q 'to A «of the central unit. For an eight line manifold system, eight of the circuits shown in FIG. 33 are required. The circuit point 300 is connected to the outputs A of the external memory and to the outputs A of the central unit. During a low phase 1, the data selector 302 is activated. Either the input signal DATA, DMAH, DMAL or M ^{1 are} selected. The ^{input · 1} , input signal DATA is used to load information from peripheral units into the central unit or into the random access memory. When the data processing arrangement is stopped, the information can be loaded directly into the memory. The data must be available during state s 3 and the STORE control signal must have the signal value 1. When the data processing arrangement is in operation, the input signal DATA is selected during the command execution time state 1 of an interrupt confirmation signal, during the data execution time state 1 of an external command or during the control signal STORB with the signal value 1 in time state 3.

The input signal DMAL corresponds to the eight low-order address bits generated by the DMAL holding circuit are selected for direct memory access.

309815/1039

This input signal is selected during the Execution state 2, during READY with the signal value 0 in state 2 or during STORE with the signal value 1 in state 2.

The input signal DMAH corresponds to the eight bits with higher significance for direct memory addressing via the DMAH hold circuit. This input signal is selected while executing in state 41 during READX with the signal value 0 'in state 4 or during STORE with the signal value 1 in state' 4.

To load the memory when the central unit is stopped the input signal STORE is used. The input signal STORE must be from the beginning of state 2 to the end of the following state 1 have the signal value 1. The four-state input signal STORE allows the from the memory locations addressed to the input signals DMAL and DMAH to save the byte present at the DATA input.

The output of data selector 302 is amplified by transistor 304. This means that all A lines of the external random access memory can be controlled. During the low phase 2 of the clock, the central processing unit or the random access memory outputs a current. This current is sampled by sense amplifier 314. Since such amplifiers are known to the person skilled in the art, they are not described in detail here. The low current is boosted to a TTIr voltage level that is input to hold circuits 306, 308, 310 and 312. These are holding circuits that contain valid information regarding the output of the central processing unit. Register M ¹ closes the current sensor /

309815/1039

Voltage input loop of the central unit. The register CDMA, is shown at 308. This register is a TTL hold circuit for direct memory access and it contains the information byte which is present in the last byte of the memory addressed by the signals DKAL or DMH. The register I 'is at 310, and it contains the last ^{instruction fetched from memory. The register A 1} is shown at 312. For each external instruction, this register A ^{1 is} updated with the contents of the internal register A of the central processing unit.

An example of the current sampling is described using the timing diagrams in Table XII.

309815/1039

TABLE XII Timing

or L or DMAL ^p h or H or DMAH I. A. (A) m ^r s
B1 or B2 D ¹ D.

Low Significance Address High Significance Address Command
Register A

Entry in register A (data entry)

Output from storage location HL Contents of the source register

Byte 1 or byte 2 of the data signal

New data for RAM memory location Pj ₁ P ₁ or HL

Data from storage location Py ₁ P ₁ or HL or (DMIIDML) ⁿ

309815/1039

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309S1B / 1039

- if -

TABLE XII (continued ) Central Unit Timing Chart

STOP Il
Il 1 2 H H f I. • M. - rvl H < A.
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309815/1039

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TABLE XII (continued)

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309815/1039

This table shows the times at which output signals or input signals occur on the central unit. Output signals appear during phase 2 of a state, while input signals appear during phase 1. For example, be on. reference is made to cycle 2 of the EXT command. During the partial cycle FETCH in state S1 'in phase 2, the central unit outputs the content of register A as a current. This current is amplified in the sense amplifier 3H of FIG. 33, and it forms an input signal for the holding circuit 312, which is denoted by CACC and which is also entered into the register M ¹ . At the end of phase 2, if the data signal at the sense amplifier 3H is valid, the signal CACC causes the results of the register A to be clocked in. This register is updated with every external command.

An example of the closed loop of the current sampling and the TTL voltage input can be seen from the shift command in state S1 'of the partial cycle FETCH. During phase 2, the central unit outputs a current which corresponds to the content of the register Pt. This current has the negated value of the current value. The loop negates the output signal at point M ¹ . During phase 1, the random access memory awaits the content of the address. During state 2 in phase 1, E ^ and Ep select the input Cq of the data selector 302. As can be seen, this is the content of register M ¹ or the memory location desired for the address and the low-order memory. During phase 1 of the clock cycle, the data selector 302 outputs the content of the register M ¹ , which is amplified and applied to the node 300. The corresponding signal forms the input signal for the direct

30981 5/1039

Access memory, as shown in Table XII in state S ¹ in phase 1 of the partial cycle FETCH. During state S4 ^{1 of} a recall cycle, the high priority address bits are entered into the random access memory. During phase 2 in state S4 ^{1 of} the sub-cycle EXECUTE, the data in the address _{memory location Pj 1} Pj _{1 of} the random access memory are output on the current scanning line. In phase 1 of the execution status that now follows, the shift command SHIFT is entered in the central unit. During the execution phase of the command cycle, the central processing unit does not request any information from the random access memory. For programming purposes, direct memory access is possible while the central processing unit is executing the command. This is done by using the input signals DMAH and DMAL. For example, the signal DMAL occurs in the course of a recall state RECALL, during the partial cycle EXECUTE in state S2 'in phase 1. It is input into data selector 202 on line A ^ Memory assumes this address. During state S4 * , the input signal DMAH of the data selector is selected and the address with the most significant value is transferred to memory. In the course of state S4 ¹ in phase 2 of the partial cycle EXECUTE, the random access memory provides the memory location The output signal B is ^{stored in the hold circuit labeled DMA 1} (Figure 33). The clock signal CDMA causes the output signal of the random access memory to be entered and stored there for use in the external system.

Table XIII shows for loading a program for Add two numbers into memory to create a truth table

£ 242912 43H

the logic states of the signals READY, INTERRUPT, STORE, EXECUTE, SYNCH, the first external state S1, the second external state S2, the third external state S3, the fourth external state S4, the data input signal DATA, the signal DMAL, the signal DMAH , the command register I ¹ , the register A 'and the register DMA ¹ ,

309815/1039

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27 EXT R. I. S. E. 1 1 1 S. ZUSTANO DATA OHAL DNAH COMMAND A « DMA « - 28 D. N T X Ö 0 1 Y 29 Y T 0
R. 0 0 1 N
C. 76543210 30th E. 0 O ^ 1 H SSSS 11111111 31 STOP 0 0 0 1234 76543210 76543210 • 76543210 76543210 76543210 11111111 32 1 0 1 1 0 0 0 0 1000 01000001 00000101 00000000 oooooooo oooooooo 11111111 33 1 0 1 1 0 0 0 0 0100 01000001 00000101 '00000000 oooooooo oooooooo 11111111 34 1 0 1 1 0 0 0 0 0010 01000001 00000101 00000000 oooooooo oooooooo 11111111 1 0 1 1 0 0 1 0 0001 01000001 00000101 00000000 oooooooo oooooooo 11111111 35 1 0 1 1 0 0 1 0 1000 11111111 00000111 00000000 oooooooo oooooooo 11111111 36 1 0 1 1 0 0 1 0 0100 11111111 00000111 00000000 oooooooo oooooooo 11111111. co 37 1 0 1 1 0 0 1 0 0010 11111111 00000 * 111 oooooooo oooooooo oooooooo to 38 1 0 1 1 0 0 0 0 0001 11111111 00000111 00000000 oooooooo oooooooo 11111111 39 INTERRUPTION 0 0 0 11111111 tn 40 1 0 0 0 0 1000 11111111 00000111 oooooooo oooooooo oooooooo 11111111 41 1 0 0 0 0 0100 11111111 00000111 oooooooo oooooooo oooooooo 11111111 42 1 0 0 1 0 0010 11111111 00000111 oooooooo oooooooo oooooooo 11111111 O
*. \ 43 1 0 0 1 0 0001 11111111 00000111 oooooooo oooooooo oooooooo 11111111 <D 1 0 0 1 1 1000 00000101 00000111 oooooooo oooooooo oooooooo 11111111 45 1 0 0 1 0 0100 00000101 00000111 oooooooo oooooooo oooooooo 11111111 46 1 0 0010 00000101 00000111 oooooooo oooooooo oooooooo 11111111 47 1 0 0001 00000101 00000111 oooooooo 11111111 oooooooo 11111111 48 1 1 1000 00000101 00000000 oooooooo 11111111 oooooooo 11111111 49 1 0 0100 00000101 00000000 oooooooo 11111111 oooooooo 00000110 50 1 0 0010 00000101 00000000 oooooooo 11111111. oooooooo 00000110 51 1 0 0001 00000101 00000000 oooooooo 11111111 oooooooo 00000110 52 1 1 1000 00000101 00000000 oooooooo 11111111 oooooooo 00000110 53 1 0 0100 00000101 00000000 oooooooo 11111111 oooooooo 00000110 54 1 0 0010 00000101 00000000 oooooooo 11111111 oooooooo 00000110 1 0 0001 00000101 00000000 oooooooo 11111111 oooooooo 00000110 1 1 1000 00000101 00000001 oooooooo 11111111 oooooooo 00000110 1 0 0100 00000101 00000001 oooooooo 11111111 oooooooo 00111000 1 0 0010 00000101 00000001 oooooooo 11111111 oooooooo 1 0 0001 00000101 00000001 oooooooo 11111111 oooooooo

55 R. Ί S. E. S. STATE OATA OMAL OMAH COMMAND A ' DMA ' 56 ■ 0 N T X Y 57 Y T 0
R. N
C. 58LA E. H SSSS 59 1234 76543210 76543210 7654321Q 76543210 76543210 76543210 60 1 0 0 0 1 1000 00000101 00000001 00000000 11111111 oooooooo 00111000 -61 1 0 0 0 0 0100 00000101 '00000001 00000000 11111111 oooooooo 00111000 62 1 . 0 0 0 0 0010 00000101 00000001 00000000 11111111. oooooooo 00111000 63 1 0 0 0 0 0001 00000101 00000001 00000000 00000110 oooooooo 00111000 64 1 0 0 1 1 1000 00000101 00000010 00000000 00000110 oooooooo 00111000 65 1 0 0 1 ■ 0 0100 00000101 00000010 00000000 00000110 ■ oooooooo 00111000 U) 66 1 0 0 1 0 0010 00000101 . 00000010 00000000 00000110 oooooooo 00111000 to 67 1 q 0 1 0 0001, 00000101 00000010 00000000 00000110 oooooooo 00001110. 00 68 1 0 0 0 1 1000 00000101 00000010 00000000 00000110 oooooooo 00001110 69 1 0 ο ■ 0 0 0100 00000101 00000010 00000000 00000110 oooooooo 00001110 Oil
• ^ 70 1 0 0 0 0 0010 00000101 00000010 00000000 00000110 oooooooo 00001110 71 1 0 0 0 0 0001 00000101 00000010 00000000 00000110 oooooooo 00001110 O
«.% 72 1 0 0 1 1 1000. 00000101 00000011 00000000 00000110 oooooooo 00001110 W.
CO 73 1 0 0 1 0 0100 00000101 00000011 00000000 00000110 oooooooo 00001110 74LB 1 0 0 1 0 0010 00000101 00000011 oooooooo 00000110 oooooooo 00001110 75 1 0 0 1 0 0001 00000101 00000011 00000000 00000110 oooooooo 00001010 76 1 0 0 0 1 • 1000 00000101 00000011 oooooooo 00000110 oooooooo 00001010 77 1 0 0 0 0 0100 00000101 00000011 oooooooo 00000110 oooooooo 00001010 78 ,1 0 0 0 0 0010 00000101 00000011 oooooooo 00000110 oooooooo 00001010 79 ■ 1 0 0 0 0 0001 00000101 00000011 oooooooo 00001110 oooooooo Ώ0001010 80 1 0 0 1 1 1000 00000101 00000100 oooooooo 00001110 oooooooo 00001010 81 1 0 0 1 0 0100 00000101 00000100 oooooooo 00001110 oooooooo 00001010 82 1 0 0 i 0 0010 00000101 00000100 oooooooo 00001110 oooooooo 00001010 1 0 0 1 0 0001 00000101 00000100 oooooooo. 00001110 oooooooo 10000001 ■ 1 0 0 0 1 iooo 00000101 00000100 oooooooo .00001110 oooooooo 10000001 1 0 0 0 0 • 0100 00000101 00000100 oooooooo 00001110 oooooooo 10000001 1 0 0 0 0 0010 00000101 00000100 ■ oooooooo 00001110 oooooooo 10000001 1 0 0 0 0 0001 00000101 00000100 oooooooo 00001110 oooooooo 10000001

to

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R. I. S. E. S. STATE DATA • DHAL DHAH COMMAND A » DHA ' D.
Y N
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C. E. H SSSS 76543210 1234 00000101 76543210 76543210 76543210 76543210 76543210 83 1 0 0 1 1 1000 00000101 00000101 oooooooo 00001110 oooooooo 10000001 84 1 0 0 1 0 0100 00000101 00000101 oooooooo 00001110 oooooooo 10000001 85 1 0 0 1 0 0010 00000101 00000101 oooooooo 00001110 oooooooo 10000001 86 1 0 0 1 0 0001 00000101 00000101 oooooooo 00001110 oooooooo 01000001 87 1 0 0 0 1 1000 00000101 00000101 oooooooo 00001110 oooooooo 01000001 88 1 0 0 0 0 0100 00000101 00000101 oooooooo 00001110 oooooooo 01000001 89 1 0 0 0 0 0010 00000101 00000101 oooooooo 00001110 oooooooo 01000001 90 ADB 1 0 0 0 0 0001 00000101 00000101 oooooooo 10000001 oooooooo 01000001. 91 1 0 0 1 1 1000 00000101 00000111 oooooooo 10000001 oooooooo 01000001 92 1 0 0 1 0 0100 00000101 00000111 oooooooo 10000001 oooooooo 01000001 93 1 0 0 1 0 0010 ■ 00000101 00000111 • oooooooo 10000001 oooooooo • 01000001 94 1 0 0 1 0 0001 . 00000101 00000111 oooooooo 10000001 oooooooo 11111111 95 1 0 0 0 1 1000 00000101 00000111 oooooooo 10000001 oooooooo 11111111 96 1 0 0 0 0 0100 00000101 00000111 oooooooo 10000001 oooooooo 11111111 97 1 0 0 0 0 0010 00000101 00000111 oooooooo 10000001 oooooooo 11111111 98 EXT 1 0 0 0 0 0001 00000101 00000111 oooooooo 01000001 oooooooo 11111111 99 1 0 0 1 1 ■ 1000 00000101 00000111 oooooooo 01000001 oooooooo 11111111 100 1 0 0 1 0 0100 00000101 00000111 oooooooo 01000001 oooooooo 11111111 101 1 0 0 1 0 0010 00000101 00000111 oooooooo 01000001 oooooooo 11111111 102 1 0 0 1 0 0001 00000101 00000111 oooooooo 01000001 oooooooo 11111111 103 1 0 0 0 1 1000 00000101 00000111 oooooooo 01000001 01000010 11111111 104 1 0 0 0 0 0100 00000101 00000111 oooooooo 01000001 01000010 11111111 105 1 0 0 0 0 0010 00000101 00000111 oooooooo 01000001 01000010 11111111 106 1 0 0 0 0 0001 00000101 00000111 oooooooo 01000001 01000010 11111111 107 1 0 0 1 1 1000 00000101 00000111 oooooooo 01000001 01000010 11111111 108 1 0 0 1 0 0100 00000101 00000111 oooooooo 01000001 01000010 11111111 109 1 0 0 1 0 0010 00000101 00000111 oooooooo .. 01000001 01000010 11111111 110 1 0 0 1 0 0001 00000111 oooooooo 01000001 Q1000010 11111111

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309816/1039

Logic circuit of the external memory

FIG. 7 shows a block diagram of the basic components of the external memory. The external storage described here offers several advantages. The memory contains an externally controlled timer (FIG. 38) which enables the address, data, input and output information to be interleaved with one another for multiplex operation. The _f circuit also includes a refresh counter for use in the external memory that executes the renewal automatically. Another advantage of the circuit is that an address register holding circuit (as shown in Figure 41) is included as part of the external memory. This type of circuit is usually provided outside the ^v memory so that a plurality of terminal connections and more space is required, while a lower reliability results. The output of the address register holding circuit is applied to an address decoder as shown in Figure 43a and Figure 43b. The decoder receives an input from the external bus and also from a die trigger circuit shown in FIG. The input / output logic shown in FIG. 40 receives an input signal from the externally controlled tent transmitter, and it also receives recall commands. The external memory can be either random access or serial access memory and it receives its inputs from the decoder circuit, the refresh counter (if random access memory is used) and from the input / output logic.

309816/1039

Pigur 38 shows the externally controlled timer of the external memory. The timer receives an input signal ST, which is a synchronization input signal which ensures that the externally controlled timer operates in synchronism with the main timer of the central unit. The externally controlled timer, for example, counts the four states of the random access memory. During state 1, the random access memory RAM is automatically renewed. The renewal circuit will be described in more detail later in connection with Pi- · ■■ - ■ · · -gur 42. During state 2, the random access memory assumes low priority address bits. During state 3 takes it data, and during state 4 he takes address bits of high priority and is a-s data storage space from. If the synchronization signal S "T has the signal value 0, the nodes 412 and 414 are at the signal value 1. This is the time of the first state. The counter shown is a conventional Johnson counter which counts the Johnson states. Such counters are known to the person skilled in the art, so that no further explanation is required here.

Figure 39 shows the circuit for sampling and storing the wafer selection used in the external memory described herein. This circuit is necessary because the wafer signals change continuously and it is necessary to clock the correct wafer signal at the appropriate time. While the counter time signal GqG ₁ , which is shown at circuit point 416, is present, the chip selection input signal (CS) is clocked if the signal at circuit point 416 has the signal value 0. The signal value 0 at the node 416 generates the signal value 1 at an input of the AND gate 417.

309815/1039

selection input signal CS has the signal value 1, the output signal of the AND gate 417 also has the signal value. This ensures that the output signal of the NOR gate 419 has the signal value 0. This signal value is negated by the inverter 421 after phase 2 of the cycle, in which an output signal CS 'with the signal value 1 is supplied. _{If the signal CqC 1} now assumes the signal value 1, the AND gate 425 feeds the platelet selection signal ^{CS 1} back into circulation until a new scanning signal is received, that is, until the signal CqC ₁ assumes the signal value 0 again .

One of the input signals of the input / output coupling device is the recall control signal R. If the recall control signal R has the signal value 0 and the chip selection signal CS ¹ (see FIG. 39) has the signal value 1, then the NAND gate 420 emits a signal at the output the signal value O. This signal triggers AND gate 422. The output signal at 406 of the shift register is transferred to the * data input line 424 of the external memory. If the signal CS ^{1 has} the signal value 0, then the output signal of the NAND gate 420 has the signal value 1. This selects the output line 400 and the output signal is transmitted back to the data input line 424 via the AND gate 425 and the NOR gate 427 . If the recall control signal R, the signal CS ¹ and the signal C ^ TC _{1 have} the signal value 1, then the output signal of the NAND gate 403 has the signal value 0. This is an input signal for the OR gate 431. The other input signal of the OR gate 431 is output from the negated signal

309815/1039

line 400 is formed. In this pail the signal is on of the output line 400 to the input / output terminal of the random access memory, the input line 424 and output line 400 come from the data storage cell selected in external memory is.

From the above description it can be seen that data are output, we, nn the signals C ^ C -j, R and GS ^{1 have} the signal value 1. Data is entered when the R signal has the signal ^{value 0 and the signal CS 1 has} the signal value 1. Data is going into circulation when the signal R has the signal value 1 or 0 and when the signal CS ^{1 has} the signal value 0.

Figure 41 shows the address hold circuit used in conjunction with the external memory described herein. This is a sample and memory hold circuit, the mode of operation of which is similar to that of the intermediate memory register which has been described in detail in connection with FIG. The first address _{bits A ^ 0} to Α _χ are stored in the scan and storage registers until the address bits change again. The data is clocked in the time in which the signal CqCTJ "has the signal value 1, and they are clocked through the terminals Aq to A. of the random access memory. The address bits at the terminals A ₅ , Ag and A ₇ are represented by a series of inverters 431 clocked so that they are delayed, and so forth are the same time as the address bits _Α χο, _Α χ1 as output signals, the address bits A to _{Q 7} A low value is input during the condition. 2

309815/1039

During state 4, the remaining two high-value address bits, which are necessary for addressing the external 1024x1-bit memory, are entered via inputs A _Q and A ₁ . They are transmitted to the address lines Ay- and Α «via a phase 1 delay. It can be seen that in this way the ten bits necessary for addressing the external memory are made possible using an eight-bit bus.

FIG. 43a shows the address multiplexer connected to the external memory. You signals on lines Α _χ0 to Αγ. are decoded as soon as they are sampled in the sample and hold register. This enables faster decoding for the Y decoders shown in FIG. 43b for the first and second stages. The Y decoder for the first stage decodes the bits on lines Ay ₀ to Ay ₂ , while the Y decoder for the second stage decodes the bits on lines Ay and Ay. decoded.

Figure 42 shows the renewal counter for the random access memory. The renewal counter is used to automatically count the 32 memory lines in the random access memory to renew. During each state 1 a line is renewed. This has the advantage that it is not necessary interrupt the central unit to renew the dynamic external memory. Expected during state 2 the memory low order address bits. During state 3, there must be data stored in memory be. During state 4, the memory expects high priority address bits. The inputs are all in phase

309815/1039

During state 2 the memory gives information a "b, if the storage space required at the disk selection input has a low signal value. During state 1, the memory neither accepts inputs nor outputs data, since this is the state of renewal. Table 10 shows the logic names assigned to the external memory, and their function is described. ■

309815/1039

- Ul -

Table X External random access memory logic name

Steps:

CHIP SELECT

RECALL

krj through Aq are the address input lines. Eight low order address bits are input during the low value of phase Φ1 of state 2. Two high order address bits are input on input lines Aq and A ₁ during the low value of phase Φ 1 of state 4. The true data value is entered.

The data is entered at the low value phase Φ1 of state 3. The input / output line I / O is connected to the Α line of the desired bits connected. The data is entered with the true data value.

The signal is input during the low value of phase Φ 1 of state 4 Chip Select. A low signal value (logical signal value 0) causes the selection of the desired 1K of memory.

A high signal value (signal value 1) of the signal with RECALL allows a recall Storage space without its content being destroyed. The RECALL signal must be used during all States other than state 1 have a high signal

309818/1039

Continuation to TaTpeile X

have value. If the RECALL signal has a low signal value during state 1 has the data clocked during the previous three states on the Storage space saved, which is determined by the previous states 2 and 4 has been"

SINCH

The internal status counter of the random access memory is synchronized by the external status counter. The input takes place of a signal with a low signal level during the external state 1.

Outputs: I / O

The data is output on the input / output line I / O during phase Φ 2 low of state 4 when the signal CHIP SELECT has a low signal value during state 4. The data output takes place negated.

309815/1039

Figure 44 shows typical MOS clock signals Φ ^ and Φ «and TTL clock signals Φ., And ^ *

The external read-only memory ROM shown in the block in FIG. 1 is preferably a 1024x8 memory. It conventional read-only memories can be used. Such memories are known in the art, so they need no further explanation here. The read-only memory ROM would typically contain fixed subroutines.

Figure 45 shows another embodiment of the invention. In this embodiment, a system is described in which two central processing units work as described above, the external memory and the jointly use the coupling device provided for this purpose. Since the data processing arrangement only during a retrieval sub-cycle and does not exercise memory access during the execution thread cycle, it is possible that a second central unit has access to the same memory while a central unit is busy with the execution is. Such a circuit arrangement is shown in FIG. The block 500 is the common one external storage. As in FIG. 1, this memory contains a read-only memory and a random access or serial access s memory. The two central processing units are shown as blocks 502 and 504. Preferably each of the central processing units mounted on a single plate. Each of the central units has external timing and Hold circuits 506 and 508. As an external timing circuit can be the one described above in connection with FIG Circuit can be used. The hold circuits can

309815/1039

are the same as those mentioned above in connection with Figure 31 have been described. The two central processing units 502 and 504 share an external timer 512. This timer can, for example, be the same as that in the Connection with fig. 35 has been described. The timer must be synchronized with both central units, this ensures that the central processing units operate out of phase. This is done by using interrupt input signals achieved. Every time

a central unit is interrupted, for example if the central unit 504 by an interrupt signal B is interrupted by 530, the interrupt signal changes the ready input signal A to the central processing unit 502. a low signal value. This causes the central unit to work 502 enters a wait state when it reaches the end of a polling subcycle. The waiting mode the central unit has been described above. When the central processing unit 502 is in the waiting mode is, the gate 522 provides a signal to the latch 526 indicating that the wait mode has been reached. The latch 526 is reset by the gate 522. The central unit 504 is of the Interrupt request signal B interrupted. this supplies a signal to coupling device 512 (which is shared by central processing units 502 and 504), indicating that an interruption requirement has been confirmed. When the central processing unit 504 receives the interrupt request * * signal detects, it issues an interrupt acknowledge signal. This output is applied to gate 534, which sends a signal to hold circuit 528 indicating that the need for interruption has been recognized, and that the central processing unit 502 resumes operation

0 9 815/1039

Α3 0

can. When the signal is applied to hold circuit 528 takes the signal on the ready signal line of the central unit 502 has the signal value 1, and the central processing unit begins its execution cycle during this period. The advantage of using two central units is that the programmer can split his program into two sections so that these run quickly? when both central processing units have finished their execution, the program can end of the two program sections can be combined to form a common result. Other advantages are that two programs with simultaneous use of a common memory, the common data sections can contain, can be executed. The. Direct access storage sections must of course be programmed that way be that the central units cannot destroy the information assigned to one another.

309815/1039

Claims (40)

Claims . 1J 'data processing arrangement with a single external Memory, characterized by a) a first and a second, each on a single one Central unit made of semiconductor material, which has a working cycle, a first section, in which the central unit has access to the external memory, and a second section, in which the central processing unit processes data, contains, each central processing unit a Contains memory registers for storing the results of data processing operations, b) means for synchronizing the operation of the first and second central units such that the first section of the operating cycle of the first central unit is simultaneous with the second section of the duty cycle of the second central unit occurs, and c) a coupling device connected to the first and the second central unit for coupling external inputs to the central units and for supplying the output variables of the arrangement, 2. Arrangement according to claim 1, characterized by a with the first and the second central unit and data storage device connected to the coupling device for storing the command executed by the associated central unit and for selecting the contents of the accumulator register. 309815/1039 ASl 3. Arrangement according to claim 2, characterized in that the external memory is a random access memory contains. 4. Arrangement according to claim 1, characterized in that that the synchronization means a switching device for putting a central unit in a Waiting state in response to a first, the other central unit for access to the external one Contain memory selecting input signal that in the synchronization devices one of the first central unit with the second central unit coupling detector device is provided which in response to the switching of one central unit to the waiting state to the other central unit applies a trigger signal and that the synchronization devices logic means includes in response to termination of the first section during the duty cycle of the other central unit the one central unit is in a standby state the second part of the duty cycle of the other central unit. 5. Arrangement according to claim 1, characterized in that the coupling device has a connection a parallel bus between the central processing units and the memory that contains a device for sampling the output current of the central units and the external memory is provided and that this current is based on the values of the Transjfetor-Transistor-Logik device amplifying for inputs via the bus to the external memory and the central processing units is provided. 30981 5/1039 AS S 6. A method of operating a completely synchronous data processing arrangement with an external memory which is shared by a first and a second central processing unit, each of which has an operating cycle comprising a first section in which the central processing unit can carry out a memory access and a second section _r in which the central unit processes data received during the first section, the central units and the external memory being connected to one another via a common parallel bus, characterized in that, a) that the operation of the first and the second central unit are synchronized so that they are completely out of phase, and b) that simultaneously separate programs in the
first and in the second central processing unit. 7. The method according to claim 6, characterized in that when synchronizing the operation of the first and the second central unit, the first central unit is switched to a waiting mode in response to a signal which selects the second central unit for memory access, so that it is determined when the first central unit enters the waiting mode that the second central unit is supplied with a trigger signal which enables it _{to cause the first section of its working cycle to find memory data for:} the execution of a first program, that the termination of the first section of the work- 309815/1059 ASH cycle is determined that to the first central unit a trigger signal is applied that enables it, to take action during the first section of their work cycle to exercise memory access for the execution of a second program, and that the first central unit exercises memory access at the same time as the second central unit processes the data it found during the previous part of its work cycle Has. 8. The method according to claim 7t, characterized in that the output current on the bus of the central processing units or of the memory is sampled that this Current on the values of the transistor transit gate logic is amplified and that the corresponding voltages as input signals to the memory or to the central processing units be created. 9. Timing circuit for synchronizing asynchronous Signals with the operation of a central unit in a completely synchronous central unit a data processing arrangement, characterized by a) a device for determining the presence of the asynchronous signal and for generating one individual output pulse depending on the asynchronous signals, b) a memory device for receiving the output pulse and storing it until a preselected time interval of the central unit occurs and 309815/1039 c) one coupled to the storage device
Logic device for receiving the stored
Output pulse for synchronization, des
Signal with a selectable time interval
the central unit. 10. Time control circuit according to claim 9, characterized in that the Peststellungseinrichtung the time control circuit contains an edge detector which ' determines the transition from one logical signal value to the other logical signal value and as Ant word then generates a single output pulse. 11. Interrupting circuit for selectively interrupting the normal operation of a fully synchronous operating Central unit of a data processing arrangement, characterized, a). that a circuit arrangement is provided which, in response to an optional output signal,
that indicates that the central unit will be interrupted sdII, a single output pulse off. b) that a device for storing the output pulse is provided until the central processing unit has reached a predetermined point in its duty cycle at which an interrupt is acknowledged will, and c) that a programmable logic field to receive the .Output pulse and for the delivery of an output signal is provided at a selected time during the working cycle of the central unit, 30961 5/1039 the output signal causing the normal operating cycle of the central processing unit to be interrupted and triggers the input of external commands without destroying the content of the central unit. 12. Circuitry to enable the use of a random access memory or a serial one Memory without changing an external circuit in a data processing arrangement with a central unit and an external memory that emits a trigger output signal when an addressed memory location corresponds to the desired memory location, characterized in that a timer circuit is provided is that sequentially and continuously a first central signal to trigger access to the Central unit to the external memory and a second central signal to trigger the processing of the generated data found from the memory in the course of the first central signal. 13. A method for operating a data processing arrangement with a central unit together with several external storage devices that are connected to the central unit via a common parallel bus, characterized in that address bits with low significance, write data, address bits with high Place value and read data sequentially on a common Manifold are transmitted and that all channels of the parallel manifold without duplication or tripling of the bus line to match the addressable area of the external memory unit 309815/1039 - 2142912 451 be used, taking the use of the common Collective line takes place within the cycle time of the data processing arrangement. 14. The method according to claim 13, characterized in that the address bits with low significance during the Transmission of the high priority address bits are decoded. 15. Internal memory section with a program address stack operating on the principle of "last input -> ■ first output" in a data processing arrangement with a central processing unit together with several external memory units, the central processing unit being connected to a control unit, a parallel arithmetic unit, an instruction register and a random access memory via a common parallel manifold, contains, characterized in, a) that a first group of dynamic random access memory registers is intended to store low-order address bits, b) that a second group of dynamic random access memory registers is provided, each with the first group of registers for storing the address bits is associated with high priority, and c) that a two-way static counter to select a pair from the first and second Group is provided for puncturing as a program address register, with the remaining register pairs of the first and second group one working according to the principle last entered - first issued 3 0 9 8 15/1039 - Ml - Forming address stacks, whereby in response to a subroutine call the counter increases by one Unit in a first direction for selecting an adjacent pair of the data registers as new program address advances, with the previous pair of data registers containing the address for a return command, which saves the counter's port circuit by one unit in causes the opposite direction. 16. Data processing arrangement with an arithmetic unit for carrying out arithmetic and logical operations in response to coded commands, indicated by a) a decoding device for receiving the encoded commands and for delivering several groups of Output control signals corresponding to the arithmetic that can be carried out by the data processing arrangement and logical operations and b) a single logic circuit for receiving the plurality of groups of output control signals and for optionally performing logical operations in accordance with the selected operation. 17. Arithmetic unit according to claim 16, characterized in that that the logic circuit contains a plurality of field effect transistors with an insulated gate electrode, which are so interconnected are connected that they carry over the logical operations of addition, addition, the Subtraction, the subtraction with borrowing, the AND link, the OR link, the non-equivalence 309815/1039 - IM $ 45 link and the comparison function. 18. Arithmetic unit according to claim 17, characterized in that the field effect transistors with an insulated gate electrode a first composite or-and-not gate "which is connected to the decoding device in such a way that it is the subtrahend of a subtraction operation negates that with the output of the composite ^ gate a first logical NAND gate for performing an MD link and for forming the carry generation signal for addition and Subtraction operations is connected that with the output of the composite gate a NOR gate to carry out a logical OR link is connected, that to carry out the; Non-equivalence operation and for generating a carry-propagation expression for addition and subtraction operations a second gate is connected to the NOR gate, which is the negated non-equivalence link executes that with the output of the first NAND gate and with the NOR gate a second logic NAND gate is connected, which controls the output signals of the OR and 'AND gates, that with the output of the -, NOR gate and with the Output of the first negating antivalence gate a second negating antivalence gate for control of the output signal from the non-equivalence link and to form the sum η output signal of the associated Bits of the arithmetic unit is connected, and that a carry circuit is connected to the first NAND gate which generates a carry signal at one bit of the arithmetic logic unit and between bits of the arithmetic unit for 309 8-1 5 / 10-39 -IN THE- 410 Add, subtract and compare operations transmits a carry signal. 19. Control unit in a synchronous central unit, which has a working cycle that starts in a first sub-cycle, in which the central unit can access an external memory, and in a second sub-cycle, in the course of which the central unit off ₍ data taken from the memory and Commands processed, subdivided, characterized in that a) that for generating the first and second partial cycle times a circuit arrangement is provided, which a programmable logic field for optional Determination of the duration of the partial cycles, b) that to receive commands from the external memory and. for generating output signals as required for the respective commands Operation of the central unit an instruction decoding device is provided which contains a programmable logic field that contains the operation resulting from the selected instructions the central unit optionally determines c) that with the circuit arrangement and with the instruction decoding device a cycle timer device is connected which indicates the number of cycles required for the respective commands the central unit controls, and d) that for receiving input signals from the circuit arrangement, the instruction decoding device 309815/1039 41 4 and the cycle timer means and for generating of control signals for synchronizing the operation of the central unit a timing device is provided, which contains a programmable logic field that the sequence of the Operation of the central unit optionally determines. 20. tail unit for a synchronous central unit according to claim 1, characterized in that the fixed. setting of the state of the arithmetic operations carried out by the central unit by parts of the plague of the logical signal value of selected bits in the accumulator of the central unit a status de- ' coding device is provided, which contains a programmable logic field, which optionally determines the wel- ' before bits of an instruction allow a state decode operation. 21. A method of manufacturing the tail unit of a synchronous central processing unit with a state timer circuit to generate a first section of a work cycle, in the course of which the central unit can exercise access to the external memory, as well as a second section of the operating cycle, in the course of which the central unit can process the data found in the memory with a command sde coding circuit for generating control signals for the central unit in response to this executable instructions, with one to the instruction decoding circuit connected cycle timer to control the number of times for a selected command required cycles and with a timing circuit 309815/1039 22A2912 IN THE - to set the state of the accumulator register the central unit following an arithmetic operation, characterized in that • a) that a programmable logic field as part of the State timer circuit is established and b) that the gate circuits of the field to control the duration of the first and second sections of the Duty cycle of the central unit can be formed optionally. 22. The method according to claim 21, characterized in that a) that a second programmable logic field is established as part of the instruction decoding circuit will and b) that the gate circuits of the second programmable logic field for the optional control of the Output signals given in response to a Command code are generated, can be formed optionally. 23. The method according to claim 22, characterized in that a) that a third programmable logic field as Part of the cycle timer circuit is established and b) that the gate circuits of the third programmable logic field to control the number of Duty cycles of the central processing unit required for a given instruction code are optionally formed will. 309815/1039. -Ml - 24. The method according to claim 23 ,. characterized, a) that a fourth programmable logic field is established as part of the timing control circuit
and Id) that the gate circuits of the fourth programmable Logic field for controlling the sequence of operation of the synchronous central unit optionally are formed. ... 25. The method according to claim 24, characterized in that a) that a fifth programmable logic field is established as part of the state decoder circuit will and b) that the gate circuits of the fifth programmable logic field to carry out the control, which bits of an instruction are used to permit a state decode operation, optionally are formed. 26. Circuit for setting the parity between several logical signals, characterized in that a) that between a first node and a first clock voltage source a first pair of in Series-connected field effect transistors are inserted, the gate electrodes for receiving a first have the logic signal and the complement of a second logic signal, b) that between the first node and the first clock voltage source a second pair of in Series-connected field effect transistors inserted 309815/1039 is, the gate electrodes to receive the complement of the first logic signal and the second logic signal, and c) that a circuit arrangement is provided that the first node simultaneously with the Application of the first and second logic signals, to a negative reference voltage, so that the node when the first and second logic signals have opposite logic signal values have, is discharged, so that at the node a corresponding to the odd parity logical signal value 1 arises. 27. A circuit according to claim 26, characterized in that the circuit arrangement for precharging the first circuit point contains a field effect transistor connected between the node and the negative reference voltage, the gate electrode of the Field effect transistor with the first clock voltage source connected is. 28. Circuit according to claim 27, characterized in that a) that a third pair between a second node and the first clock voltage source of field effect transistors connected in series is inserted, the gate electrodes for reception of the first and second logic signals, b) that between the second node and the first clock voltage source is a fourth pair of field effect transistors connected in series 309815/1039 -IN THE- US is inserted, the G-ate electrodes for reception of the complement of the first and second logic signals, and c) that a circuit arrangement is provided that the second node simultaneously with the Application of the first and second logic signals to a negative reference voltage precharges so that then if the first and second logical sig-,. nale have the same 'logical signal values, the second node is discharged so that at the second node one of the even parity corresponding logical signal value 1 arises. 29. Parity circuit according to claim 28, characterized in that that the circuit arrangement for precharging the second node contains a second field effect transistor with an insulated gate electrode which is inserted between the second node and the reference voltage source, the gate electrode of the second field effect transistor with the clock. source is connected. 30. Parity circuit according to claim 29, characterized in that a) that a fifth and a sixth field effect transistor together with an electrode at the first circuit point with the other electrode connected to a third "or to a fourth circuit point are, the fifth and the sixth field effect transistor each having a gate electrode which 309815/1039 receives a third input signal or the complement of the third input signal, b) that a seventh and an eighth field effect transistor together with. an electrode at the second node and connected with the other electrode to the third or fourth circuit point are, the seventh and the eighth field effect transistor each having a gate electrode which receives the complement of the third input signal or the third input signal, and c) that a circuit arrangement is provided that the third and the fourth circuit point simultaneously with the application of the third input signal to a negative reference voltage, so that either the third node or the fourth Node is selectively discharged according to the logical signal value of the third input signal, wherein the discharged node corresponds to the odd parity or the even parity. 31. Carry propagation circuit for an arithmetic and logic unit of a data processing arrangement, which is dependent on Addition and subtraction operations generate a logical carry signal, characterized by a) a circuit arrangement for precharging the carry signal terminals of the arithmetic unit to a reference potential during a phase of a clock signal and to) a circuit arrangement for optionally discharging these terminals depending on the logical signal value of the carry signal. 309815/1039. -IN THE- 32. · Circuit for setting an output signal on a bus and for generating a voltage input signal for the collecting line in a data processing arrangement, which contains a central unit together with several external storage units, which are connected to the central unit via the common parallel manifold, one after the other Low significance address bits, write data, Significant address foits and read 'transmits' data, identified by a) a first switching device for generating a bus current during a first phase a clock from a selectable data source, b) means for sensing the current on the manifold during the first phase, c) one on the output signal of the scanning device responsive hold circuit that is triggered during one phase and when this one ends Phase is set to a selected state depending on the output signal, d) a logic gate for receiving the output signal of the hold circuit with a control terminal responsive to a second phase of the clock, the logical Gate transmits the output signal 'of the holding circuit during the second phase, e) that an arrangement for generating a Sparinungssignals on the logic gate and the bus line Collective line depending on the value of the output signal of the logical gate is connected and 309815/1039 4I.S f) that a second switching device is provided, which is responsive to a second phase such that the voltage signal is applied to a selected data destination is transmitted. 33. Circuit according to Claim 32, characterized in that that the first and second switching devices field effect transistors with insulated gate electrode, the gate electrodes for receiving the first and second clock signals. 34. A circuit according to claim 33, characterized in that the device for sampling the current at the The bus contains a differential amplifier provided with a first resistor connected to a first bias voltage source. 35. Circuit for precharging a collecting line during an operating phase and for optionally discharging the collecting line during the time interval between the "one operating phase" and a second operating phase depending on input signals from the control components of a central unit connected to one another via the collecting line in a data processing arrangement with the central unit and with several external ones memory units, the Zen ^x traleinheit on a single die, connected to the common parallel bus llechenwerk parallel-in, contains a random access memory, an instruction register and a tail unit, characterized in that 309815/1039 a) that between the manifold and circuit dimensions first and second transmission gates connected in series each having control electrodes, the first transmission port to the bus connected, b) that to connect a first voltage source with a first switching device for precharging the bus during a first phase of a clock system the voltage of the manifold is provided, c) that for transmitting one of the desired logical value on the bus to the control electrode of the second transmission gate a second switching device is provided during the first phase, d) that to the control terminal of the first transmission gate a logic circuit device is connected which is responsive to the first phase to be the first transmission gate for the duration of the first phase biases into a non-conductive state, and e) that for the optional discharge of the bus at the end of the first phase, a circuit arrangement is provided. 36. Central unit., A data processing arrangement which is monolithically integrated on a single plate, characterized by . a) a parallel manifold, b) a coupling device connected to the manifold to transfer data between the bus and an external circuit, 309815/1039 c) a command register that is used to receive commands transmitted over the bus the collecting line is connected, d) a parallel arithmetic unit connected to the collecting line, e) a random access memory connected to the bus, which forms several data registers, and f) one with the command register and the bus connected tail unit for synchronizing the operation of the central unit in such a way that the successive Use of the bus between the command register, the arithmetic unit and the random access memory is controlled. 37. Central unit according to claim 36, characterized in that the bus comprises eight bits and that the Random access memory contains multiple 8-bit registers. 38. Central unit according to claim 37, characterized in that two of the 8-bit registers to enable one 16-bit addressing selected as program address register that allow the addressing of up to 64K bytes of the external memory. 39. Central unit according to claim 38, characterized in that that several pairs of the 8-bit registers to form a `` last entered - first output '' principle working address stack are combined to allow 16-bit addressing and subroutine address storage be made possible. 309815/1039 40. Central unit according to claim 39, characterized in that a) that the random access memory has fourteen 8-bit registers contains, the formation of a seven-step, according to the principle "last entered - first output" working program address stack are combined, b) that two 8-bit random access memory registers are combined "in such a way that they contain a program address · - ' form register for storing a 16-bit address, and c) that eight 8-bit general purpose registers in the 'direct access memory are included, one of which forms the accumulator register of the central unit.