GB2175109A - Digital code detector circuits - Google Patents

Abstract

A parity checker circuit for detecting parities (odd, even or pattern) of code combinations of n-bit binary digital codes. A circuit for detecting even parity of 4-bit codes (i.e. codes with 0, 2 or 4 bits of binary '1' value) comprises a set of four input leads (15 to 18) with associated inverters (19 to 22) to supply inverse code combinations as well as true input code combinations to a lattice gate structure composed of field- effect transistors (1 to 12). A current path is completed through the gate structure by selective turn-on of the transistors to drive an output circuit 27, only in response to input code combinations having 0, 2 or 4 bits of binary '1' value. Odd or even parity, or pattern, may be detected in connection with 8-bit codes (Figs. 4, 5). <IMAGE>

Description

SPECIFICATION Digital code detector circuits This invention relates to digital code detector circuits of a type known as parity checker circuits which are suitable for detecting errors in binary digital codes represented by a set of data signals of each of which a first logic level represents one binary value (say high=1) and a second logic level represents the opposite binary value (say low=O).

In digital data systems, parity checker circuits are frequently used for various error detection schemes. One such scheme which is in common usuage provides a so-called "odd" parity check of 7-bit ASCII data codes by using an eighth bit which is added to each 7-bit data code and has a binary 1 value or a binary 0 value appropriate for making an odd number of the total number of, say, 1-bits in the data code. The total number of 1-bits in each received 8-bit data code is then checked by a parity checker circuit and the detection of an error is assumed in repect of any received code which does not satisfy the "odd" parity check. Equivalently, an "even" parity check can be performed by using the extra parity bit to make an even number of the total number of bits in the data codes.Combinations of parity checker circuits may give error correction as well as error detection, for example as in the case of Hamming coded data.

Conventionally, parity checker circuits are designed using tree structures of exclusive-OR gates.

One example of such a parity checker circuit for detecting "odd" parity in 8-bit codes is shown in Fig. 1 of the accompanying drawings. This parity checker circuit comprises seven two-input exclusive-OR gates G1 to G7 of which, each of the gates G1 to G4 has its two inputs connected to receive a respective two of the eight bits b1 to b8 of 8-bit codes. The gates G1 and G2 have their outputs connected to respective inputs of the gate G5 and the gates G3 and G4 have their outputs connected to respective inputs of the gate G6. In turn, the gates G5 and G6 have their outputs connected to respective inputs of the gate G7. The output of the gate G7 has a binary 1 (high) value when there are 1, 3, 5 or 7 bits of binary 1 value in an applied 8-bit code.

It is an object of the present invention to provide an improved parity checker circuit which lends itself to a specific form of integrated circuit implementation.

According to the invention, a parity checker circuit of the type set forth above is characterised by comprising, a first set of n-input leads for receiving respective bits of an n-bit codes, inverter means for producing from a received (true) code an inverse code whose bit values are opposite to those of the true code, a second set of n-input leads for receiving respective bits of the inverse code, an output circuit for producing a parity check signal, and a lattice gate structure composed of AND-gates each having an enabling input, a signal input and a signal output, and arranged in accordance with a required parity, said lattice gate structure comprising first and second series arrangements of AND-gates connected in parallel, the junctions of successive pairs of AND-gates in each series arrangement being cross-connected via further AND-gates to junctions of successive pairs of AND-gates in the other series arrangement, all the AND-gates having respective enabling inputs connected selectively to input leads of the two sets to receive bits of one value as anabling signals, the lattice gate structure being operable to provide a path between the output circuit and a driving source therefor in response to a received code having a number of bits of said one value that satisfy the parity check.

In carrying out the invention, the lattice gate structure can be organised to provide "even" parity, or "odd" parity, or to provide for the detection of different parity patterns.

In the case of "even" parity the lattice gate structure would be organised as follows: (a) the input leads of the second set are connected to the enabling inputs of respective ANDgates which form the second series arrangement of AND-gates, (b) the first and last input leads of the first set, and the input leads of the second set other than the first and last, are connected to the enabling inputs of respective further AND-gates which form the first series arrangement of AND-gates, and (c) the remaining (intermediate) inputs leads of the first set are each connected to the enabling inputs of a respective two other AND-gates which have their signal inputs respectively connected to the first and second series arrangements of AND-gates at the junctions of the two-AND-gates whose enabling inputs are connected to the corresponding and to the next (lower) input leads of the second set, the signal outputs of said two other AND-gates being respectively connected to the second and first series arrangement of AND-gates at the junctions of the AND-gates whose enabling inputs are connected to the corresponding and to the next (higher) input leads of the second set.

It is to be understood that the words lower and higher as used above are to be interpreted in a relative sense having regard to the binary order allocated to the bits of received codes.

For "odd" parity, the positions in the first and second series arrangements of AND-gates whose enabling inputs are respectively connected to the last input leads of the first and second sets are reversed.

To provide for the detection of different parity patterns, the lattice gate structure comprises an additional series arrangement of AND-gates for each additional parity bit to be detected, with further AND-gates to provide the cross-connections between the additional series arrangement(s) and the first and second series arrangement of AND-gates.

A A parity checker circuit according to the invention is eminently suited for implementation as an integrated circuit that includes what will be termed an "array logic structure" which can be used to form so-called combinational logic circuits (that is, circuits which can perform combinations of logic functions, such as AND and OR functions.

For the purposes of the present specification an "array logic structure" is hereindefined as a plurality of controllable insulated gate field effect transistors (IGFETS) which are formed at selected intersections of an array consisting of a plurality of rows of series-connected gate regions and a plurality of columns of surface regions which at each selected intersection define source and drain regions for the transistor which is formed there, an electrical path being formed at each other (non-selected) intersection, at least in use of the structure, to effectively short circuit the intersection in respect of the relevant surface column region.

In one known form of this array logic structure, the controllable transistors at the selected intersections are formed as n-channel IGFETS of the enhancement type, and at the non-selected intersections there are formed n-channel IGFETS of the depletion type to provide the electrical paths which short circuit (or bridge) these latter intersections in the direction of the relevant surface region column. Further information concerning such an array logic structure can be found in United Kingdom patent specification 1 575 741.

In order that the invention may be more fully understood, reference will now be made by way of example to the accompanying drawings, of which: Figure 1, as aforesaid, shows an example of a known parity checker circuit formed by a tree structure of exclusive-OR gates; Figure 2 shows one embodiment of a parity checker circuit according to the invention; Figure 3 shows a schematic diagram of the circuit shown in Fig. 2; Figures 4 and 5 show schematic diagrams of respective further embodiments of parity checker circuits according to the invention; Figure 6 shows an output circuit for the three embodiments; and Figures 7 and 8 are schematic diagrams which illustrate the limitations of the use of an array logic structure for a conventional implementation of a parity checker circuit.

The parity checker circuit shown in Fig. 2 of the drawings comprises a lattice gate structure in the form of an array of twelve gating transistors 1 to 12 connected between a pair of drive transistors 13 and 14 across supply terminals (+V), (OV). The array has a first set of four input leads 15 to 18 for receiving true data signals. These true data signals represents 4-bit binary codes and can have either a high logic level or a low logic level, corresponding to binary 1 and 0 values, respectively. Inverse data signals which are derived from the true data signals by respective inverters 19 to 22 are also fed to the array over a second set of four input leads 23 to 26. The array drives an output circuit 27 which includes an input storage capacitor 28.

In operation of the circuit, the drive transistors 13 and 14 receive pulses K1 and K2, respectively, at their gates. These pulses K1 and K2 are two phase in that they occur alternately without overlap in time. The occurrence of a pulse K2 switches on transistor 14 for the period of this pulse and the capacitor 28 is pre-charged to the voltage +V which corresponds to the high logic level. On the occurrence of the immediately following pulse K1, the transistor 13 is switched on, by which time the transistor 14 will be switched off again. In dependence on the logic levels on the two sets of input leads 15 to 18 and 23 to 26, different combinations of the transistors 1 to 12 can be switched on and off to complete or not a number of paths through the array.With the transistor 13 switched on, the capacitor 28 will discharge over any path which is completed through the array to the voltage OV which corresponds to the low logic level. If no discharge path is established through the array when the pulse K1 occurs, the capacitor 28 will retain the high logic level. In the output circuit 27 the prevailing logic level is inverted by an inverter 29 to produce the current logic level at an output 30 of the output circuit 27.

As implemented by an array logic structure, the transistors 1 to 12 can be enchancement type IGFETS. At each of the intersections in the array where two crossover leads are electrically insulated from each other, depletion type IGFETS can be used to form the intersection.

A convenient way illustrating the circuit of Fig. 2 is by means of a schematic diagram of the form shown in Fig. 3. In this schematic diagram, which will now be used to further describe the operation of the parity checker circuit, the gating transistors forming the array are represented by the small rectangles 1 to 12, respectively. At each intersection of the array where no gating transistor is provided, electrical isolation between the two crossover leads is assumed. Because the output circuit 27 receives a low logic level in response to "gated'' high logic levels (i.e.

when a discharge path is completed), the input to the output circuit 27 is given an "inverter" circle to signify that the low logic level corresponds to a binary 1 input signal. The "inverter" circle at the output 30 of the output circuit 27 signifies that a (high logic level) binary 1 signal is produced in response to a binary 1 (low logic level) input signal. The two-phase action of the pulses K1 and K2 is assumed to be implicit in the operation. Further consideration of the invention will now be with reference to the schematic diagram of Fig. 3, and also those of Figs.

4 and 5.

The parity checker circuit represented by the schematic diagram of Fig. 3 is for checking "even" parity of 4-bit codes represented by data signals applied to the set of input leads 15 to 18; that is, the circuit will produce an output signal to signify "even" parity for any 4-bit input code combination containing an even number of 1s (i.e. 0, 2 or 4). The following TABLE gives the logic gating within the circuit for the sixteen different possible code combinations of a 4-bit input code.

TABLE Gating Parity Check Input Leads Transistors 1 yes, O=no 15 16 17 18 23 24 25 26 (A) (B) (C) (D) ca, (B) (C) (D) 0 0 0 0 1 1 1 1 2,5,6,9,10,12 1 O 0 0 1 1 1 1 0 2,5,6,9,10,11 0 0 0 1 0 1 1 0 1 2,5,6,7,8,12 0 0 0 1 1 1 1 0 0 2,5,6,7,8,11 1 0 1 0 0 1 0 1 1 2,3,4,9,10,12 0 0 1 0 1 1 0 1 0 2,3,4,9,10,11 1 0 1 1 0 1 0 0 1 2,3,4,7,8,12 1 0 1 1 1 1 0 0 0 2,3,4,7,8,11 0 1 0 0 0 0 1 1 1 1,5,6,9,10,12 0 1 0 0 1 0 1 1 0 1,5,6,9,10,11 1 0 0 1 0 0 1 0 1 1,5,6,7,8,12 1 1 0 1 1 0 1 0 0 1,5,6,7,8,11 0 1 1 0 0 0 0 1 1 1,3,4,9,10,12 1 1 1 0 1 0 0 1 0 1,3,4,9,10,11 0 1 1 1 0 0 0 0 1 1,3,4,7,8,12 0 1 1 1 1 1 0 0 0 0 1,3,4,7,8,11 1 In the above TABLE the first and second columns give the 4-bit input (true) and inverse code combinations A, B, C, D and A, B, C, D at the two sets of input leads 15 to 18 and 23 to 26, respectively, the third column gives the gating transistors which are enabled for each 4-bit input code combination, and the fourth column gives the parity check signal from the output circuit 27 for each 4-bit input code combination. Consideration of the TABLE shows that only each of the 4-bit code combinations with an even number of bits of binary 1 value enables a pattern of gating transistors that provides a respective conductive path through the array to cause the output circuit to produce a binary 1 signal.It can be seen that the array is effectively composed of two series arrangements of gating transistors extending through the array, with additional gating transistors being provided to cross-couple the series arrangements at the junctions of adjacent transistors therein. A completed conduction path through the array is always diverted twice from one series arrangement to the other. In general, in an of appropriate size for identifying "even" parity of n-bit code combinations, where n is an even number, a completed conduction path through the array would be diverted from one series arrangement of gating transistors to the other an even number of times.

The schematic diagram of Fig. 4 represents a parity checker circuit according to the invention which has a set of eight input leads 31 to 38 for receiving true 8-bit code combinations A to H and a set of derived input leads 39 to 46 for receiving the inverse 8-bit code combinations A to H. The circuit has a lattice gate structure LG which is organised to identify "odd" parity in received 8-bit code combinations A to H, that is, the circuit will complete a conductive path through the array to cause the output circuit 27 to produce a binary 1 signal, which signifies "odd" parity, for an received 8-bit code combination which has a odd number of bits of binary 1 value. It would not be practical to list all the 256 code combinations of an 8-bit code, as has been done for a 4-bit code in the above TABLE.However, it can be seen that, in general, the array in the circuit of Fig. 4, like the array in the circuit of Fig. 3 already described, has effectively two series arrangements of gating transistors extending through the array, with additional gating transistors being provided to cross-couple the junctions of the adjacent transistors therein. In this instance, a completed condition path through the array is diverted from one series arrangement to the other an odd number of times. For example, an input (true) code combination 01100010 and the inverse code combination 10011101 would enable all the gating transistors which have a vertical arrow adjacent to them. Of these transistors, those which are drawn in bold lines in Fig. 4, would complete the conduction path shown in broken line through the array.

Parity checker circuits as thus implemented in accordance with the invention for signify "odd" or "even" parity, can be combined in conventional ways to produce Hamming checker circuits.

It is also possible to provide parity checker circuits according to the invention when can detect "parity patterns" in received n-bit code combinations. Fig. 5 shows a schematic diagram of such a parity checker circuit which can identify any 9-bit input code combination containing 0, 3, 6 or 9 9 bits of binary 1 value. For this circuit, the lattice gate structure LG effectively comprises three series arrangements of gating transistors, with additional transistors mutually cross-coupling the junctions of additional transistors of the three series arrangements.In this instance, for example, an input (true) code combination 101101110 (containing six 1 's) and the inverse code combina tion 010010001 would enable all the gating transistors which have a vertical arrow adjacent to them, and a conduction path shown in broken line would be completed through the transistors which are drawn in bold lines in Fig. 5.

For the sake of completeness in the description, Fig. 6 shows a typical two-phase dynamic circuit which can be used as the output circuit and which is operable synchronously with an array logic structure. The circuit shown in Fig. 6 comprises both enhancement and depletion type insulated gate field effect transistors and is assumed to be implemented as an integrated circuit structure using n-channel technology. For this assumption, the array logic structures with which it is associated would, of course, be implemented using the same technology. Supply rails 47 and 48 of the circuit are connected across a supply voltage (+V), (OV). The circuit has an input stage comprised by two transistors 49 and 50, an intermediate stage comprised by two transistors 51 and 52, and an output stage comprised by two transistors 53 and 54.

A first transfer transistor 55 is connected between an input 56 and the input stage, and a second transfer transistor 57 is connected between the input stage and the output stage. The output stage provides a high (1 = +V) logic level at the output 58, in response to a low (1=OV) logic level at the input 56. The transistors 50, 52, 54, 55, and 57 are enchancement type IGFETS. The transistors 49, 51 and 53 are depletion type IGFETS and serve as loads for the transistors 50, 52 and 54, respectively.

The circuit of Fig. 6 is driven by the two clock pulses K1 and K2, of different phases, which are used to drive an associated array logic structure. These clock pulses K1 and K2 are applied respectively to the gates of the transfer transistors 55 and 57. In operation of the circuit, the input 56 is at either a high (O=+V) logic level or a low (1=OV) logic level, as determined by the associated array logic structure, the operation of which corresponds to that described previously with reference to Fig. 2. On the occurrence of a clock pulse K1, the transfer transistor 55 is switched on and the prevailing logic level at the input 56 is transferred to the gate of the transistor 50. At the end of the clock pulse K1, the transfer transistor 55 is switched off and the prevailing logic level is maintained at the gate of the transistor 50 by a capacitor 59.The transistor 50 is switched on, or remains switched off, according as the prevailing logic level at the input 56 is the high logic level or the low logic level, to provide the alternate logic level at the junction of transistors 49/50. On the occurrence of the immediately following clock pulse K2, the transfer transistor 57 is switched on and said alternate logic level is transferred to the gate of the transistor 52. At the end of the clock pulse K2, the transfer transistor 57 is switched off and said alternate level is maintained at the gate of the transistor 52 by a capacitor 60. The transistor 52 is switched on, or remains switched off, according as said alternate logic level is the high logic level or the low logic level.The transistor 54 has its gate connected to the junction of transistors 51/52 and thus provides the alternate logic level at the output 58. A capacitor 61 is provided to compensate for possible degradation of the logic level at the input 56. The capacitors 59, 60 and 61 are shown in dotted lines, because it is possible that each can be dispensed with if the gate capacitance of the relevant transistor suffices to perform their function.

Parity checker circuits according to the invention which are implemented using array logic structures as hereinbefore defined, are smaller than conventional parity checker circuits imple mented with the same technology. In order to illustrate this significant advantage which the present invention affords, Figs. 7 and 8 have been included. In Fig. 7, the A or B only , X logic function of the exclusive-OR gate shown at (a) is equivalent to the AND/OR logic function AO+B=A.B+A.B X of the logic gate array shown at (b). If this logic gate array is used as a logic element to implement a parity checker circuit which is equivalent to the known 8-bit "odd" parity checker circuit shown in Fig. 1, then a circuit as represented by the schmatic diagram in Fig. 8 results. The lattice gate structure LG of this circuit required eight columns of sixteen transistors and is too large for high speed applications. Furthermore, it may have to be imple mented as a number of smaller arrays joined together, which would still further decrease its speed of operation. Since high speed operation is often a critical requirement is parity checking data codes, such a conventional implementation of a parity checker circuit may be not satisfactory. In the schematic diagram of Fig. 3 which has already been discussed and which is the equivalent 8-bit "odd" parity checker circuit according to the invention, the lattice gate structure requires only four columns of sixteen transistors. For single bit "odd" or "even" parity, the lattice gate structure is always the same width irrespective of the number of bits of the input codes to be tested.

Claims (6)

1. A parity checker circuit for detecting errors in binary digital codes represented by a set of data signals of each of which a first logic level represents one binary value and a second logic level represents the opposite binary value, which parity checker circuit is characterised by comprising, a first set of n-input leads for receiving respective bits of an n-bit code, inverter means for producing from a received (true) code an inverse code whose bit values are opposite to those of the true code, a second set of n-input leads for receiving respective bits of the inverse code, an output circuit for producing a parity check signal, and a lattice gate structure composed of AND-gates each having an enabling input, a signal input and a signal output and arranged in accordance with a required parity, said lattice gate structure comprising first and second series arrangements of AND-gates connected in parallel, the junctions of successive pairs of AND-gates in each series arrangement being cross-connected via further AND-gates to junctions of successive pairs of AND-gates in the other series arrangement, all the AND-gates having respective enabling inputs connected selectively to input leads of the two sets to receive bits of one value as enabling signals, the lattice gate structure being operable to provide a path between the output circuit and a driving source therefor in response to a received code having a number of bits of said one value that satisfy the parity check.

2. A parity checker circuit as claimed in Claim 1, characterised in that the lattice gate structure is organised as follows: (a) the input leads of the second set are connected to the enabling inputs of respective ANDgates which form the second series of AND-gates, (b) the first and last input leads of the first set, and the input leads of the second set other than the first and last, are connected to the enabling inputs of respective further AND-gates which form the first series arrangement of AND-gates, and (c) the remaining (intermediate) input leads of the first set are each connected to the enabling inputs of a respective two other AND-gates which have their signal inputs respectively connected to the first and second series arrangement of AND-gates at the junctions of the two AND-gates whose enabling inputs are connected to the corresponding and to the next (lower) input leads of the second set, the signal outputs of said two other AND-gates being respectively connected to the second and first series arrangement of AND-gates at the junctions of the ANDgates whose enabling inputs are connected to the corresponding and to the next (higher) input leads of the second set.

3. A parity checker circuit as claimed in Claim 2, characterised in that in the first and second series arrangement of AND-gates, the positions of the AND-gates whose enabling inputs are respectively connected to the last input leads of the first and second sets are reversed.

4. A parity checker circuit as claimed in Claim 1, characterised in that the lattice gate structure comprises an additional series arrangement of AND-gates for each additional parity bit to be detected, with further AND-gates to provide the cross-connections between the additional series arrangement(s) and the first and second series arrangements of AND-gates.

5. A parity checker circuit as claimed in any preceding Claim, implemented as an integrated circuit in which the lattice gate structure is formed as an array logic structure comprising a plurality of controllable insulated gate field effect transistors which are formed at selected intersections of an array consisting of a plurality of rows of series-connected gate regions and a plurality of columns of surface regions which at each selected intersection define source and drain regions for the transistor which is formed there, an electrical path being formed at each other (non-selected) intersection, at least in use of the structure, to effectively short circuit the intersection in respect of the relevant surface region column.

6. A parity checker circuit, substantially as hereinbefore described with reference to Figs. 2 to 6 of the accompanying drawings.