DE2162806C2 - Speichersteuereinheit zur vereinfachter Pufferung von Anforderungen der Ein- Ausgabekanäle - Google Patents

Speichersteuereinheit zur vereinfachter Pufferung von Anforderungen der Ein- Ausgabekanäle

Info

Publication number
DE2162806C2
DE2162806C2 DE2162806A DE2162806A DE2162806C2 DE 2162806 C2 DE2162806 C2 DE 2162806C2 DE 2162806 A DE2162806 A DE 2162806A DE 2162806 A DE2162806 A DE 2162806A DE 2162806 C2 DE2162806 C2 DE 2162806C2
Authority
DE
Germany
Prior art keywords
channel
output
data
input
buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE2162806A
Other languages
German (de)
English (en)
Other versions
DE2162806A1 (de
Inventor
Robert Stanley Wappingers Falls N.Y. Capowski
Larry Ray Lousville Col. Horsman
Robert Mark Poughkeepsie N.Y. Unterberger
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE2162806A1 publication Critical patent/DE2162806A1/de
Application granted granted Critical
Publication of DE2162806C2 publication Critical patent/DE2162806C2/de
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Memory System (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)
  • Computer And Data Communications (AREA)
DE2162806A 1970-12-30 1971-12-17 Speichersteuereinheit zur vereinfachter Pufferung von Anforderungen der Ein- Ausgabekanäle Expired DE2162806C2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10257770A 1970-12-30 1970-12-30

Publications (2)

Publication Number Publication Date
DE2162806A1 DE2162806A1 (de) 1972-07-20
DE2162806C2 true DE2162806C2 (de) 1982-06-24

Family

ID=22290557

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2162806A Expired DE2162806C2 (de) 1970-12-30 1971-12-17 Speichersteuereinheit zur vereinfachter Pufferung von Anforderungen der Ein- Ausgabekanäle

Country Status (5)

Country Link
US (1) US3699530A (Direct)
JP (1) JPS5118297B1 (Direct)
DE (1) DE2162806C2 (Direct)
FR (1) FR2120738A5 (Direct)
GB (1) GB1312410A (Direct)

Families Citing this family (46)

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US3924241A (en) * 1971-03-15 1975-12-02 Burroughs Corp Memory cycle initiation in response to the presence of the memory address
US3858183A (en) * 1972-10-30 1974-12-31 Amdahl Corp Data processing system and method therefor
US3828325A (en) * 1973-02-05 1974-08-06 Honeywell Inf Systems Universal interface system using a controller to adapt to any connecting peripheral device
US3831151A (en) * 1973-04-04 1974-08-20 Gte Automatic Electric Lab Inc Sense line processor with priority interrupt arrangement for data processing systems
US3936803A (en) * 1973-11-19 1976-02-03 Amdahl Corporation Data processing system having a common channel unit with circulating fields
FR2253428A5 (Direct) * 1973-11-30 1975-06-27 Honeywell Bull Soc Ind
US3919483A (en) * 1973-12-26 1975-11-11 Ibm Parallel multiplexed loop interface for data transfer and control between data processing systems and subsystems
IT1002275B (it) * 1973-12-27 1976-05-20 Honeywell Inf Systems Sistema di elaborazione dati a piu canali di ingresso uscita a risorse orientate per livelli di servizio distinti e interrompi bili
US4040026A (en) * 1974-05-08 1977-08-02 Francois Gernelle Channel for exchanging information between a computer and rapid peripheral units
US4028663A (en) * 1974-06-05 1977-06-07 Bell Telephone Laboratories, Incorporated Digital computer arrangement for high speed memory access
US4056845A (en) * 1975-04-25 1977-11-01 Data General Corporation Memory access technique
US4070706A (en) * 1976-09-20 1978-01-24 Sperry Rand Corporation Parallel requestor priority determination and requestor address matching in a cache memory system
US4126893A (en) * 1977-02-17 1978-11-21 Xerox Corporation Interrupt request controller for data processing system
SE414087B (sv) * 1977-02-28 1980-07-07 Ellemtel Utvecklings Ab Anordning i ett datorsystem vid utsendning av signaler fran en processor till en eller flera andra processorer varvid prioriterade signaler sends direkt utan tidsfordrojning och oprioriterade signalers ordningsfoljd ...
US4115854A (en) * 1977-03-28 1978-09-19 International Business Machines Corporation Channel bus controller
US4110830A (en) * 1977-07-05 1978-08-29 International Business Machines Corporation Channel storage adapter
US4177513A (en) * 1977-07-08 1979-12-04 International Business Machines Corporation Task handling apparatus for a computer system
US4131940A (en) * 1977-07-25 1978-12-26 International Business Machines Corporation Channel data buffer apparatus for a digital data processing system
US4354232A (en) * 1977-12-16 1982-10-12 Honeywell Information Systems Inc. Cache memory command buffer circuit
FR2470412B1 (fr) * 1979-11-19 1986-10-03 Bull Sa Procede et dispositif de comptabilisation et de gestion des evenements asynchrones emis par des appareils peripheriques dans un systeme de traitement de donnees
US4425615A (en) 1980-11-14 1984-01-10 Sperry Corporation Hierarchical memory system having cache/disk subsystem with command queues for plural disks
JPS6037938B2 (ja) * 1980-12-29 1985-08-29 富士通株式会社 情報処理装置
US4410942A (en) * 1981-03-06 1983-10-18 International Business Machines Corporation Synchronizing buffered peripheral subsystems to host operations
US4410943A (en) * 1981-03-23 1983-10-18 Honeywell Information Systems Inc. Memory delay start apparatus for a queued memory controller
US4541045A (en) * 1981-09-21 1985-09-10 Racal-Milgo, Inc. Microprocessor architecture employing efficient operand and instruction addressing
DE3140310C1 (de) * 1981-10-10 1983-04-07 Telefonbau Und Normalzeit Gmbh, 6000 Frankfurt Schaltungsanordnung zur Speicherung von eine Datenverarbeitungseinrichtung weiterzugebenden Daten
US4672543A (en) * 1982-08-31 1987-06-09 Sharp Kabushiki Kaisha Data transmission control apparatus in local network systems
US4571674A (en) * 1982-09-27 1986-02-18 International Business Machines Corporation Peripheral storage system having multiple data transfer rates
JPS59148952A (ja) * 1983-02-14 1984-08-25 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション 優先順位回路
US4682304A (en) * 1983-08-04 1987-07-21 Tektronix, Inc. Asynchronous multiple buffered communications interface having an independent microprocessor for controlling host/peripheral exchanges
US5038277A (en) * 1983-11-07 1991-08-06 Digital Equipment Corporation Adjustable buffer for data communications in a data processing system
US4652993A (en) * 1984-04-02 1987-03-24 Sperry Corporation Multiple output port memory storage module
JPH0628051B2 (ja) * 1986-04-25 1994-04-13 株式会社日立製作所 記憶制御方式
US4803622A (en) * 1987-05-07 1989-02-07 Intel Corporation Programmable I/O sequencer for use in an I/O processor
US5111530A (en) * 1988-11-04 1992-05-05 Sony Corporation Digital audio signal generating apparatus
KR940002905B1 (en) * 1989-12-15 1994-04-07 Ibm Apparatus for conditioning priority arbitration in buffered direct memory addressing
EP0453863A2 (en) * 1990-04-27 1991-10-30 National Semiconductor Corporation Methods and apparatus for implementing a media access control/host system interface
US5584028A (en) * 1990-05-14 1996-12-10 At&T Global Information Solutions Company Method and device for processing multiple, asynchronous interrupt signals
US5465355A (en) * 1991-09-04 1995-11-07 International Business Machines Corporation Establishing and restoring paths in a data processing I/O system
US5544318A (en) * 1993-04-16 1996-08-06 Accom, Inc., Asynchronous media server request processing system for servicing reprioritizing request from a client determines whether or not to delay executing said reprioritizing request
JP3305042B2 (ja) * 1993-04-23 2002-07-22 キヤノン株式会社 印刷制御装置
GB2277816B (en) * 1993-05-04 1997-09-03 Motorola Inc Data communication system
DE19503022A1 (de) * 1994-04-08 1995-10-12 Hewlett Packard Co Master/Slave-Buskonfiguration für schnelle erweiterbare Speichersysteme
US5701434A (en) * 1995-03-16 1997-12-23 Hitachi, Ltd. Interleave memory controller with a common access queue
US6141707A (en) * 1998-05-28 2000-10-31 Emc Corporation Input/output request allocation by establishing master command queue among plurality of command queues to receive and store commands, determine logical volume, and forwarding command to determined logical volume
JP5225054B2 (ja) * 2008-12-19 2013-07-03 株式会社東芝 Ｉｃカード

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3210733A (en) * 1958-08-18 1965-10-05 Sylvania Electric Prod Data processing system
US3274554A (en) * 1961-02-15 1966-09-20 Burroughs Corp Computer system
US3200380A (en) * 1961-02-16 1965-08-10 Burroughs Corp Data processing system
US3274561A (en) * 1962-11-30 1966-09-20 Burroughs Corp Data processor input/output control system
US3530438A (en) * 1965-12-13 1970-09-22 Sperry Rand Corp Task control
US3396372A (en) * 1965-12-29 1968-08-06 Ibm Polling system
US3483522A (en) * 1966-05-26 1969-12-09 Gen Electric Priority apparatus in a computer system
US3482265A (en) * 1966-07-22 1969-12-02 Gen Electric Data processing system including means for awarding priority to requests for communication
US3449724A (en) * 1966-09-12 1969-06-10 Ibm Control system for interleave memory

Also Published As

Publication number Publication date
FR2120738A5 (Direct) 1972-08-18
US3699530A (en) 1972-10-17
DE2162806A1 (de) 1972-07-20
GB1312410A (en) 1973-04-04
JPS5118297B1 (Direct) 1976-06-09

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Legal Events

Date Code Title Description
OD Request for examination
D2 Grant after examination
8339 Ceased/non-payment of the annual fee