DE2031255C3 - Method and circuit arrangement for remote control of the serial-parallel conversion in a receiver of a telecommunications system, in particular a telephone exchange - Google Patents

Description

The invention relates to a method and a circuit arrangement for remote control and monitoring of the serial-parallel conversion in an information receiver in a central controller Telecommunication, in particular telephone exchange.

A serial transmission is often chosen for the transmission of multi-digit, binary information,

provided there is no transmission speed

Requirements close to the feasibility limit

be asked. The serial transmission method offers the advantage that the line expenditure is reduced will. However, most of the information is in the recipient needed to decode them and in parallel form to be able to evaluate. For this it is necessary in the

To arrange a series-parallel converter for the receiver. Such series-parallel converters can be used e.g.

ίο realize with known shift registers. The shift registers require one for the writing process well synchronized shift clock out of phase with the information. From the German Auslegeschrift 12 30 851 and the

is U.S. patent 27 19 959 cited therein known, the check for even numbers or odd numbers (checksum check, in English: parity check) used to secure the code in the case of serial transmission of the bits with a bistable multivibrator to execute. In this test circuit, the toggle circuit is switched to and fro depending on the incoming character elements Completion of the switching back and forth the bistable flip-flop has the original operating position or not, is the number of drawing elements to which has been checked (e.g. L elements), even or odd.

The structure and function of such a

bistable trigger circuit as modulo-2 series adder are so well known that a description can be found the details are superfluous. It is only mentioned that two modes of operation are possible, namely either the to give summed drawing elements to the clock input and the actual signal inputs free to leave, or a corresponding control clock on the To give clock input and the to be summed To give drawing elements to the signal inputs.

The task of the control method according to the invention is now the writing process in the Series-to-parallel converter to control and correct Control conversion at the output of the converter.

The method according to the invention is characterized in that in addition to the information a Control cycle twice the base frequency compared to the Information clock is transmitted to the receiver that in the receiver by frequency division from the control clock two auxiliary clocks which are phase-shifted from one another by about half the period, but are rigidly synchronized with the information clock and with one another are obtained that the one auxiliary clock for controlling the writing process in the series-parallel converter is used, and that the other auxiliary clock character-element-wise through the one Auxiliary clock serially generated output signals of the Series-parallel converter nested and so for serial checking of the output information that is ultimately pending in parallel is used.

A circuit arrangement according to the invention for carrying out the specified method is thereby characterized in that as a basic module for testing the serial input information, for the frequency division of the control clock and for testing the Output information from the series-parallel converter, uniform, known modulo-2 series adder are arranged that one output of the modulo-2 series adder used as a frequency divider is connected to a control meter, the outputs of which are each connected to a different stage of the series-parallel converter

are connected that a common serial interrogation output of the series-parallel converter with the signal inputs of the for checking the output information arranged modulo-2 series adder is connected, and that the other output of the modulo-2 series adder used as a frequency divider with the clock input of the modulo-2 series adder arranged for checking the output information is connected

A further development of the circuit arrangement according to the invention is characterized in that the ro Transmission path for the control clock and / or for the information is duplicated in each case that the two Transmission lines for the information each with their own testing modulo-2 series adder are connected and that the two transmission lines for the control clock with a common, frequency-dividing modulo-2 series adders are connected.

The invention is described below in context explained with the embodiment shown in the drawing

The drawing shows, with known logical symbols, a block diagram of a receiver for serially transmitted information.

The serial transmission of the information takes place via an information line IL, which in the example consists of two lines Li L2 to increase security, on which the same information is transmitted in parallel. The information on line L 2 is fed to the clock input of a first modulo-2 series adder 51, the actual signal inputs of which are not connected. This modulo-2 series adder supplies the result of the checksum check at its output 5 M in a known manner.

The information on the lines L 1 and L 2 are combined via technology-related inverters and an OR circuit 01. A character L therefore always arrives at the series-parallel converter SPW when a character L is received on both lines Li, L2.

On a control line StL, which is also duplicated in the example for reasons of security, the transmitting device delivers a control clock which has twice the frequency as the clock frequency of the information received. The control clock is fed from lines L 3 and L 4 via an OR circuit 02 and an inverter / to the clock input of a second modulo-2 series adder 52. This modulo-2 series adder 52 operates as a frequency divider. At its outputs S2Ai, S2A2 there appears a control clock (auxiliary clock) half the frequency compared to the received control clock, whereby the control clock at output S 2Ai is phase shifted by about half the period compared to the control clock at output S2A 2. The control clock from output 52Al is serialized. Parallel converter SPW is fed to a counter Z , which is reset before the start of an information transmission and then successively marks its outputs 1 to π with the aid of the control clock, where π is equal to the number of character elements of an information word

In addition to the counter Z, the series-parallel converter SPW includes a number of mutually identical storage flip-flops FFl to FFn, the structure and mode of operation of which are generally known. In principle, as with the modulo 2 series adder, there are two mutually fed back NAN D circuits Ni, N 2, one Ni being additionally connected to the information line and to an output of the counter via a further NAND circuit N3 , while the second NAND circuit N2 is additionally connected to a reset input, not shown

A character L appearing on the information line causes the memory flip-flop that is marked by the counter Z to flip over, e.g. B. the storage flip-flop FFl. As a result, a pulse appears at their output FF XA. Al! E corresponding outputs of the memory flip-flops FFl to FFn are connected together with the signal inputs of a third modulo-2 series adder 53, whose clock input is supplied with the control clock from output S2A2 of the second modulo-2 series adder 5 2.

Since the pulses at the outputs of the memory flip-flops occur immediately during the writing process, but on the other hand they reflect the actually stored state of each stage, the result of the checksum check of the pending can be obtained with certainty at output S3A of the modulo-2 series adder 53 immediately after the writing process has been completed Read output signals of the series-parallel converter 5PW.

Since the control clock for the write-in process and the modulo-2 series adder 53 come from the same control clock of the sending device is obtained, there are no synchronization problems that occur with multi-digit Information would place tight limits on the transmission speed.

1 sheet of drawings

Claims (3)

Patent claims: 1. A method for remote control and monitoring of the serial-parallel conversion in an information receiver in the central control of a remote control, in particular telephone switching system, characterized in that in addition to the information, a control clock twice the basic frequency compared to the information clock is transmitted to the receiver that in the receiver by Frequency division from the control clock two auxiliary clocks, phase-shifted by about half the period, but rigidly synchronized with the information clock and with each other, that one auxiliary clock is used to control the writing process in the serial / allele converter (SPW) , and that the other auxiliary clock is again interleaved character-by-character with the output signals of the serial-to-parallel converter produced in series by the one auxiliary clock and is thus used for the serial checking of the output information that is ultimately pending in parallel. 2. Circuit arrangement for carrying out the method according to claim 1, characterized in that the basic module for checking the serial input information, for the frequency division of the control clock and for checking the output information of the series-parallel converter (SPW) is uniform, known modulo -2 series adders (SX, S2, S3) are arranged that one output (S2A X) of the modulator 2 series adder (S 2) used as a frequency divider is connected to a control counter (Z) whose outputs (1 .. . n) are each connected to a different stage (FFX ... FFn) of the series-parallel converter (SPW) that a common series query output of the series-parallel converter with the signal inputs of the modulo arranged for checking the output information -2 series adder (S3) is connected, and that the other output (S 2A 2) of the modulo-2 series adder (S 2) used as a frequency divider with the clock input of the arranged for checking the output information Modulo 2 series adder (S3) is connected. 3. Circuit arrangement according to claim 2, characterized in that the transmission path for the control clock and / or for the information is duplicated in each case that the two transmission lines (L 1, L 2) for the information each have their own testing modulo-2 series adder (SX, SX ') are connected and that the two transmission lines (L 3, L 4) for the control clock are connected to a common, frequency-dividing modulo-2 series adder (S 2).