GB1348530A - Serial parallel conversion - Google Patents

Abstract

1348530 Automatic exchange systems; digital transmission systems INTERNATIONAL STANDARD ELECTRIC CORP 27 May 1971 [24 June 1970] 17519/71 Headings H4K and H4P In the central control equipment of a telecommunication exchange a clock pulse train and a signal pulse train of half the clock pulse train frequency are transmitted to a receiver which divides the clock pulse train into first and second pulse trains each of the signal pulse frequency, the first of which is used to control writing of the signal pulse train in a serial to parallel converter and fed together with the second train to a circuit which checks the written information. In the receiver shown information signals incoming on lines L1 and L2, in duplicate for security, are checked for parity (odd or even) by trigger circuits S1, S1, and applied to each of a set of gates such as N3 leading to bi-stables FF1 to FFn. Clock pulse trains arriving over lines L3 and L4, in duplicate for security, are applied to a trigger circuit S2 which passes them alternately to lines S2A1 and S2A2 to provide two clock pulse trains of the same frequency as the incoming signals and 180 degrees out of phase with each other. The pulses of the train at S2A1 step a counter Z successively enabling its outputs 1 to n, causing for each step a bi-stable such as FF1 to be set in accordance with the information signal bit received at that time and causing the set state to be applied via a gate such as FF1A to trigger circuit S3 enabled by the next pulse of the other clock pulse train at S2A2. The trigger circuit S3 performs a parity check of the information stored in the bi-stables FF1 to FFn prior to their gating out in parallel at A1 to An.