DE2015643A1 - Verfahren zur Herstellung von Mehrschi cht-Stromkreispaneelen - Google Patents

Verfahren zur Herstellung von Mehrschi cht-Stromkreispaneelen

Info

Publication number
DE2015643A1
DE2015643A1 DE19702015643 DE2015643A DE2015643A1 DE 2015643 A1 DE2015643 A1 DE 2015643A1 DE 19702015643 DE19702015643 DE 19702015643 DE 2015643 A DE2015643 A DE 2015643A DE 2015643 A1 DE2015643 A1 DE 2015643A1
Authority
DE
Germany
Prior art keywords
process according
insulating material
conductive material
layer
electrically conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE19702015643
Other languages
German (de)
English (en)
Inventor
Alexander Joseph Binhamton; Scheer Herman Carl Endicott; N.Y. Mc Pherson (V.St.A.)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE2015643A1 publication Critical patent/DE2015643A1/de
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4647—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09881—Coating only between conductors, i.e. flush with the conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/0733—Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
    • H05K3/181—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing of the conductive pattern
    • H05K3/243—Reinforcing of the conductive pattern characterised by selective plating, e.g. for finish plating of pads

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE19702015643 1969-04-02 1970-04-02 Verfahren zur Herstellung von Mehrschi cht-Stromkreispaneelen Pending DE2015643A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US81270069A 1969-04-02 1969-04-02

Publications (1)

Publication Number Publication Date
DE2015643A1 true DE2015643A1 (de) 1970-11-05

Family

ID=25210373

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19702015643 Pending DE2015643A1 (de) 1969-04-02 1970-04-02 Verfahren zur Herstellung von Mehrschi cht-Stromkreispaneelen

Country Status (4)

Country Link
JP (1) JPS502059B1 (https=)
DE (1) DE2015643A1 (https=)
FR (1) FR2042059A5 (https=)
GB (1) GB1262245A (https=)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3315615A1 (de) * 1983-04-29 1984-10-31 Brown, Boveri & Cie Ag, 6800 Mannheim Verfahren zur herstellung einer multilayer-schaltung
EP0190490A3 (en) * 1985-01-31 1987-01-28 Gould Inc. Thin-film electrical connections for integrated circuits
DE3735959A1 (de) * 1987-10-23 1989-05-03 Bbc Brown Boveri & Cie Mehrlagige duennschichtschaltung sowie verfahren zu deren herstellung
US4996584A (en) * 1985-01-31 1991-02-26 Gould, Inc. Thin-film electrical connections for integrated circuits

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5398650U (https=) * 1977-01-14 1978-08-10
JPS543202U (https=) * 1977-06-08 1979-01-10
JPS6224739U (https=) * 1985-07-30 1987-02-14
JPH01268504A (ja) * 1988-04-21 1989-10-26 Cleanup Corp 多用途家具
DE69633690T2 (de) * 1995-10-23 2005-03-10 Ibiden Co., Ltd., Ogaki Harzfüllstoff und mehrschichtige Leiterplatte
WO2000025355A1 (fr) * 1998-10-26 2000-05-04 Hitachi, Ltd. Procede de fabrication de dispositifs a semi-conducteurs
JP6447075B2 (ja) * 2014-12-10 2019-01-09 凸版印刷株式会社 配線基板、半導体装置及び半導体装置の製造方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3315615A1 (de) * 1983-04-29 1984-10-31 Brown, Boveri & Cie Ag, 6800 Mannheim Verfahren zur herstellung einer multilayer-schaltung
EP0190490A3 (en) * 1985-01-31 1987-01-28 Gould Inc. Thin-film electrical connections for integrated circuits
US4996584A (en) * 1985-01-31 1991-02-26 Gould, Inc. Thin-film electrical connections for integrated circuits
DE3735959A1 (de) * 1987-10-23 1989-05-03 Bbc Brown Boveri & Cie Mehrlagige duennschichtschaltung sowie verfahren zu deren herstellung

Also Published As

Publication number Publication date
GB1262245A (en) 1972-02-02
JPS502059B1 (https=) 1975-01-23
FR2042059A5 (https=) 1971-02-05

Similar Documents

Publication Publication Date Title
DE69529632T2 (de) Induktivität und zugehöriges Herstellungsverfahren
DE4447897B4 (de) Verfahren zur Herstellung von Leiterplatten
DE2847356C2 (de) Verfahren zur Herstellung einer gedruckten Schaltung mit Widerstandselementen
DE1271235B (de) Verfahren zur Herstellung von leitenden Verbindungen zwischen den leitenden Schichten einer elektrischen Schaltungsplatte
DE19636735B4 (de) Mehrschichtiges Schaltungssubstrat und Verfahren zu seiner Herstellung
DE4417245A1 (de) Verfahren zur strukturierten Metallisierung der Oberfläche von Substraten
DE2650761A1 (de) Metallmaske zur verwendung beim siebdruck
DE68918210T2 (de) Selektive Lötmetallbildung auf Leiterplatten.
DE2144137A1 (de) Verfahren zum Herstellen der Löcher für die Verbindungen zwischen elektrischen, parallel übereinander liegenden Schaltungslagen einer Mehrlagen-Schaltungspackung
EP0508946A1 (de) Metallfolie mit einer strukturierten Oberfläche
DE3700910A1 (de) Verfahren zum aufbau elektrischer schaltungen auf einer grundplatte
DE1817434B2 (de) Verfahren zur Herstellung einer elektrischen Leitungsanordnung
EP0016925A1 (de) Verfahren zum Aufbringen von Metall auf Metallmuster auf dielektrischen Substraten
DE2015643A1 (de) Verfahren zur Herstellung von Mehrschi cht-Stromkreispaneelen
DE2045830A1 (de) Koaxiale Schaltungsanordnung und Verfahren zu ihrer Herstellung
DE4203114A1 (de) Bandtraeger fuer halbleitergeraete und verfahren zur herstellung desselben
DE60130412T2 (de) System und Verfahren zur Erzeugung von Hochspannungswiderstandsfähigkeit zwischen den nachgiebigen Stiften eines Steckverbinders mit hoher Kontaktdichte
CH654161A5 (de) Verfahren zum herstellen von gedruckten leiterplatten mit lochungen, deren wandungen metallisiert sind.
DE69530698T2 (de) Verfahren zur herstellung einer leiterplatte
DE1446214A1 (de) Verfahren zum Aufbringen von metallischen UEberzuegen auf Dielektrika
DE4406397A1 (de) Substrat für elektrische Schaltkreise sowie Verfahren zum Herstellen des Substrates
DE2838982B2 (de) Verfahren zum Herstellen von Mehrebenen-Leiterplatten
DE2014138C3 (de) Verfahren zur Herstellung von gedruckten Leiterplatten
DE1665248C3 (de) Verfahren zur Herstellung eines Trägers für eine miniaturisierte Schaltung
DE3522852C2 (de) Verfahren zur Herstellung eines Zwischenträgers für Halbleiterkörper

Legal Events

Date Code Title Description
E77 Valid patent as to the heymanns-index 1977