DE19982913T1 - System und Verfahren zum Multiplexen von seriellen Linkleitungen - Google Patents

System und Verfahren zum Multiplexen von seriellen Linkleitungen

Info

Publication number
DE19982913T1
DE19982913T1 DE19982913T DE19982913T DE19982913T1 DE 19982913 T1 DE19982913 T1 DE 19982913T1 DE 19982913 T DE19982913 T DE 19982913T DE 19982913 T DE19982913 T DE 19982913T DE 19982913 T1 DE19982913 T1 DE 19982913T1
Authority
DE
Germany
Prior art keywords
serial link
link lines
multiplexing serial
multiplexing
lines
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE19982913T
Other languages
English (en)
Inventor
William Burns
Michael Lucas
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Storage Technology Corp
Original Assignee
Storage Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Storage Technology Corp filed Critical Storage Technology Corp
Publication of DE19982913T1 publication Critical patent/DE19982913T1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0656—Data buffering arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G06F3/0689—Disk arrays, e.g. RAID, JBOD
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/04—Distributors combined with modulators or demodulators
    • H04J3/047—Distributors with transistors or integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Mathematical Physics (AREA)
  • Information Transfer Systems (AREA)
  • Time-Division Multiplex Systems (AREA)
DE19982913T 1998-03-16 1999-03-15 System und Verfahren zum Multiplexen von seriellen Linkleitungen Withdrawn DE19982913T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/039,890 US5974058A (en) 1998-03-16 1998-03-16 System and method for multiplexing serial links
PCT/US1999/005658 WO1999048235A1 (en) 1998-03-16 1999-03-15 System and method for multiplexing serial links

Publications (1)

Publication Number Publication Date
DE19982913T1 true DE19982913T1 (de) 2001-02-22

Family

ID=21907893

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19982913T Withdrawn DE19982913T1 (de) 1998-03-16 1999-03-15 System und Verfahren zum Multiplexen von seriellen Linkleitungen

Country Status (4)

Country Link
US (2) US5974058A (de)
JP (1) JP2002507856A (de)
DE (1) DE19982913T1 (de)
WO (1) WO1999048235A1 (de)

Cited By (1)

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Publication number Priority date Publication date Assignee Title
DE102004023810B3 (de) * 2004-02-16 2005-08-25 Hitachi, Ltd. Speicherplattensteuerung

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US6265951B1 (en) 1997-11-15 2001-07-24 Cybex Computer Products Corporation Method and apparatus for equalizing channel characteristics in a computer extension system
US6185643B1 (en) 1997-11-15 2001-02-06 Cybex Computer Products Corporation Method and apparatus for extending the range between a computer and computer peripherals
US6078974A (en) * 1998-04-08 2000-06-20 Cybex Computer Products Corporation Method and apparatus for extension of bi-directional open collector signals in a multiplexed data transmission system
JP3657428B2 (ja) * 1998-04-27 2005-06-08 株式会社日立製作所 記憶制御装置
US6301637B1 (en) * 1998-06-08 2001-10-09 Storage Technology Corporation High performance data paths
US6611895B1 (en) * 1998-06-08 2003-08-26 Nicholas J. Krull High bandwidth cache system
EP1093046A1 (de) * 1999-10-15 2001-04-18 Koninklijke Philips Electronics N.V. Verfahren zur Auswahl eines Signals aus N Signalen
US6738935B1 (en) * 2000-02-07 2004-05-18 3Com Corporation Coding sublayer for multi-channel media with error correction
US6662253B1 (en) * 2000-09-13 2003-12-09 Stmicroelectronics, Inc. Shared peripheral architecture
US7254647B2 (en) * 2001-03-23 2007-08-07 International Business Machines Corporation Network for decreasing transmit link layer core speed
US6625675B2 (en) 2001-03-23 2003-09-23 International Business Machines Corporation Processor for determining physical lane skew order
US6665754B2 (en) 2001-03-23 2003-12-16 International Business Machines Corporation Network for increasing transmit link layer core speed
US7639655B2 (en) * 2001-12-22 2009-12-29 Scientific-Atlanta, Inc. Ethernet switch interface for use in optical nodes
US6981190B2 (en) * 2002-09-30 2005-12-27 Texas Instruments Incorporated Controlling the content of specific desired memory elements when testing integrated circuits using sequential scanning techniques
US6996645B1 (en) * 2002-12-27 2006-02-07 Unisys Corporation Method and apparatus for spawning multiple requests from a single entry of a queue
JP2004348464A (ja) * 2003-05-22 2004-12-09 Hitachi Ltd ストレージ装置、及び通信信号の整形回路
DE10335978B4 (de) * 2003-08-06 2006-02-16 Infineon Technologies Ag Hub-Baustein zum Anschließen von einem oder mehreren Speicherbausteinen
US7342520B1 (en) * 2004-01-08 2008-03-11 Vladimir Katzman Method and system for multilevel serializer/deserializer
US7467238B2 (en) * 2004-02-10 2008-12-16 Hitachi, Ltd. Disk controller and storage system
JP4441286B2 (ja) * 2004-02-10 2010-03-31 株式会社日立製作所 ストレージシステム
US7174411B1 (en) 2004-12-02 2007-02-06 Pericom Semiconductor Corp. Dynamic allocation of PCI express lanes using a differential mux to an additional lane to a host
JP5381305B2 (ja) * 2009-05-08 2014-01-08 富士通株式会社 受信装置、送受信装置、及び伝送システム
US8254378B2 (en) * 2009-07-23 2012-08-28 Altera Canada Co. Strict-sense minimal spanning switch non-blocking architecture

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US4759014A (en) * 1987-05-28 1988-07-19 Ampex Corporation Asynchronous-to-synchronous digital data multiplexer/demultiplexer with asynchronous clock regeneration
JPH07114348B2 (ja) * 1987-12-11 1995-12-06 日本電気株式会社 論理回路
US4855616A (en) * 1987-12-22 1989-08-08 Amdahl Corporation Apparatus for synchronously switching frequency source
US4853653A (en) * 1988-04-25 1989-08-01 Rockwell International Corporation Multiple input clock selector
KR910006355B1 (ko) * 1988-08-18 1991-08-21 한국 전기 통신공사 채널 선택 제어신호를 이용한 멀티플렉서 출력의 인에이블/디스에이블 제어장치
WO1992006436A2 (en) * 1990-10-03 1992-04-16 Thinking Machines Corporation Parallel computer system
JP2715671B2 (ja) * 1991-01-30 1998-02-18 三菱電機株式会社 表示制御装置
WO1993019529A1 (en) * 1992-03-19 1993-09-30 Vlsi Technology Inc. Asynchronous-to-synchronous synchronizers, particularly cmos synchronizers
US5237573A (en) * 1992-03-31 1993-08-17 Apple Computer, Inc. Method and apparatus for selectively switching between input signals
GB2293062B (en) * 1994-09-09 1996-12-04 Toshiba Kk Master-slave multiplex communication system and PLL circuit applied to the system
US5680564A (en) * 1995-05-26 1997-10-21 National Semiconductor Corporation Pipelined processor with two tier prefetch buffer structure and method with bypass
US5734685A (en) * 1996-01-03 1998-03-31 Credence Systems Corporation Clock signal deskewing system
US5751724A (en) * 1996-02-23 1998-05-12 Dsc Communications Corporation Demultiplexer for a multi-bitline bus
US5867543A (en) * 1996-03-29 1999-02-02 Dsc Communications Corporation Multi-rate transmission system
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JP3883687B2 (ja) * 1998-02-16 2007-02-21 株式会社ルネサステクノロジ 半導体装置、メモリカード及びデータ処理システム

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004023810B3 (de) * 2004-02-16 2005-08-25 Hitachi, Ltd. Speicherplattensteuerung

Also Published As

Publication number Publication date
WO1999048235A1 (en) 1999-09-23
JP2002507856A (ja) 2002-03-12
US6154797A (en) 2000-11-28
US5974058A (en) 1999-10-26

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Legal Events

Date Code Title Description
8139 Disposal/non-payment of the annual fee