DE19511594A1 - Analogue input magnitude to digital output value conversion method - Google Patents

Abstract

A method of converting an analog input magnitude (Vin) into a digital output value having n bit places of value 2 power 0 up to 2 power n-1, and in which for each bit place a reference value is formed whose weighting or value is at least as great as a minimum value, of this reference (V Ref1-----V Ref n), proportional to the weighting or value (2 power 0----2 power n-1) of the bit place (Bit 1----Bit n). The input magnitude (Vin) is then compared with the reference values assigned to the bit places (Bit 1---Bit n) to form a comparison value V (V 01 -----V vn), to which is allocated a bit place (Bit 1---Bit n-1) of lower weighting (value) than the highest value assigned reference value (V ref 1----V ref n-1). The input value (Vin) is compared with the reference values assigned to the bit places until none of the comparison values cause a change of value of the reference values (V Ref 1---- V Ref n). The digital output value of a bit place (Bit 1----Bit n) is then fixed by the sign of the difference resulting from the value (Vin) and the reference value (V ref 1---V ref n) assigned to this bit position (Bit 1-----Bit n).

Description

The invention relates to a method according to the Oberbe handle of claim 1 and an analog / digital Converter for performing the method.

From U. Tietze, Ch. Schenk: Semiconductor circuit technology, 1978, pages 631-646, several methods for analog / digital conversion are known. In the process referred to there as the parallel method, the input variable is simultaneously compared with 2 ⁿ -1 reference variables. In this way it is determined between which two reference variables the input variable lies. The parallel procedure is a fast procedure, since the input variable is compared with all reference variables at the same time and consequently only one comparison step is required to determine the digital output value. However, the circuit complexity for an analog / digital converter for carrying out this method is very high, since for a digital output value with n bit positions 2 ⁿ -1 comparison stages and additionally a priority encoder for evaluating 2 ⁿ -1 ver supplied by the comparison stages results are needed.

In the case of the weighing reference in the cited reference The designated procedures are the digital off determined values of the individual bit positions one after the other  telt. To do this, a logic circuit is used current digital test value generated, this test value through a digital / analog converter into an analog re converted reference size and the reference size with the analog input variable compared. The result of this Comparison is used to create a new digital Test value evaluated by the logic circuit. To Bil a digital output value with n bit positions n comparison steps are required in this process does. The process is therefore slower than that Parallel method, however, the circuitry is for an analog / digital converter to perform this Process less than the circuitry for one analog / digital Converter, since all comparison steps with a ver be carried out at the same level.

It's a simple but slow process if described in the mentioned reference Counting method. The number of times a reef is counted limit size must be added to the input size receive. The number of addi specified as a dual number step is equal to the digital output value. Receives a digital output value with n bit positions therefore, after a maximum of n comparison steps.

The object of the invention is to provide a method rens for analog / digital conversion, which is fast and can be realized with just a few individual components. The The object is achieved by the characterizing Features of claim 1 solved. Beneficial Further developments and refinements result from the subclaims.

In the method according to the invention, n reference sizes ß formed, all compared with the input variable  will. Each of the reference quantities becomes a bit assigned to the digital output value; of the Is the value of the reference variable assigned to a bit position at least the same size as the value of the Bit position proportional minimum value of this reference size, whereby the value of the bit position with the highest Most valued assigned reference size is equal to The minimum value of this reference variable is. For every bit le becomes a comparison assigned to this bit position size formed by the sign of the difference Input variable and the Re assigned to this bit position reference size depends and the result of the comparison of the Input variable with the Re assigned to this bit position represents reference size. By the one bit position ordered comparison size are the values of the bit places with lower value assigned Refe limit sizes set. This is a bit position assigned reference size the sum of its minimum value and the minimum values of those reference values, the bit positions with higher significance, their assigned ordered comparison size larger than one of the respective Threshold size assigned to reference size are assigned sen. The value of the reference assigned to a bit position The limit size is therefore, if no bit position with a higher one Value exists or if the bit positions with comparison values assigned to higher values are smaller than the respective threshold values their minimum value. The input variable is with so long compared the reference sizes until the comparison sizes cause no change in the values of the reference values ken. The digital output value of a bit position is then by the sign of the difference from the one output size and the reference assigned to this bit position limit size set.  

The process is a continuous, lagging one Method; it's continuous because for the input size, as soon as it changes, one of the changed ones corresponding new digital output value is determined, it is a post process because the digital output values of those bits len, which are due to the change in the input variable not change, not redetermined.

The method can be excellently carried out using an Ana Carry out log / digital converter. This analog / digi tal converter has a converter input for the Input variable and n, each assigned to a bit position te, converter outputs for the n bit positions of the digital Output value. It also has n control units which each form one of the n reference values, so like n comparison levels, each one of the reference Compare sizes with the input size and each form one of the benchmarks. The reference sizes are all at the same time with the input variable compared. The control units and the comparator fen are each assigned to a bit position. Each of the Comparison stages has a comparison output as well a first comparison input and a second ver same input on. The converter entrance is with the he most comparison inputs of the comparison levels connected the. The converter output assigned to a bit position is with the comparison output assigned to this bit position neten comparison stage at which this bit position orderly comparison variable is pending, connected. The the control unit assigned to this bit position is with the second input of the Ver assigned to this bit position equal level connected; it assigns a tax to this output on which the bit it generated, this bit position assigned, reference quantity is pending; she points in addition, provided that the bit position to which it is assigned  is not the most significant bit position, one for each bit position with higher significance Tax assigned bit position with higher value input on that to the comparison output of this Bit position with higher significance assigned to ver equal stage is connected.

A control unit preferably assigns to each of them Control inputs one from the respective control input controllable threshold switching and an initialization tion circuit and a summing circuit; the Ini tialization circuit and the threshold circuits are in the summing circuit with the control gear of the control unit connected. Here serves the Initialization circuit for generating an initiali size, which is the minimum value of the tax specifies unit generated reference size; the swell value circuits are used to generate switchable Sizes that correspond to the minimum value of the reference size Specify the added value of the reference size.

The input variable and the reference variable are preferred wise tensions. The summation circuit of the control unit Unit is then advantageously as one with a Re Reference resistor connected and to the control output line node connected to the control unit leads into which a current is fed, the value the reference quantity generated by this control unit specifies. This current consists of an initiali sierungsstrom and possibly from one or more switchable other currents together. The initial tion current is preferably from the Initia initialization current source circuit supplied; the switchable other currents are preferably each switchable Current source executed threshold circuit gelie  finished. A switchable power source is used if the the control input via which it is controlled comparison size led a threshold size of this switchable power source, d. H. that of the reference size assigned threshold size, exceeds or below steps, switched on or switched off.

That assigned to a bit position, from the difference of Input variable and the Re assigned to this bit position Reference size dependent comparison value runs through if the sign of this difference changes, a ste value range. Because the threshold size is one Threshold switching within this value range is the switchable power source of this threshold value switching on or off at a time tet, to which this threshold value circuit supplied Comparative size not yet their digital off corresponding to the assigned bit position Has reached final value. Accordingly, a reference takes increase its final value before the digital output value the bit position with the next higher significance than that Significance of the bit position to which this reference variable is assigned, ready at the respective converter output is posed.

The reference resistors of the control units are in front preferably the same size; the initialization stream one The control unit is then proportional to the value the bit position to which the control unit is assigned is net, and the switchable other currents are each because proportional to the value of the higher Bit positions, with a switchable additional current per is proportional to the value of that bit position which is assigned the comparison variable that the switch baren power source, which this switchable further Electricity supplies, is supplied. The proportionality  factor is for the initialization streams and for the switchable other currents of all control units same size.

The comparison outputs of the comparison levels are direct or via a matching level with one each Converter output connected. With these adjustment levels you can the comparison quantities of signal levels supplied to them, which correspond to the digital output values of the bit positions speak, be adjusted. The adjustment circuits can also be designed as memory cells for Store the digital output value.

The advantages achieved with the invention are special in that the process is quick and self is controlling and that no clock signals are required. The process is faster than the weighing process because it is a post process and consequently especially with small changes in the input variable short conversion times result and since that of a bit le assigned reference size not only after loading Setting the digital output value of the bit position is generated with the next higher value. Of the Circuitry for the analog / digital converter is less than the circuitry for an analog / di gital converter to carry out the parallel process, there is only one control unit for each bit position and only a comparison level is required and there is no priority encoder is required.

The invention is based on the figures nä described here. Show it:

Fig. 1 is a schematic diagram of an analog / digital converter for implementing the method according to the invention,

Fig. 2 is a schematic diagram of a control unit of the analog / digital converter of Fig. 1,

Fig. 3 shows an embodiment of the analog / digital converter from Fig. 1 and

FIGS. 4a and 4b shows a typical waveform for a 3-bit analog / digital wall lung.

In the analog / digital converter shown in Fig. 1, an input voltage - the input variable V _IN - on the converter input IN the first comparison inputs (+) - the non-inverting comparison inputs - the n amplifier stages V₁. . . V _n supplied. The two th comparison input (-) - the inverting comparison input - the amplifier stage V₁ or. . . . or V _n is with the control unit S₁ or. . . . or S _n , which is a reference _voltage - the reference _variable V _Ref1 or. . . or V _Refn generated, connected. The comparison output VO₁ or. . . . or VO _{n of} the amplifier stage V₁ or. . . or V _n , on which the difference between the input variable V _IN and the reference _variable V _Ref1 or. . . . or V _Refn dependent comparison _variable V _VO1 or. . . . or V _VON is present, is with the converter output D₁ or. . . . or D _n connected. The converter outputs D₁. . . D _n , the comparison stages V₁. . . V _n and the control units S₁. . . S _n and their reference _variables V _Ref1 . . . V _Refn who with k = 1, 2 _,. . . , n consecutively numbered. The k-th converter output D _k , the k-th amplifier stage V _k , the k-th control unit S _k and the reference variable V _Refk generated _thereby are assigned to the k-th bit position bit _k with the valency 2 ^k-1 . In addition to the control output SO _k connected to the inverting comparison input of the k-th amplifier stage V _k , the k-th control unit S _k has bits _{k + 1} ,. For each higher-order bit position. . ., Bit _n a control input SI _{k, 1} . . . SI _{k, nk} on. The control input SI _{k, 1} resp. . . . or SI _{k, nk} is with the comparison output VO _{k + 1} or VO _{n of} the comparison stage V _{k + 1} or. . . . or V _n connected. The adaptation levels A₁. . . A _n , over which the comparison outputs VO₁ or. . . . or VO _n with the converter outputs D₁ or. . . . or D _n are used to adapt the comparison _variables V _VO1 or. . . . or V _VOn to the inputs of a circuit to which the digital output value is supplied.

Fig. 2 shows the principle circuit diagram of the k-th, bit of the bit location _k associated control unit S _k. The summing circuit Σ _k is formed as a reference resistor R _k , one terminal of which is connected to ground and the other terminal of which is connected to the control output SO _k . At the _k to the control output terminal SO connected to the reference resistance R _k are the nk as switchable current sources IQ _{k,. 1} . . IQ _{k, nk} threshold circuits SQ _{k, 1} . . . SQ _{k, nk} and the initialization circuit INI _k designed as initialization current source IQ _{k, 0} . The initialization circuit INI _k supplies a constant initialization current I _{k, 0} and the threshold circuits SQ _{k, 1} . . . SQ _{k, nk} each have a switchable additional current I _{k, 1} or. . . . or I _{k, nk} , which only flows when the respective switchable current source IQ _{k, 1} or. . . . or IQ _{k, nk is} switched on. With the switching device SW _{k, 1} or. . . . or SW _{k, nk} , the control input SI _{k, 1} or. . . . or SI _{k, nk is} connected, the switchable current source IQ _{k, 1} or. . . . or IQ _{k, nk} on or off. The switching device SW _{k, 1} or. . . . or SW _{k, nk} is switched on if the you via the respective control input SI _{k, 1} or. . . . or SI _{k, nk} supplied comparison _variable V _{VOk + 1} or. . . or V _from a switching threshold - the size of ence Refe V _REFk associated threshold amount V _Sch - ser the switching device SW _{k, 1} respectively. . . . or SW _{k, nk} exceeds. Since the switching process should be carried out as quickly as possible and current peaks caused by the switching process should be as small as possible, the switching devices SW _{k, 1} . . . SW _{k, nk} executed as a switch ter, the respective current I _{k, 1} . . . I _{k, nk} either to the summing circuit Σ _k or to a reference potential. The source of the initialization current IQ _{k, k 0} supplied initialization current _{I 0} is proportional to the value of the bit position of bit _k to the control unit S is assigned to _k, ie for the Ini tialisierungsstrom I _{k, 0} the following relationship applies I _{k, 0} = 2 ^k-1 · I₀, where 2 ^{k-1 represents} the value of the bit position bit _k and I₀ a proportionality factor, which for all control units S₁. . . S _{n is the} same size. The of the threshold circuit SQ _{k, 1} or. . . . or SQ _{k, nk} supplied switchable additional current I _{k, 1} or. . . . or I _{k, nk} is by a factor of 2¹ or. . . or 2 ^nk greater than the initialization current I _{k, 0} , ie it is proportional to the value of the bit position bit _{k + 1} or. . . or bit _n . The executed in the manner of the reference resistor R _k reference resistors of the control units S₁. . . S _n are all the same size. The relationship then applies to the reference _variable V _Refk , ie for the voltage present at the reference _resistor R _k

where 2 ^k-1 · I₀ · R _{k is} the minimum value of the reference _variable V _Refk and 2 ^j · I₀ · R _k with j = k _,. . ., n-1 represents the minimum value of the reference _variable V _{Refj + 1} . The product I₀ · R _k - the minimum value of the reference _variable V _Ref1 - determines the resolution of the analog / digital converter, ie the change in the input variable V _IN , which _{corresponds to} the change in the digital output value by 1 bit. The factors a _{k, j} for j = k,. . . n-1, which each take the value 1 or 0, represent the switching states of the threshold value circuits SQ _{k, 1} . . . SQ _{k, nk} . The factor a _{k, j} assumes the value 0 if no current flows from the threshold circuit SQ _{k, j} to the summing circuit Σ _k , ie if the comparison _variable V _{VOk + j is} smaller than the threshold _variable V _{Sch is} the threshold circuit SQ _{k, j} ; otherwise it takes the value 1. As a result, it represents the digital value that bit position bit _{j + 1} assumes after the end of the analog / digital conversion.

Fig. 3 shows the embodiment of FIG. 1 and FIG. 2 realized 3-bit analog / digital coupler wall. The reference resistors R₁, R₂, R₃, at which the reference _variables V _Ref1 or V _Ref2 or V _{Ref3 are} tapped, are all R₀ = 1 kΩ. The initialization power source IQ _1.0 supplies a current to the current 1 mA to _2.0 Initialisierungsstromquelle IQ and SQ threshold value _1.1 in the on state a current circuits each of the current 2 mA and the Ini tialisierungsstromquelle IQ _3.0 and the threshold value SQ _2.1 and SQ _1.2 each have a current of 4 mA when switched on.

The mode of operation of this 3-bit analog / digital converter is described in more detail with reference to a signal curve shown in FIGS. 4a and 4b. Fig. 4a shows the course of the input variable V _IN and the reference variables V _Ref1 , V _Ref2 and V _Ref3 and Fig. 4b shows the course of the comparison variable VO1 or VO2 or VO₃ applied comparison _variable V _VO1 or V _VO2 or V _VO3 and the course of the threshold _variable V _Sch . The threshold variable V _Sch is of the same size for all threshold circuits SQ _1.1 , SQ _1.2 , SQ _2.1 and lies within the range of values of the comparison _variables V _VO1 , which is limited by the lower limit value V _L and by the upper limit value V _H , V _VO2 , V _VO3 . The method also works if different threshold sizes are provided for the threshold value circuits SQ _1,1 , SQ _1,2 , SQ _2,1, provided that these threshold sizes lie within the value range limited by the limit values V _L and V _H. The reference _variables V _Ref1 or V _Ref2 or V _Ref3 are _initialized according to FIG. 4a with 1 V or 2 V or 4 V - their minimum values. At time t₀, input variable V _IN jumps from 0 V to, for example, 5.5 V. From this time t₀, input variable V _{IN is} greater than the values of reference _variables V _Ref1 , V _Ref2 and V _Ref3 . As a result, the comparison _variables V _VO1 , V _VO2 and V _{VO3 change} . Referring to FIG. 4b they pass through ei NEN length range from the lower limit value V _L - the di gitalen the output value 0 corresponding signal level - in the direction of the upper limit value V _H - the output value from the digital signal level 1 corresponding. As soon as the comparative variables V _VO3 and V _{VO2 exceed} the threshold _variable V _Sch of, for example, 0.7 V, a current of 2 mA flows from the threshold circuits SQ _1.1 , SQ _1.2 and from the threshold circuit and SQ _2.1 Current of 4 mA. These currents increase the value of the reference _variable V _Ref1 by 6 V and the value of the reference _variable V _Ref2 by 4 V; the value of the reference variable V _Ref3, since he sizes regardless of the comparison V _{VO1, VO2} V, V _VO3 is not changed. Since the input variable V _{IN is} now smaller than the values of the reference variables V _Ref1 and V _Ref2 , the comparison variables V _VO1 and V _{VO2 change} and pass through a wide range in the direction of the lower limit value V _L. As soon as the comparison _variable V _{VO2 falls below} the threshold _variable V _Sch , the current flowing from the threshold circuit SQ _1,1 is switched off. The value of the reference _variable V _Ref1 is therefore reduced by 2 V. Since the input variable V _{IN is} now again larger than the value of the reference _variable V _Ref1 according to FIG. 4b, the comparison _variable V _{VO1 changes} and rises up to the upper limit value V _H. It reaches this value at the time t _o -t _w , where t _{w represents} the conversion time. The _{values of} the reference _variables V _Ref1 or V _Ref2 or V _Ref3 after conversion are 5 V or 6 V or 4 V. These are the initialization _{values of} the reference _variables V _Ref1 , V _Ref2 , V _Ref3 for the subsequent analog / Digital transformation.

With comparison stages V₁, V₂, V₃, which are designed as comparators with a throughput time t _p = 100 ns, conversion times of less than 150 ns can thus be realized.

Claims (8)

1. Method for converting an analog input variable (V _IN ) into a digital output value with n bit positions (bit 1... Bit _n ) with a value of 2⁰ to 2 ^n-1 , characterized by the following process steps :

• a) for each bit position (Bit₁.. Bit _n ) a reference quantity (V _Ref1... V _Refn ) assigned to this bit position (Bit₁... Bit _n ) is formed, the value of which is at least as large as a value ( 2⁰... 2 ^n-1 ) of the respective bit position (Bit₁... Bit _n ) is the proportional minimum value of this reference _variable (V _Ref1... V _Refn ), the value of the bit position (Bit _n ) being assigned the highest value Reference variable (V _Refn ) is equal to the minimum value of this reference variable (V _Refn ),
• b) the input variable (V _IN ) is compared with the bit positions (Bit₁... Bit _n ) assigned reference _variables (V _Ref1... V _Refn ) and based on this comparison one for each bit position (Bit₁... Bit _n ) on the sign of the difference between the input variable (V _IN ) and this reference position (Bit₁... Bit _n ) to the ordered reference _variable (V _Ref1... V _Refn ) dependent and this reference point (Bit₁... Bit _n ) assigned comparison variable (V _{VO1 ...} V _VOn ),
• c) the reference value assigned to a bit position (bit ₁ ... bit _n-1 ) with a lower value than the highest value (V _Ref1... V _Refn-1 ) is the sum of its minimum value and the minimum values of the reference values ( V _Ref2... V _Refn ), which are assigned to those bit positions (Bit₂... Bit _n ) with higher significance, whose assigned comparison variables (V _VO2... V _VOn ) are larger than a threshold variable (V _Sch ) are assigned
• d) the input variable (V _IN) is compared for as long with the bit positions (Bit₁... Bit _n) associated reference values (V _Ref1... V _Refn) until none of the comparison variables (V _VO1... V _by) causes a change in the values of the reference _variables (V _Ref1... V _Refn ),
• e) the digital output value of a bit position (Bit₁... Bit _n ) is determined by the sign of the difference between the input variable (V _IN ) and this bit position (Bit₁... Bit _n ) assigned reference _variable (V _Ref1... V _Refn ).

2. Analog / digital converter for carrying out the method according to claim 1, characterized in that

• - It has a converter input (IN) at which the input variable (V _IN ) is present, and for each bit position (bit 1 ... bit _n ) one of these bit positions (bit 1 ... bit _n ) assigned a comparison stage (V 1 ... V) _n ), one of these bit position (Bit₁.. Bit _n ) assigned control unit (S₁... S _n ) and one of this bit position (Bit₁... Bit _n ) assigned converter output (D₁... D _n ), at which the digital output value has this bit position (bit 1 ... bit _n ),
• - the _(n Bit₁ bits...) Of a bit position associated comparison stage (V₁ V _n...) Has a with this bit position associated Wandleraus gear associated comparison output (VO₁ (Bit₁ bit _n...) (D₁ D _n...) ... L _n) to which. the this bit position (Bit₁.. bit _n) associated with the comparison value (V _VO1... V _in) is present, one connected to the converter input (iN) the first comparison input (+) and a second comparison input (-) and
• - the _(n Bit₁ bits...) Of a bit position associated control unit (S₁ S _n...) An with the second comparison input (-) of this bit position (Bit₁ bit _n...) Associated comparison stage (V₁ V _n... ) connected control output (SO₁.. SO _n ) at which the reference variable assigned to this bit position (Bit₁... Bit _n ) (V _Ref1... V _Refn ) is present, and for each bit position (Bit₂... Bit _n ) with higher significance one control input assigned to this bit position (Bit₂... Bit _n ) with higher significance (SI _1,1 ... SI _{1, n-1} ; SI _2,1 ... SI _{2, n-2} ; _.. SI _n1,1 ), which is connected to the comparison _output (VO₂.. VO _n ) of this bit position (Bit₂... Bit _n ) associated with higher valuation comparison stage (V₂... V _n ).

3. Analog / digital converter according to claim 2, characterized in that the input variable (V _IN ) and the reference variables (V _{Ref1 ...} V _Refn ) are voltages. 4. Analogue / digital converter according to claim 2 or 3, as characterized by that the (... Bit _k, k = 1, n) of an arbitrary Bitstel le associated control unit (S _k) an initialization (INI _k) with a Output and for each of their control inputs (SI _{k, 1} ... SI _{k, nk} ) a threshold circuit (SQ _{k, 1} ... SQ _{k, nk} ) with one with this control input (SI _{k, 1} ... SI _{k, nk} ) connected input and with an output and a summing circuit (Σ _k ), via which the output of the initialization circuit (INI _k ) and the outputs of the threshold circuits (SQ _{k, 1} ... SQ _{k, nk} ) with the Control output (SO _k ) are connected to this control unit (S _k ). 5. Analog / digital converter according to claim 4, characterized in that

• the initialization circuit (INI _k ) of this control unit (S _k ) is designed as an initialization current source (IQ _{k, 0} ),
• - The threshold value circuits (SQ _{k, 1} ... SQ _{k, nk} ) of this control unit (S _k ) are designed as switchable current sources (IQ _{k, 1} ... IQ _{k, nk} ) which are _configured via the respective control inputs (SI _{k , 1} ... SI _{k, nk} ) of this control unit (S _k ) can be controlled and
• - The summing circuit (Σ _k ) of this control unit (S _k ) is designed as a reference resistor (R _k ), at one connection of which the control output (SO _k ) of this control unit (S _k ), the output of the initialization circuit (INI _k ) and the Outputs of the threshold circuits (SQ _{k, 1} ... SQ _{k, nk} ) are connected.

6. Analog / digital converter according to claim 5, characterized in that

• an initialization current (I _{k, 0} ) present at the output of the initialization circuit (INI _k ) of this control unit (S _k ) is proportional to the value of the bit position (bit _k ) to which this control unit (S _k ) is assigned,
• - A switchable further current (I _{k, 1 ...} I _{k, nk} ) present at the output of a threshold circuit (SQ _{k, 1} ... SQ _{k, nk} ) of this control unit (S _k ) proportional to the value of the bit position (bit _k if bit _n), to which the this threshold circuit (SQ _{k, 1.. k. SQ, nk)} connected to the control input (SI _{k, 1...} SI _{k, nk)} of the control unit (S _k) is allocated,
• - The reference resistors (R₁, R₂, R₃, R _k ) of all control units (S₁ ... S _n ) are the same size.

7. Analog / digital converter according to one of claims 2 to 6, characterized in that the comparison stages as differential amplifiers, comparators or operations amplifiers are executed. 8. Analog / digital converter according to one of claims 2 to 6, characterized in that the one bit position (Bit₁... Bit _n ) assigned comparison output (VO₁ VO _n ) of a comparison stage (V₁... V _n ) via an adaptation stage (A₁.. A _n ) is connected to the converter output assigned to this bit position (Bit₁ Bit _n ) (D₁... D _n ).