WO1998057432A1

WO1998057432A1 - Analog-digital converter

Info

Publication number: WO1998057432A1
Application number: PCT/DE1998/001464
Authority: WO
Inventors: Rupert Glaser
Original assignee: Siemens Aktiengesellschaft
Priority date: 1997-06-09
Filing date: 1998-05-28
Publication date: 1998-12-17
Also published as: DE19724247A1

Abstract

The invention relates to an analog-digital converter with n comparator devices having a first and a second input and n reference-potential generating devices for applying an individual reference potential to a corresponding comparator potential device, wherein the comparator devices are connected to the analog signal to be converted in the first input and to the corresponding reference potential in the second input. At its output, the i-te comparator device supplies a bit with a given valence i of the digital signal corresponding to the converted analog signal. The highest-valent bit Q(n) has an n valence. The i-te reference-potential generating device is configured in such a way that it regulates the reference potential to be applied in the i-te comparator device depending on the fed-back bits whose valence j higher than i is, n, i, j being natural numbers and the relation being 1 ≤ i < j ≤ n.

Description

description

Analog / digital converter device

The invention relates to an analog / digital converter device which converts an analog input signal into a plurality of binary output signals, the conversion being carried out by comparator devices which are each connected to the analog input signal and an associated comparison potential generating device.

Analog / digital converters convert amplitude-analog input signals into digital output signals. In principle, three different processes can be distinguished during the conversion, namely the parallel process, the weighing process and the counting process. In the case of comparators which operate according to the parallel method, the analog input signal to be converted is compared at the same time by several comparators with different reference or comparison potentials. With analog / digital converters that work according to the parallel method, it is possible to obtain the converted digital signal in one step. These analog / digital converters with parallel comparators therefore have very short conversion times. However, a considerable disadvantage of this analog / digital converter with comparators connected in parallel is that the technical outlay for it is very high. An analog / digital converter with n comparators connected in parallel makes it possible to distinguish n + 1 different input signal ranges. 1 shows the basic structure of a conventional analog / digital converter with four comparators connected in parallel, which works according to the parallel method. The analog input signal U _e is applied to the respective first inputs of the four comparators Kl, K2, K3, K4. The comparative potentials of the comparators K1 to K4 are generated from a common constant voltage source U _e by means of a voltage divider consisting of four resistors R connected in series. The comparison potential for the comparator K4, whose digital output signal represents the bit with the highest value Q ₄ , is U _c . The comparison potentials for the further comparators K3, K2, Kl are 0.75 x U _c , 0, 5 x U _c and 0.25 x U _c with decreasing significance.

FIG. 2 shows the digital output signals Q _lt Q ₂ , Q ₃ , Q _{4 of} the known analog / digital converter shown in FIG. 1 with increasing analog input signal U _e . If the analog input signal U _{e is} zero, the four output bits Q _1; Q ₂ , Q ₃ , Q _{4 are} not set or are in the L state. If the respective comparison potentials of the comparators K1 to K4 are exceeded, the corresponding binary output signals Q1 to Q4 are set in succession. The bit with the lowest value Q_ goes into the H state if that

analog input signal - of the comparison potential U _c

4 is enough. Starting from the bit with the lowest value Q _x to the bit with the highest value Q _4, all bits Q_ to Q _{4 are} set with increasing analog input signal U _e . As can be seen directly from FIG. 2, five possible input signal ranges are defined in this 4-bit analog / digital converter with the four parallel comparators K1 to K4. For example, it forms the digital output signal

Q_, Q ₂ . Q ₃ 1 Q = 11 ⁰⁰ an analog signal range of - <^ ≤-

² "c -

<- from. The resolution of such a parallel 4

/ Digital converter, i.e. the analog input signal range that can be represented with a digital output signal is at

the 4-bit parallel analog / digital converter - the constant

4

Comparative potential U _c . In general, in a parallel analog / digital converter with n comparators, the resolution is the nth part of the comparison potential U _c . With an n-bit parallel analog / digital converter, the number of distinguishable analog input signal ranges is n + 1.

Table 1 shows the dependence of the output bits on the input signal voltage in the 4-bit parallel analog / digital converter shown in FIG. 1.

0 0 0 0 0 <u ^J „e <- -

4

0 0 0 ^ <U _e <s ^ü .

4 2

^ <U _e <^

2 4 3f,

1 1 1 0 - ≤ u _e u

4 1 1 1 1 u _c ≤ u _e

Table 1

Such parallel analog / digital converters do have a very short conversion time, since the digital output signal is formed in one step by the parallel comparison with several comparison potentials, but they have a relatively low resolution, since with n comparators only n + 1 analog input signal ranges can be defined. For a resolution of a measuring range in the range from 0 to 100 in steps of 1, 100 comparators are required with a parallel analog / digital converter. The technical effort increases to a very high degree with increasing measuring range of the analog input signal and with increasing desired resolution with such parallel analog / digital converters.

In addition to the parallel method for analog / digital conversion, the weighing method and the counting method for converting analog signals into digital signals are also used.

In the weighing process, the digital output signal is not generated in one step, but only one digit of the associated dual number is determined in each case. You start at the highest point and determine whether the input voltage is higher or lower than the reference voltage for the highest Place is. If the applied analog input voltage is greater than the reference voltage, the highest digit is set to logic "1" and the reference voltage is subtracted. The rest is compared to the next lower digit until the lowest bit is reached. So you need as many comparison steps as the dual number has digits and just as many reference voltages. Analog / digital converters that work according to the weighing method have the advantage that they only need a comparator for their construction, but the conversion times are very long.

The simplest known conversion method for analog / digital converters is the counting method. It is counted how often you have to add the reference voltage to the lowest digit until you get the input voltage. The number of

Steps are then the result. Such analog / digital converters, which operate according to the counting method, can also be implemented technically with a single comparator, but the conversion time is considerably longer than with the other methods.

While on the one hand parallel-analog / digital converters have high conversion frequencies and a low resolution, analog / digital converters, which operate according to the weighing method, have medium conversion frequencies and a higher resolution. Analog / digital converters that use the counting method have only very low conversion frequencies and a higher resolution than parallel analog / digital converters. Parallel-analog / digital converters enable an analog / Digital conversion in one step and thus very high conversion frequencies, but they are technically very difficult to implement, ie the technical effort, in particular the number of comparators required, is very high.

It is therefore the object of the invention to provide an analog / digital converter which is simple in construction and which has a short conversion time and a high resolution.

According to the invention, this object is achieved by the subject matter of claim 1, that is to say by an analog / digital converter device with n comparator devices with a first and a second input; and n comparison potential generating devices for applying a respective comparison potential to a corresponding comparator device; wherein the comparator devices are connected at the first input to the analog signal to be converted and at the second input to the respective comparison potential; the i-th comparator device supplies at its output a bit with a specific value i of the digital signal corresponding to the converted analog signal and the most significant bit Q (n) has the value n; the i-th comparison potential generating device is designed in such a way that it sets the comparison potential i-al to be applied to the i-th comparator device as a function of the feedback bits, the value of which j is greater than i; and n, i, j are natural numbers and the relationship 1 <i <j <n applies. The invention is based on the idea of coupling the binary output signals of the comparator devices back to the comparison potential generating devices and thus adjusting the comparison potentials of the comparator devices as a function of the digital output signals.

An advantage of the invention is that the feedback of the digital output signals to the comparison potential generating devices takes place asynchronously, i.e. the analog / digital converter according to the invention offers a very short conversion time without the need for an external clock.

Preferred further developments of the analog / digital converter device according to the invention are specified in the subclaims.

According to a preferred development, the i-th comparison potential generating device is designed in such a way that it applies the following comparison potential U. to the i-th comparator device:

= u _{const (1} + δu _x

where U _{const / 1} = - ^ for 1 <i <n

2

and

l = n where δU _x = Σ ß (* U _{const> 1} for 1 <i <n- 1 = ι + l

where U _{c is} a constant potential, i, 1 are natural numbers and bit Q (l ^{) has} the numerical values 0 or 1 according to its state.

This offers the particular advantage that the comparison potentials which are generated by the comparison potential generating devices can be set by suitable selection of U _c , taking into account the size of the analog input signal.

According to a further preferred development, the comparison potential generating devices each have at least one current source and a reference resistor connected in series with them.

The construction of the comparison potential generating devices from one or more current sources, which conduct an adjustable current via a reference resistor, offers the particular advantage that the comparison potentials can be set particularly easily and precisely without great technical effort.

According to a further preferred development, the comparison potential generating devices each have a constant current source. According to a further preferred embodiment the i-th constant current source outputs a constant current, which is the valence of the speaking _¬ belonging to the respective comparison potential generating means bits Q (i) weighted tet ent.

According to a further preferred development, the comparison potential generating devices, apart from the comparison potential generating device corresponding to the most significant bit Q (n), have respective controllable current sources which are each connected in parallel to the associated constant current source.

According to a further preferred development, the number k of the controllable current sources connected in parallel and contained in the i-th comparison potential generating device is

k = n - i with 1 <i <n.

According to a further preferred development, the controllable current sources of the i-th comparison potential generating device are controlled by the high-order bits Q (j), 1 <i <j <n.

The invention is explained in more detail below on the basis of preferred embodiments with reference to the accompanying drawings.

Show it: 1 shows the basic structure of a 4-bit parallel

Analog / digital converter according to the prior art with four comparators;

FIG. 2 shows the binary output signals of the 4-bit parallel analog / digital converter shown in FIG. 1 with an increasing analog input signal;

3 shows the basic structure of an embodiment of the 4-bit analog / digital converter according to the invention with four comparators;

4 (a) to 4 (h) the comparison potentials and the binary output

Signals which are generated on the embodiment of the 4-bit analog / digital converter according to the invention shown in FIG. 3 with an increasing analog input signal;

5 shows the binary output signals shown in FIG. 4 as a function of the analog input signal applied in tabular form;

6 shows a further preferred embodiment of the 4-bit analog / digital converter according to the invention with four comparators, the comparison potential generating devices in each case being connected in parallel by switched current sources and a reference resistor are formed;

FIG. 7 shows a further preferred embodiment of an analog / digital converter with 4 comparators, and

Figure 8 shows the signals present in Figure 7 in a timing diagram.

Fig. 3 shows the basic structure of an embodiment of the 4-bit analog / digital converter according to the invention with four comparators 1, 2, 3, 4. The comparators 1, 2, 3, 4 are expediently operational amplifiers and each do not have a first -inverting input (+) and a second inverting input (-). An analog signal U _e fed to the analog / digital converter is present via an analog signal input line 5 at the first inputs of the comparators 1, 2, 3, 4. The second inputs of the comparators 1, 2, 3, 4 are each connected to an associated comparison potential generating device 10, 11, 12, 13 via a corresponding line 6, 7, 8, 9 for applying a comparison potential. The comparators 1, 2, 3, 4 each have an output signal line 14, 15, 16, 17 for outputting a binary output signal Q _{1 (} Q ₂ , Q ₃ , Q ₄₎ .

With the exception of the output signal line 14 of the comparator 1 for the least significant output signal bit Q _x , the output signal lines 15, 16, 17 of the more significant binary output signals Q ₂ , Q ₃ , Q _{4 are} at branch points 18, 19, 20 a respective feedback line 21, 22, 23 is connected to the comparison potential generating devices, which belong to comparators with the binary output signals of lesser value.

The output signal line 17 of the comparator 4 for the binary output signal Q ₄ with the highest valence is connected via the feedback line 23 to the comparison potential generating devices 10, 11, 12 of all comparators 1, 2, 3 which are valued below. The output signal line 16 of the comparator 3, which outputs the binary output signal Q ₃ with the second highest binary valency, is connected via the feedback line 22 to the comparison potential generating devices 10, 11 of the two comparators 1, 2, which are valued below . The output signal line 15 of the comparator 2, which outputs the binary output signal Q ₂ with the second lowest binary value, is connected via the feedback line 21 to the comparison potential generator 10 of the comparator 1, which outputs the binary output signal Q with the lowest value. The output signal line 14 of the comparator 1 is not fed back. The comparison potential generating device 13 of the comparator 4 with the highest significance is not connected to any of the digital output signal lines 14, 15, 16, 17.

The mode of operation of the analog / digital converter according to the invention shown in FIG. 3 is described below. The comparison potential generating devices 10, 11, 12,

13 each apply a comparison potential to the second inputs of the comparators 1, 2, 3, 4 via the respective connecting line 6, 7, 8, 9. The comparison potential U ₄ applied to the connecting line 9 for the comparator 4 with the highest value is constantly set to a comparison potential U _c by the comparison potential generating device 13. The comparison potential, which is present at the second input of the comparator 4 with the highest valency, is independent of the bits Q ₁ which are present on the binary output signal lines 14, 15, 16, 17 _; Q ₂ , Q ₃ , Q ₄ . The comparison potential U ₃ applied to the connecting line 8 for the comparator 3 with the second highest value is set by the comparison potential generating device 12.

The comparison potential U ₃ output by the comparison potential generating device is composed of a constant component U _{const (3} and a variable component δU _3. The constant component U _{const / 3} is permanently set to a value which is determined by division of the constant comparison potential U ₄ = U _c by a weighting factor which corresponds to the value of the comparator 3. Since U _{3 is} the comparison potential of the comparator 3 for the binary output signal Q ₃ with the second highest value, the

constant proportion of its comparison potential to -

2 poses. The constant portion of the comparison potential for the comparator 3 with the second highest value is thus obtained by dividing the comparison potential U _c by the factor 2. 1 A det. The constant portion of the comparison potential U ₂ for the comparator 2 with the third highest value is formed by dividing the comparison potential U ₄ = U _c by a factor 4. The constant portion of the comparison potential U _x applied to the line 6 for the comparator 1 is formed by dividing the comparison potential U _c by the factor 8.

In general, the formula for the constant component U _{const α of} the i-th comparator is:

U, const.i in-ι) 2

where n is the number of comparators provided in the analog / digital converter according to the invention, U _{c is} the constantly set comparison potential for the comparator with the highest value n and i represents a run variable for the i th comparator device, 1 < i <n applies.

The constant components of the generated comparison potentials U _x , U ₂ , U ₃ , U ₄ are therefore for the 4-bit analog / digital converter shown in FIG. 3:

'-'const, l = =

2 ³ 8

'-'const, - = = y 4

'-'const, ₃ = 1 = 2 2 U = ^ = U

In addition to the constant component U _{const i} , the comparison potentials generated by the comparison potential generating devices 10, 11, 12, 13, with the exception of the comparison potential U ₄ for the comparator 4 with the highest value, also have a variable component, which depends on the binary output signals of higher significance is set. For example, the variable component of the comparison potential U ₂ for the second comparator 2 depends on the binary output signal Q _{4 of} the most significant comparator 4 and on the binary output signal Q _{3 of} the comparator 3 with the second highest value. The comparison potential generating device 11 for the comparator 2 sets the variable component δU _{2 of} the comparison potential U ₂ as a function of the feedback bits Q ₄ and Q ₃ .

In general, the variable component of the comparison potential of the i-th comparator is set by the comparison potential generating devices 10, 11, 12, 13 according to the following formula:

δU _t = ∑ Q (l) xUa t, ll = i + \

where i, 1 are run variables and Q (l) is the feedback binary output signal of the 1st comparator and can assume a numerical value 0 or 1 depending on its state, where n is the number of comparators provided and 1 <i <n-1 applies. For the nth comparator, the variable component is zero, as I said.

The comparison potential U_ generated by the comparison _{potential generating device} for the i-th comparator is therefore composed of the constant comparison _potential U _constιi and the variable, adjustable comparison potential δU _± _:

Ui = u _{const ri} + δu _±

For the exemplary embodiment of the invention shown in FIG. 3, the comparison potentials set by the comparison potential generating devices 10, 11, 12, 13, which are present at the second inputs of the comparators 1, 2, 3, 4, are as follows:

U _x = ^ + Q ₄ x U _c + Q ₃ x ^ + Q _{2 x} ü

8 2 4

U ₂ = ^ Q ₄ x U _c + Q ₃ x ^

4 2

U ₃ = - ^ + Q ₄ XU _c

2

U ₄ = U _c = constant potential

The binary output signal of a certain comparator with a certain value controls all by feedback Comparison potential generating devices for comparators with a lower value in comparison.

4 (a) to 4 ⁽ h ⁾ show the comparison potentials U _j . as well as binary output signals of the comparators Q_ for various analog input signal voltages U _e .

5 shows in table form the output signals Q _{1 #} Q ₂ , Q ₃ , Q _{4 of} the 4-bit analog / digital converter according to the invention for various analog input signal voltages U _e which are connected to the analog signal input line 5 of the analog / Digital converter is created.

As can be seen from FIG. 4 (a), the comparison potential U ₄ generated by the comparison potential generating device 13 is equal to the constant potential U _c .

4 (b) shows that the comparison potential

U ₃ , which is generated by the comparison potential generating device 12, has a constant component of 0.5 U _c , a variable component of U _c being applied when the most significant bit Q ₄ (FIG. 4 (h)) changes to the logical H state. The most significant bit Q ₄ is set when the analog input signal U _e on the input line 5 exceeds the comparison potential U ₄ (FIG. 4 (a)), ie when the input signal U _{e is} greater than U _c .

As can be seen from FIG. 4 (c), the constant portion of the voltage generated by the comparison potential generating device 11 is generated comparison potential U ₂ a quarter of U _c . When the binary output signal Q _{3 of} the third comparator (FIG. 4 (g)) is set, the comparison potential U ₂ for the second comparator 2 is increased by 0.5 U _c to 0.75 U _c . As can be seen from FIG. 4 (c), the comparison potential emitted by the comparison potential generating device 11 is gradually increased with an increasing analog input signal U _e , to a value of 1.75 x U _c .

As can be seen from FIG. 4 (d), the comparison potential which is output by the comparison potential generating device 10 for the least significant comparator 1 increases step by step with increasing input signal voltage U _e up to a value of 1.875 U _c .

As can be seen from FIG. 4, for example, an analog input signal U _e of 1.2 x U _c corresponds to a digital output value Q ₄ , Q ₃ , Q ₂ , Q _x = 1001. With an analog input

The output signal from U _e <- U _c are the binary output signals

8 all reset, ie Q ₄ , Q ₃ , Q ₂ , Q_ = 0000. With an analog input signal that is more than 1.875 U _c , all binary output signals assume the logic H state.

4 (a) to 4 (h) are summarized in table form in FIG. 5. As can be seen from the table in FIG. 5, the 4-bit analog / digital converter shown in FIG. 3 distinguishes 16 states according to the invention. In comparison to the known parallel 4-bit analog / digital converter shown in Fig. 1, which with four comparators only five analog Can distinguish signal ranges, the number of analog input signal ranges that can be defined by the analog / digital converter according to the invention is considerably increased. According to the invention, ⁿ different signal or voltage ranges can be defined with n comparators 2, whereas in the prior art analog / digital converter shown in FIG. 1 there are only n + 1.

The resolution of the analog / digital converter according to the invention

5, as can be seen from the table in FIG.

8th

- The constant applied to the most significant comparator 4

8th

Comparative potential U _c . In comparison, the resolution of the known parallel analog /

Digital converter - of the constant reference

4 tials U _c , as shown in Fig. 2. The analog / digital converter according to the invention thus has a significantly higher resolution, ie smaller distinguishable analog input signal intervals than the parallel analog / digital converter shown in FIG. 1.

In general, the resolution of the analog / digital converter according to the invention is as shown in FIG. 3:

where n is the number of comparators contained and U _c that of the comparison potential generating device for the highest comparator output is constant comparison potential.

The number of analog input signal ranges that can be defined by the analog / digital converter according to the invention is 2 ⁿ , where n is the number of comparators contained in the analog / digital converter according to the invention.

The mode of operation of the analog / digital converter according to the invention shown in FIG. 3 is explained using the following example, in which an input signal voltage U _e of 1.2 × U _{c is applied} to input 5 of the converter.

The initial state is at t <t ₀ Q ₄ , Q ₃ , Q ₂ , Q _x = 0000, the comparison potentials which are initially applied to the second inputs of the comparators 1, 2, 3, 4 by the comparison potential generating devices,

U ₄ = U _c ; U ₃ = ^ -; U ₂ = - ^; and U _x = ^

2 4 8

be.

At time t = t ₀ , an analog input signal of U _e = 1.2 x U _{c is applied} to the analog input line 5 of the analog / digital converter.

The following table shows how the binary output signals Q _{1 #} Q ₂ , Q ₃ , Q ₄ and those of the comparison potential Modification potentials given to generating facilities change.

t <t ₀ initial state i_ £. i_ £. 4 8

Applying U _e = = 1, .2 Uc t = t ₀

t = t, 1 1 1 1 _c 1.5U _C 1.7SU _C 1, 875U, t = t, 1 0 0 0 U _c 1.5U _e 1.25U _C 1, 125U, t - t, 1 0 0 1 Uc 1.5U _C 1.25U- 1.125U, t = t ₄ 1 0 0 1 c 1.5U _C 1.250. 1.125U,

e 2

As can be seen from Table 2 above, the digital output signal Q ₄ , Q ₃ , Q ₂ , Q__ = 1001, which corresponds to the analog input signal U _e = 1.2 U _c , at the time t = t ₃ , ie after three steps , reached. The conversion speed of the analog / digital converter according to the invention is therefore considerably increased in comparison to analog / digital converters which use the weighing method or the counting method.

If the input signal U _{e is} less than - U _c , the bi-

8 nary output signal Q ₄ , Q ₃ , Q ₂ , Q__ = 0000, and if the analog input signal U _{e is} more than 1.875 U _c , the digital Output signal Q ₄ , Q ₃ , Q ₂ , Q _τ = 1111 already reached after the first step.

In the known parallel analog / digital converter shown in FIG. 1, the binary output signal is already reached in the first step. The analog / digital converter according to the invention shown in FIG. 3 thus has a conversion speed which lies between the conversion speed of the parallel analog / digital converter and the conversion speed of analog / digital converters, which after the Weighing or counting processes work.

In comparison to the parallel analog / digital converter shown in FIG. 1, the analog / digital converter according to the invention shown in FIG. 3 has a lower conversion speed, but its resolution and the number of distinguishable analog input intervals significantly higher.

To achieve an equally high resolution, the known parallel analog / digital converter shown in FIG. 1 requires a considerably higher technical outlay than the analog / digital converter according to the invention. In terms of circuitry, the analog / digital converter according to the invention is very low compared to the parallel analog / digital converter, the conversion speed being only slightly reduced. The relationship between power and effort is therefore shown in the analog / digital converter according to the invention in comparison to that shown in FIG. put parallel analog / digital converter significantly improved.

FIG. 6 shows a further preferred embodiment of the analog / digital converter according to the invention shown in FIG. 3, in which the comparison potential generating devices 10, 11, 12, 13 are each formed from current sources connected in parallel and a reference resistor R. The comparison potential generating device 13 has a non-controllable current source 24 and a reference resistor 25 connected in series with it. The constant current _source 24 is supplied by a supply voltage V _cc and supplies a constant current which flows to the earth (GND) via the resistor 25. The comparison potential U _{4 present} at the second input of the comparator 4 via the connecting line 9 is a constant potential U _c , which is formed as follows by the product of the constant current of the constant current source 24 and the reference resistor 25:

U _c = I ₂₄ x R ₂₅ = constant,

The comparison potential generating device 12 has two current sources 26, 27 connected in parallel. The current source 26 is connected via a control line 28 to the feedback line 23, which is connected at the branch point 20 to the output signal line 17 of the comparator 4. If the binary output bit Q _{4 is set} at the output of the comparator 4 or assumes the logic H state, the controllable current source 26 outputs the comparison potential generation device 12 from a current I ₂₆ , which is equal to the current of the constant current source 24, namely

^ 26 ⁼ ^ 24 ⁼ ^ o

The current source 27 of the comparison potential generating device 12 is not controllable and, regardless of the binary output signal, outputs a constant current I .. which is half as large as the current I ₂₄ emitted by the current source ₂₄ .

'24

I ₂ 7 =

The currents emitted at the current sources 26 and 27 add up at the node 29 of the comparison potential generating device 12 and flow to ground (GND) via the reference resistor 30. As a result, they generate a comparison potential in the amount of:

U ₃ = 2S x Q ₄ + I ₂₇ ) x R 30 x Q ₄ __0) x R 30

The comparison potential generating device 11 has three current sources 31, 32, 33 connected in parallel. The current source 31 is a constant current source which has a constant

constant current of - supplies. The current source 32 is

4 controllable and is via a control line 34 to the feedback line 22 and the output line 16 of the comparator 3 connected. If the binary output signal Q _{3 of} the comparator 3 is set or assumes a logic H state, there

the controllable current source 32 a current of - from.

2

The controllable current source 33 of the comparison potential generating device 11 is connected via a control line 36 to the feedback line 23 and to the output line of the comparator 4. If the output binary signal Q _{4 is} set, the controllable current source 33 outputs a current of I ₀ . The currents emitted by the current sources 31, 32, 33 add up at the node 37 and flow to ground (GND) via the reference resistor 38. The comparison potential present at the second input of the comparator 2 via the connecting line 7 is:

U ₂ = (I 31 32 I ₃₃ ) x R ₃₈ = (- + QQ ₄ x I ₀ ) x R 38

2

The comparison potential generating device 10 has four current sources 39, 40, 41, 42 connected in parallel. The current source 39 is a constant current source and gives one

constant current from - down. The controllable power source

8 le 40 is connected via the feedback line 21 to the binary output line 15 of the comparator 2 and gives, if the output bit Q _{2 is} set or a logic high

State assumes a current of - from. The tax-

4 bare current source 41 of the comparison potential generating device 10 is connected via the feedback line 22 to the output line 16 of the comparator 3 and outputs with an output bit Q ₃ = H set, a current in the amount

from. The controllable current source 42 of the comparison potential generating device 10 is connected via the feedback line 23 to the output line 17 of the comparator 4. If the binary Asuangssignal Q _{4 of} the most significant comparator 4 assumes a logic high, the current source 42 outputs a current of I ₀ . The currents emitted by the current sources 39, 40, 41, 42 add up at the node 43 and flow to ground (GND) via the reference resistor 44.

The comparison potential J_ present at the second input of the comparator 1 via the connecting line 6 is therefore:

U _x = (I 39 + I ₄₀ + I ₄₁ + I ₄₂ ) x R, 43

= (- + Q ₂ x ^ + Q ₃ x ^ - + Q ₄ x I ₀ ) x R ₄₄

8 4 2

In a particularly preferred embodiment of the invention, the reference resistances of the comparison potential generating devices 10, 11, 12, 13, ie R ₂₅ , R ₃₀ , R ₃₈ , R _{44, are of the} same height, ie they all have the same resistance value R.

In a further preferred embodiment of the invention, the current value I _{0 of} the constant current source 24 in the comparison potential generating device 13 and thus the on the second input of the comparator 4 adjustable comparison potential U _c adjustable.

In a further embodiment of the analog / digital converter according to the invention, the current sources shown in FIG. 6 are replaced by corresponding voltage sources.

The invention is not restricted to the described embodiments. For example, the number of comparators can be increased as desired. Furthermore, it is expedient to connect a sample hold circuit to the analog signal input line 5 in order to ensure a constant input signal voltage U _e at the first input of the comparators. Furthermore, it is possible to provide a device at the output of the analog / digital converter according to the invention which determines that the analog / digital conversion has been completed, ie which states the states of the digital output signals Q ₄ , Q ₃ , Q ₂ , Q_ checks and determines when there is no change. After the end of the analog / digital conversion has been determined, the analog output signal Q ₄ , Q ₃ , Q ₂ , Q_ is then released for reading.

In the exemplary embodiment shown in FIG. 7, a total of 16 resistors R1 to R16 with a resistance value R are connected between a reference potential Uc and a reference potential. The individual divider taps are connected to the inverting inputs of the comparators K1 to K4 via a total of 11 switching devices UMSCH, which are connected according to FIG. The inverting input of the comparator K4 is connected to the divider tap between the resistors Rl and R9. The non-inverting inputs of the above Comparators K1 to K4 are connected to the input voltage Ue. The output of the comparator Kl is connected to the terminal Q0 of the switching device. The output terminals of the other comparators K2 to K3 are each connected to terminals Ql, Q2 and Q3 via a LATCH. Cables from a CONTROL control device also lead into this LATCH. Signals S1, S2 and S3 are carried on these lines. Cables lead into the control device COBTROL, which carry the clock signal CLK and the start signal START.

The associated time sequences of the individual signals are shown in FIG.

The circuit arrangement of FIG. 8 is suitable for realizing short settling times and small structures. The feedback on current sources explained in connection with the aforementioned figures has been modified. The individual reference levels are formed in the manner already explained. The switch cascades can be replaced by multiplexers with 4, 8 or 16 inputs and one output. A further improvement in performance can be achieved if the switch networks are precharged. This can be done as follows. In the idle state, all switches UMSCH, which are connected to the resistor divider Rl to R16, are open: A potential that corresponds to the voltage to be converted is fed in at this point. The switches UMSCH behind are switched to the Ote stage. This means that all capacities of the switch networks are pre-charged to the voltage to be converted. A reference level is determined in each conversion step, the voltage jump from the precharged value to the reference level becoming smaller and smaller with each step. With the LSB this is only + -1 / (2 xn). This is very advantageous because the capacity of the switch networks increases with falling value. (The switching network of the LSB has the greatest capacitive value.) To ensure stable states in the circuit arrangement of Figure 7 and to prevent swinging, each comparator K2 to K4 is preferably a LATCH nachgeschal _¬ tet. The control circuit CONTROL generates signals with de _¬ NEN stage by stage, the results are abgelatcht. The results from the MSB to the LSB are also valid here. Here _¬ means MSB most significant bit and LSB least significant bit.

Claims

claims

1. Analog / digital converter device with:

n comparator devices (1, 2, 3, 4) with a first and a second input (+, -); and

n comparison potential generating devices (10, 11, 12, 13) for applying a respective comparison potential (U _x , U ₂ , U ₃ , U ₄ ) to a corresponding comparator device (1, 2, 3, 4);

in which

the comparator devices (1, 2, 3, 4) at the first input (+) with the analog signal to be converted (U _e ) and at the second input (-) with the respective comparison potential (U _l; U ₂ , U ₃ , U ₄ ) are connected;

the i-th comparator device (1, 2, 3, 4) at its output (14, 15, 16, 17) each has a bit Q (i) with a specific value i of the digital signal corresponding to the converted analog signal (U _e ) ( Delivers Q (4), Q (3), Q (2), Q (D) and the most significant bit Q (n) has the significance n; the i-th comparison potential generating device (10, 11, 12, 13) is designed in such a way that the comparison potential (U _1; U ₂ , U ₃ , U ₃ , 4) to be applied to the i th comparator device ⁽ 1, 2, 3, 4) U ₄ ) as a function of the feedback bits Q (j) whose value j is greater than i; and

n, i, j are natural numbers and the relationship 1 <i _< j <n applies.

2. Analog / digital converter device according to claim 1, characterized in that the i-th comparison potential generating device (10, 11, 12, 13) is designed such that it to the i-th comparator device (1, 2, 3, 4) applies the following comparison potential TJ _L :

Ui = U _{const (i} + δUi

where U _{const ι i} = -j ^ for 1 <i <n

and

ln where δU _t = ι £ _{+ \} ^{Q {,)} * ^U const, ι for 1 <i <n- 1

and δüi = 0 for i = n where U _{c is} a constant potential, i, 1 are natural numbers and bit Q (l) has the numerical values 0 or 1 according to its state.

3. Analog / digital converter device according to one of the preceding claims, characterized in that the comparison potential generating devices (10, 11, 12, 13) each have at least one current source (24, 26, 27, 31, 32, 33, 39, 40, 41, 42) and a reference resistor (25, 30, 38, 44) connected in series.

4. Analog / digital converter device according to claim 3, characterized in that the comparison potential generating devices (10, 11, 12, 13) each have a constant current source (24, 27, 31, 39).

5. Analog / digital converter device according to claim 4, characterized in that the i th constant current source

(24, 27, 31, 39) outputs a constant current which is weighted in accordance with the value of the bit Q (i) belonging to the relevant comparison potential generating device (10, 11, 12, 13).

6. Analog / digital converter device according to claim 3 or 4, characterized in that the comparison potential

Generating devices (10, 11, 12), apart from the comparison potential generating device (13) corresponding to the most significant bit Q (n), have respective controllable current sources (26; 32, 33; 40, 41, 42) which are each connected in parallel to the associated constant current source (24, 27, 31, 39).

7. Analog / digital converter device according to claim 6, characterized in that the number k of the i-th

Comparison potential generating device (10, 11, 12, 13) contained, connected in parallel, controllable current sources

k = n - i with 1 <i <n

is.

8. Analog / digital converter device according to claim 6 or 7, characterized in that the controllable current sources (26; 32, 33; 40, 41, 42) of the i-th comparison potential generating device (10, 11, 12, 13) controlled by the higher order bits Q (j), where 1 <i <j <n.