DE1812178A1 - Integrated semiconductor circuit - Google Patents

Description

Integrated semiconductor circuit

The invention relates to an integrated semiconductor circuit and to a method for the production thereof and, in particular, to an integrated circuit which consists of monocrystalline regions which are mutually both duroh ροIykristalline regions with a higher resistance than are also separated by the pn-T junctions.

So far, various methods for decoupling the switching elements from integrated semiconductor devices have become known, but these are methods known from the prior art afflicted with deficiencies, for example in the imperfect decoupling of the switching elements of the finished integrated circuit and lie in the use of diffusion processes, which require a considerable amount of time in the manufacturing process. With the usual Manufacturing methods, for example, is also a problem like that to take into account the generation of a high stray capacitance, which leads to mutual interference between the individual switching elements.

According to the Brfinduag, the selected ones are served

Place

909828/1150

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BATH ORIGINAL

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Circuit are required *

Figures 2A to 2? a number of SkiBeen for demonstrating the various stages of manufacture of an integrated semiconductor circuit according to the invention shown in the side view;

FIG. 3 shows a circuit diagram of that embodied in FIG semiconductor integrated circuit;

Figure 4 «in the associated spare circuit diagram;

FIGS. 5A to 5F and 6A to 6l are a series of further sketches similar to those of FIG. 2, which serve to illustrate the individual process steps in the context of modified embodiments of the invention * and M.

FIG. 7 is a circuit diagram of the one shown in FIG integrated semiconductor circuit.

For a better understanding of the invention should first with reference to FIG. 1, a method known from the prior art for producing an integrated semiconductor circuit will be discussed in greater detail.

First, on a p-type semiconductor substrate 1, which is silicon, for example, one of an n-layer and an η-layer using the customary vapor deposition process existing vapor deposition 2 formed with double structure, like this shown in Figure IA. The vapor deposition surface 2 is then selectively etched, for example in the manner of a checkerboard pattern, where RiI-I len 3 are formed, which are deep enough that they sioh up to that Substrate 1 extend, thus creating islands 4, some of which are shown in FIG. 1B. The entire surface of the islands 4 and the grooves 3 are then covered with an insulating pad 5 coated, which may for example consist of Silioiumoiyd, after which on this insulating layer 5 by vapor deposition of Silioium a polycrystalline silicon layer 6 is formed as shown in FIG Figure IC is shown. In the case of the polycrystalline silicon layer 6 Sometimes it is a glass sintered glass.

The polycrystalline silicon alloy 6 is then lapped from the surface until the islands 4 are illustrated in FIG

90982B / 1150

echauliohten way are exposed. Here should preferably only the silicon soles ent 6 are subjected to the Lftppvorgang while the insulating layer 5 deposited on the islands 4 is reversed should stay, but in practice it comes with lapping with probability to different degrees of material removal at certain points or surface areas of the silicon layer 6, so that, for example, the island 4a may be abraded too much, as shown in Jlgur ID. So are before training the silicon layer 6, for example, switching elements each of the islands has been formed, they become these switching elements destroyed if the islands collapse. will. If a transistor is made by playing white # on each of the islands After the lapping process, a base zone is created using a diffusion process and an emitter zone is formed, including the individual values the limit voltage of a collector edge layer and the residual resistance from predetermined values, so that it is not possible to achieve the desired integrated semiconductor stereo devices in this way reach.

The object of the invention is to remedy the above-mentioned deficiencies off, which is to be explained in the following with reference to the drawings in detail by way of example.

FIGS. 2A to 2F serve to explain a sequence of method steps as are provided in the production of the integrated semiconductor circuits created by the invention. The first of these method steps consists in the preparation of a single-crystal silicon semiconductor substrate 1 such as that shown in FIG. 2A, which has a predetermined conductivity type, for example ρ-conductivity. The monocrystalline semiconductor substrate 1 is coated with an oxide layer 2, for example with SiOp, which then functions as a diffusion mask, and this oxide layer 2 is removed at the points provided for this purpose by etching or in a similar manner, so that the oxide layer 2 in its entirety For example, a checkerboard pattern remains. An n-type impurity is then diffused into the substrate 1 through the oxide layer 2 serving as a mask, so as to form a plurality of n ⁺ -semiconductor zones 3 and 3 'in the substrate 1

909828/1150

as shown in Figure 2B. Subsequently, the oxide resist formed during diffusion of the n-impurity on the n * -semiconductor zones 3 and 3 'are removed, whereby a semiconductor with a relatively low concentration of impurities, for example an intrinsic semiconductor, is deposited on the monocrystalline silicon substrate 1 by vapor deposition. Oxydsohloht 2 forms nucleation sites on which polycrystalline layers 4 with high resistivity or high specific resistivity arise, while monocrystalline solids 5 and 5 'form on n * -Halterzones 3 and 3', as shown in the illustration in FIG. 2C au can be found. The monocrystalline pads 5 and 5 ¹ serve as switching elements, for example as collector zones of a transistor, as can be seen from the following description. The monocrystalline soles 5 and 5 'adjoining the η -semiconductor zones 3 and 3' become n-zones, since the foreign matter of the n ⁺ -semiconductor zones below the soles 5 and y diffuses into them during the above vapor deposition process. The oxide layer here has a thickness of about 5000 ingströmunhciten, while the temperature during vapor deposition is kept in the range of 1050 to 125O ⁰ C and the monocrystalline soles 5 and 5 '> u are formed with a thickness of about 5 microns. If it is assumed that the n-foreign substance of the n ⁺ -semiconductor zones 3 and 3 * diffuses into the polycrystalline soles 4, as indicated by the arrows in FIG 5 and 5 ') are as wide as possible in order to increase the resistance of the polycrystalline solids 4 more effectively and quietly, while the silicon dioxide layers in the embodiment shown in FIG. even if the nucleation points for the construction of the polycrystalline structure are polycrystalline SiIioiumsohlohten, which can be formed, for example, by vapor deposition, or scratches, grooves or the like that are formed in the substrate surface.

In order to form semiconductor components in the single-crystal n-type layers 5 and 5 ', a p-type foreign substance is then used as in the case of-'

for example

909828/1150

For example, boron (B) by the oxide surface 6 serving as the mask diffuses into the monocrystalline layers 5 and 5 ^{1 in} order to form ρ semiconductor zones 7 and 7 ¹ , which then serve as base zones in the finished transistors, as shown in the illustration in FIG Figure 2D emerges. Then, in the manner illustrated in FIG. 2E, an η-impurity 6 serving as a mask is allowed to diffuse into the p-semiconductors 7 and 7 *, so that η -semiconductor zones 8 and 8 'are formed which serve as emitter zones. Semiconductor components (transistors) are thus formed in each case in the single-crystal layers 5 and 5 '. Furthermore, a thin-film component, for example a thin-film resistor 9, is formed by vapor deposition of metal or the like on one surface of each polycrystalline layer 4 through the oxide layer 6, as shown in FIG. 2F. Thereafter, a metal such as aluminum is vapor-deposited so that electrodes 10 are formed in a predetermined arrangement on the semiconductor components formed in the monocrystalline layers 5 and 5 'and that lead parts for connecting the electrodes formed in a predetermined arrangement to one another and lead parts 11 for connecting the one ; Correct arrangement of electrodes with * \ m I5ünr, oMohtbauelemente 9 ®ntst @ h®n. Figure 3 illustrates a Sohaltsoheiß £ for the thus formed semiconductor integrated circuit. Although the diffusion regions 3 and 3 ¹ during the subsequent vapor deposition process used as impurity sources, these zones brauohen nioht in each case provided to be vapor deposition rrobei in this case AUOH ohnedem proceeds more and whereupon a non-ferrous substance is diffused from the surface into the “steam on” chioht formed in this way, in order to form the layers 5 and 5 ^{1 in it} . However, the method which is based on the formation of zones 3 and 3 * is of greater simplicity in terms of production technology and guarantees better operating properties of the semiconductor arrangements finally obtained.

The semiconductor integrated circuit constructed in this way is shown in FIG see the individual, in the monocrystalline crystals 5 and 5 * formed semiconductor components as well as between the semiconductor components and the thin-film component 9 · 1η high Is © -

capacity

909828/1150 BAD OPr ₁ GlNAL

capacity, so that a complete decoupling of the components formed on the same substrate is guaranteed. As a result, mutual interference between the components is avoided, and these components are to be regarded as whether they would be applied to separate substrates so that an increase in their properties can be expected.

In Figure 4, an equivalent circuit is shown for the thus constructed semiconductor integrated circuit, wherein by the reference numerals 5 and 5 ^1, the single-crystal n-Schiohten 5 and 5 ¹ of Figure 2, - the reference numeral 1, the monocrystalline · p-type semiconductor substrate and by the reference numeral 9 the Dünneohiohtbauelement are designated. With the reference number D, the pn-area diode is denoted by the ρ-semiconductor substrate 1 and by the n ⁺ -semiconductor zone 3 arranged under the monocrystalline n-layer 5 and by the reference number L- a further pn-area diode, which by means of the p Semiconductor substrate 1 and duroh the n ⁺ semiconductor zone 3 ¹ lying under the monocrystalline n-layer 5 ¹ is formed. The reference character H ^ denotes the resistance of the ppIycrystalline layer 4 arranged in the horizontal position between the two monocrystalline layers 5 and 5 'and there? _: Reference number R ₂ the resistance of the polycrystalline layer 4 arranged underneath the thin-film component 9, also in the horizontal plane, furthermore with the reference number C, denotes a capacitor, which through the polycrystalline material 4, the thin-film component 9 and through the wipe-added oxide layer 6 is formed, as well as with the reference sign C _? another capacitor formed by the polycrystalline layer 4 itself. Tests have shown that the polycrystalline Sohioht 4 shows a specific resistance that exceeds the value of 100 ohm centimeters, and that it consequently has a very high resistance and can be regarded as a dielectric or insulator, which is why only the capacitive component of the vertical polycrystalline Sohioht 4 is shown, while the ohmic component is omitted. Numeral C- denotes a capacitor formed by the polycrystalline substrate 4, the semiconductor substrate 1 and the oxide layer 2 interposed therebetween.

As

909828/1150

"Ke from 3? Igur 4 iaex ', is iio monocrystalline as ScMoIi 5 against the SJubstrai 1 eferefe the pn-area diode J} _{? As} well as the monocrystalline layer 5 ^! Ilurefa the polycrystalline layer 4 -roll adhered with holiea Wiäerstsaid constantly isolated The single-crystal layer 5 ⁵ is in turn completely insulated from the substrate I by the flat diode B ₉ and from the thin-film component 9 by the polycrystalline fuse 4 and by the capacitor CL.

lates. 331 © semiconductor components formed on the single crystalline layers 5 ^ and 5 'are therefore completely decoupled in this way, as if they were applied to substrates that are viewed separately from one another, and mutual interference between the components is thus avoided. In addition, the voltage of the decoupling between the semiconductor components is only determined by the limit voltage of the pn junction provided in each of the islands. So there is no transition zone on the surface of the component, the residual voltage in the usual semiconductor components is extremely low, so that the limit voltage can be increased.

is the Süirasohiehtbauelement 9 against the Süisstrat 1 and geg »R, the ®iiii: ristalliae layer 5 ^J iureh the capacitors C, <, C _1, C iowie anti duroh resistor l _o completely insulated. Accordingly, the semiconductor components provided with the monocrystalline layers 5 ^ .nd 5 »and that on the? The thin-film component 3 provided for oxide layer 6 is decoupled in a well-insulated state, and the components can therefore not have any influence. The operating characteristics of semiconductor devices cannot be deteriorated in any way, so that the invention is of particular value for the manufacture of integrated circuits of the kind in which a number of switching elements are provided on the same substrate , la the capacitors C ,, 0 "and C ₃ , between the Sünnsehiehbauelemeni 9 and the substrate 1 g®- i9ohalt" t "inst also the capacitance between these are low, • o that care is taken to reduce the parasitic capacitance effect let, furthermore, the surface exhibits the polycrystalline

4 ff ancillary within «tiaiea areas of 2 ms 5 microns and the oxide roof layer 6 formed on this is the same

uneven

409-828 / 1150

uneven. The surface area of the Oxydsohioht 6 is therefore increased approximately β and the sizes typical for the thin Sohioht, for example that is, the thin-film resistance value or the capacity per unit area are increased as a result, and the thin-film construction learns shows, thanks to the unevenness, a good adhesion to the Oxydsohioht 6. In addition, a du raw shows the Dünnsohiohtbauelement formed passive element has a higher value, a lower temperature coefficient and a higher accuracy than one in that Substrate formed by diffusion.

FIG. 3 shows the procedural steps in a modified embodiment of the invention. First of all, a monocrystalline semiconductor substrate with a predetermined % conductivity character, for example with p-conductivity, is prepared in the quiet, as shown in FIG. 5A. On the monocrystalline semiconductor substrate 21 an oxide layer 22, such as SLO_, is deposited, which is removed again at certain selected areas by means of etching or in a similar way. An η-impurity is then allowed to diffuse into the semiconductor substrate 21, the oxide layer 22 serving as a mask, so that an n ⁺ semiconductor zone 23 is formed, as can be seen from FIG. 5B. Subsequently, the Oxydsohioht on the n ⁺ -Halbleiterzone 23 and on the substrate 21 at selected locations in the embodiment shown in Figure 50 manner is etched away, whereupon a semiconductor material having a low impurity concentration, for example, g i-conductive material is evaporated onto the substrate 21st In this way, polycrystalline zones 24 with high resistance are formed on the oxide layer 22, while on the n ⁺ -semiconductor zone 23 and the substrate 21, in contrast, single-crystal solids 25 and 26, respectively, as can also be seen from the illustration in FIG. 5D. In this case, however, the single-crystal layer 25 on the η -semiconductor zone 23 assumes n-conductivity character due to diffusion of the n-impurity of the zone 23 during the evaporation process, while the single-crystal layer 26 covering the substrate 21 in a corresponding manner during the evaporation process as a result of a diffusion β of the p Foreign taffy of the p-type substrate 21 becomes p-type. For the formation of a semiconductor component in the monocrystalline

linen

* ^{AD 0} FfIQINAL 1 909828/1150

181

lln · »n-Sokioht 25 becomes in this © © inkslstallin © Soaah 25 under Yenrenduag- eis« O ^ dsehiofet 2f sis Haste ei.u ρ »foreign matter © indif- m that it forms ice © ρ-semiconductorssm © ti, like this is sung 'in 5E-. Thereupon, the oxide layer 2f al «mask, iron n - foreign matter in di © p-Ealble'itersone 28 βi & diffuse» w & s® iron B-half-lter zone 29 to form ₅ dl © la Figure 5F derg® istc Here the a-Premdstoff gleiofeaiiiitig auoii & r © li the ale Msske SieneKd © Oxyasohicht 27 in di "single crystal !!)" - p-SeMe & t 26 aiadiffKixdies't ρ so that it forms eia® nH & lleiterzone 50 "wsdioaswidorg a Hiff -tana is geoehaffen. In this way, la dos © iakristalüaea SfefaiüM-ten 25 uaa 2β das Hslaleitertosmeleiaaat beaissengsueis © der dureh. the. Eiffusionevorgaag formed lliäerstaßd auegeformd. If necessary, as in the case of FIG. 2, integrated semiconductor triofesltung, a thinnessliicrh -tbeuslemesit _s trbindun-galeltungen slectrodes

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ORIGINAL BATHROOM

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Correct, selected surface area removed, after which sin i-conductive semiconductor material is deposited on the substrate 31 by vapor deposition, as shown in Figure ÖD. As a result, polycrystalline layers 35 with high resistance are formed on the individual parts of the oxide 32 and monocrystalline layers <6 or 37 ^{on the p +} -semiconductor-, sone 34 and on the n ⁺ -semiconductor zoae 35B. The egg-crystalline layer 36 lying over the p ⁺ -semiconductor zone becomes p-conductive as a result of the diffusion of the p-impurity of the p ⁺ -semiconductor zone 34 during the evaporation process and in a similar way the monocrystalline layer lying ^{over the n + -suction conductor 33B becomes p-conductive through the} The n-type impurity of the n ⁺ -semiconductor zone 33B diffuses in during the vapor deposition process of an η-conductive layer. The i-type Torerwähnte%, on the vapor layer may be formed after the oxide layer has been removed in the Yeiae 32 is that their bands or so about the H ⁺ -HaIbICiteraone 33A away grab "as the" in Figure 6D "'. In order to form semiconductor components in the ρ-conducting monocrystalline layer J6 and In the η-conducting monocrystalline layer 37, an n-type foreign substance is then diffused into the monocrystalline p-layer 36 through an oxide layer 38 serving as a mask, so that an n Semiconductors 39 are formed, whereupon a p-free detaff is allowed to diffuse in through the oxide layer 38, which serves as a mask, in the form of single-crystalline solids 40 su, as shown in FIG. 6F. liernaoh becomes into the monocrystalline ρ-layer 36 | ~ λώ. & flalbleiterzone n-39 in the diffused using the Oxydaohieht 38 as a mask, p-type impurity, so that the geaeigten in figure Sa p ⁺ -Halbleitereonen 4I and 42 form. If necessary, the p-semiconductor ^{zone 40 and the p +} -halter zones 4I and 42 can be formed on the same side. As the next step, an n-type impurity is diffused into the monocrystalline n-layer 37 and into the p-half isiter zone 40, so that n ⁺ semiconductor zones 43 and 44 form, as shown in FIG. 6H. In this way, pnp- unu in the monocrystalline layers 36 and ^{r j7.} npn-fransistören trained. Then by evaporation. of metal or the like on a designated area

throat area

309 ^ 28/1150

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surface area of the applied to the polycrystalline surface 55 Oxydsohioht J8 formed a thin-film component, for example a thin film resistor 45 as shown in Figure 61. Then is formed on the single crystal layers 36 and 57 Semiconductor components a metal such as aluminum. vapor-deposited so as to provide electrodes in a predetermined arrangement 46, line parts for connecting the in a predetermined Arrangement provided electrodes with each other and lead parts 47 for connecting the electrodes provided in a predetermined arrangement to be formed with the thin-film component 45. In Figure 7 is a Sohaltschema for the integrated semiconductor circuit produced in this way shown, wherein a resistor R. corresponds to the thin-film resistor 45, while a resistor R, in Figure 6l is not shown.

Since in the context of the invention, the lapping process is no longer necessary comes as an introduction to the one known from the state of the Teohnik The method described with reference to FIG. 1 is required, the invention enables the production of an integrated semiconductor circuit much easier with switching elements of stable operating characteristics.

Needless to say, numerous modifications and variations are possible which come within the scope of the invention fall.

Claims

9 0 9 8 2 8/1150

Claims (13)

■ - 13 - claims · 1. Integrated semiconductor circuit with a monocrystalline semiconductor substrate and a vapor deposition adjoining the monocrystalline semiconductor substrate, characterized in that the vapor deposition layer (4, 5, 5 ¹ ) consists of a large number of polycrystalline layer areas (4) of high resistance and a large number of the polycrystalline layer areas (4) single-crystal layer series (5, 5 ') separated from one another. 2. Integrated semiconductor circuit according to claim 1, characterized in that ^{pn junctions are provided between the monocrystalline layer regions (5f 5 1} ) and the monocrystalline semiconductor substrate (l). ^ J. Integrated semiconductor circuit according to Claim 1, characterized in that that the monocrystalline layer areas (5, 5 ') from each other are electrically decoupled. 4. Integrated semiconductor circuit according to one of the preceding claims, characterized in that in the monocrystalline semiconductor substrate (l) a plurality of diffusion ^{zones (3, 3 1} ) is provided with a high level of interference, the diffusion zones (3r 3 ") having opposite conductivity character as that monocrystalline semiconductor substrate (1) and adjoin the respective monocrystalline layer regions (5, 5 ¹ ). 5 »A semiconductor integrated circuit according to claim 4 marked ä» characterized shows that the diffusion zones (3, 3 ') have the same conductivity as the monocrystalline layer areas (5, 50- 6. Integrated semiconductor circuit according to one of the preceding claims, characterized in that a second diffusion ^{zone (7 »7 1} ) of opposite conductivity character to that of the monocrystalline Schiohtbereich (5, 5") is provided ^{in at least one of the monocrystalline Sohlchtbereiehe (5, 5 1)} is. 7 Integrated semiconductor circuit according to Claim 6, characterized in that that a third diffusion zone (8j 8 ') is provided in at least one of the second diffusion zones (7, 7'). 8/1160 8, a method for producing an integrated semiconductor circuit with the process steps of preparing a single-crystal semiconductor substrate of one conductivity type, the selective formation of nuclei on the single-crystal semiconductor substrate and the formation of a vapor deposition layer on the single-crystal semiconductor substrate, characterized in that the vapor deposition (4, 5, 5 ¹ ) simultaneously a multitude of monocrystalline layer areas (3, 5 ¹ ) and a multitude of polycrystalline layer areas (4) of high resistance are formed, the single crystalline layer areas (5 »5 ¹ ) being separated from one another by the polycrystalline layer areas (4) are. ■ Process for producing an integrated semiconductor circuit according to Claim 8, characterized in that the process step is the diffusion of a premed substance into at least one of the monocrystalline layer areas (5t 5 ¹ ), this foreign substance having opposite conductivity characteristics to the single crystalline layer areas (5 »5 ') · 10. A method for producing an integrated semiconductor circuit according to claim 9i, characterized in that the process step is the diffusion of a Premdstoffes in the diffusion zone (7, 7 ^f ) for the formation of switching elements (7 »8 $ 7 '» 8 ¹ ) is provided. 11. A method for producing an integrated semiconductor circuit naoh claim 10, characterized in that the formation of conductive layers (10, 11) sum mutual connection of the switching elements (7 »8j 7 '» 8 ¹ ) is provided as a procedural step, 12. A method for manufacturing a semiconductor integrated circuit according to claim 8, characterized in that in the monocrystalline Semiconductor substrate (1) selectively diffusion sensors (3 9 3 ') formed are, these diffusion zones (3, 3 ″) opposite conductivity character like the semiconductor substrate (l). 13. A method for manufacturing a semiconductor integrated circuit according to claim 8, characterized in that the subsequent process step is the diffusion of a foreign substance of opposite conductivity character like that of the monocrystalline semiconductor substrate (21) is provided in the monocrystalline layer regions (26). 909828/1150