DE2738614A1 - Integrated circuit module - produced by glass film bonding one substrate for silicon island domains to another as carrier - Google Patents

Abstract

A semiconductor substrate for integrated circuits is produced by mfg. 2 monocrystalline semiconductor wafers and by forming insulating grooves in the desired pattern on the first, and covering its whole surface by a dielectric insulating layer. A bonding layer is applied over this or over a silicon dioxide coated major surface of the second water and both wafers are firmly joined together. The first wafer is finally polished or etched away from its rear face to the bottom of the grooves. This creates many monocrystalline island of even thickness in the substrate and results in a better integration density. The penetration of other than the preselected impurities into the island domains is prevented, resulting in excellent electrical properties of the modules.

Description

Method for manufacturing semiconductor substrates

for semiconductor integrated circuits The invention relates to generally to a method for manufacturing semiconductor substrates for integrated Semiconductor circuits, in particular a method for producing semiconductor substrates for integrated circuits by mutually connecting two semiconductor bitrates by a dielectric insulating layer such as oxide layer clay and binder clay made of an insulating material such as glass.

Generally, has a semiconductor substrate for integrated circuits a structure in which a large number of single crystal semiconductor island regions, in which various circuit components, such as thyristors, transistors, Resistors and the like are to be formed on mutually insulating support areas is held. Accordingly, one must good electrical isolation between the monocrystalline semiconductor islands.

Typically, the method for obtaining such Divide isolation into two groups.

According to one method, pn junctions are made in a monocrystalline Semiconductor plate formed by diffusing an impurity and backwards biased so as to move the single crystal semiconductor islands from one another through the reverse to isolate biased pn junctions (hereinafter referred to as pn junction isolation method designated). The other method is based on the fact that the several monocrystalline Semiconductor islands from each other by dielectric insulating layers such as silicon dioxide layers and glass, are insulated from one another, with them on associated support areas are held. The latter method can be called a dielectric isolation method are designated.

The pn junction isolation process that was used long ago in the Development of the integrated semiconductor circuit was specified, is disadvantageous in that as large stray capacitances between the isolated monocrystalline semiconductor islands are present and disrupt the normal operation of the integrated semiconductor circuits, a high voltage resistance suitability is not satisfactorily available, the integrated Semiconductor circuit arrangements are not usable in such places where they exposed to radioactive radiation, etc. Attempts to eliminate the drawbacks of the above-described pn junction isolation type integrated circuit substrate then led to the development of the semiconductor substrate of the dielectric isolation structure, and many proposals have been made in this area.

For example, U.S. Patent 3,909,332 discloses a method of manufacturing a dielectrically isolated semiconductor substrate for integrated circuits. According to the teaching of this patent specification, a pair of single-crystal semiconductor wafers is produced ago, of which at least one with an insulating layer and a glass layer with a softening point below that of the semiconductor substrate and one that of the semiconductor substrate almost the same coefficient of thermal expansion is formed. Both tokens will then bonded along the interposed glass layer by thermal pressure bonding. In of the specification of this U.S. Patent 3,909,332 is a glass composition comprising 15 to Contains 20 mol% boron oxide (B203) and the remainder silicon dioxide (sie2) and a coefficient of thermal expansion which almost corresponds to that of silicon, described as a connection layer, which is suitable for connecting the two semiconductor wafers. As an example Embodiment for illustration purposes is a silicon expansion or

Voltmeter explained. Although it is stated that the teaching of this Patent specification on the manufacture of monolithic integrated circuits can be applied is not a specific example in the description of the US patent disclosed.

In practice, for the manufacture of a semiconductor substrate for the integrated circuit there are special requirements, which are different from those in the Manufacture of a strain gauge or tension meter are noticeably different.

First, in the case of the semiconductor substrate for semiconductor integrated circuits a high integration density is of great importance. In other words it is about how many circuits or components in a given area of Substrate can be formed. Second, all single crystal semiconductor island areas must be have the same depth as the semiconductor substrate, in one of its main surfaces the insulating grooves are formed from the opposite major surface through Polishing or etching to the level corresponding to the bottom parts of the insulating grooves must be partially removed in order to preserve the island areas. When the individual single crystal island areas do not have the same thickness, a case may occur that those in the island areas are less than a certain value Thick circuit elements formed do not work properly. Also, it can be under under these circumstances, the adjacent single-crystal island regions occur on Isolating groove part adjoin each other, so that the desired mutual isolation is no longer achieved.

Third, the island areas must be protected against intrusion impurities other than those required to form the circuit elements are provided.

In particular, bring two semiconductor wafers with a glass layer are interconnected to form the substrate for the integrated circuit to obtain the contaminants contained in the glass layer, such as e.g. Boron, phosphorus, and the like, into the island areas through the dielectric layer possibly lead to a deterioration in the electrical properties of the circuit elements in these island areas. Therefore, it is necessary that the impurities penetrate to suppress.

The invention is based on the object of a method for manufacturing of semiconductor substrates for integrated semiconductor circuits to develop that an improved Integration density allows the same thickness a plurality of monocrystalline semiconductor island regions ensured in the substrate and ingress of contaminants other than that used to form preselected circuit elements required, prevented in the single crystal semiconductor island areas so excellent electrical properties of those in the single crystal semiconductor areas to secure formed circuit elements.

The subject of the invention, with which this object is achieved, is in claim 1 characterized method.

To implement the invention, two monocrystalline cells are first made Semiconductor wafers, forms isolation areas in a certain pattern in a main surface of the one semiconductor die, forms a dielectric Isolation layer over the main surface containing the isolation areas a connection layer either on the insulating layer of one semiconductor die or a major surface of the other die connects the two Semiconductor wafers by means of the bonding layer at a certain high temperature and under pressure (thermal pressure bonding step), partially removes a semiconductor from the other main surface to. to the level of the bottom part of the isolation areas, thereby obtaining a plurality of the single crystal island regions mutually are isolated by the dielectric insulating layer and the insulating regions.

According to one embodiment of the invention, a glass of the boron oxide group is used with 3 to 10 mol% boron oxide (b03) rAr the connecting layer is used.

The invention is illustrated with reference to the in the drawing Embodiments explained in more detail; These show: FIGS. 1A to 1E in vertical sectional views of a semiconductor substrate for integrated circuits at different levels the production according to an exemplary embodiment of the invention; Fig. 2 in a vertical sectional view of a semiconductor substrate for an integrated circuit, which after a second Ausrührungsbeispiei the invention is made; 3 in vertical section of a semiconductor substrate for an integrated circuit, which according to a third Embodiment of the invention is made; Fig. 4 is a vertical sectional view of a semiconductor substrate for an integrated circuit on a specific Stage their production according to a fourth embodiment of the invention; and Fig. 5 is a vertical sectional view of a semiconductor substrate for integrated Circuits at a certain stage in the manufacturing process after a fifth Embodiment of the invention.

Referring to Fig. 1A, there are two platelets of single crystal silicon substrates 11 and 12 provided. The first single crystal Silicon substrate 9 is for the formation of the single crystal silicon island regions at the end of manufacture determines and has a certain conductivity type, a certain resistance, a specific plane orientation and thickness. For example, can the substrate 11 has the N conductivity type, a resistance of 1 to cm, (100) plane, a 50 mm in diameter and 300 μm in thickness. The second monocrystalline Silicon substrate 12 is intended for use as a support area. Hence surrendered there are no restrictions with regard to the conductivity type for the second substrate 12, the resistance, the crystal plane orientation, etc. The thickness of the substrate 12 can be chosen to give different treatments as described above can withstand. In the case of the example shown, the thickness of the second substrate is 12 with 300 / um chosen.

The first and second single crystal silicon substrates entered 11 and 12 are to be connected at the end to a one-piece structure. Let me begin with an explanation of the method or treatment steps given before these connection steps will.

As shown in Fig. 1B, a main side surface of the first single crystal is provided Substrate 11 with isolation grooves 13 of 40 µm thick in a grid pattern according to a well known photolithography technique and an anisotropic etching technique.

Then the entire main surface is covered with the isolation grooves from an insulating silicon dioxide (SiO 2) layer 14 approximately 1 µm thick by means of thermal oxidation at a temperature of about 1100 0C.

Then a polycrystalline silicon layer 15 with a Thickness of about 55 / µm, which is slightly greater than the depth of the insulation grooves 13, trained to the isolation grooves 13 to be filled. The education such a polycrystalline silicon layer 15 can be grown in a reactionor in the presence of hydrogen gas containing silane trichloride (H2) can be carried out at a temperature of 1100 to 1250 ° C. Then the thus obtained polycrystalline silicon layer 15 by switching to the through the Dashed line d in Fig. 1C indicated level polished by about 10 / .mu.m so to form the flat top major surface. In this context, it should be noted that that the thickness of the remaining polycrystalline silicon layer part 15a is not must be set with particularly high accuracy. So you don't need any high accuracy in controlling this polishing process.

In the above description it was assumed that a polycrystalline Silicon layer is used as a filler material for filling the insulation grooves 13 will. However, it will be readily understood that the invention applies to polycrystalline Silicon is not restricted for this. It is possible to use any other insulating material to use that to withstand heat treatments at a temperature of over 1000 ° C is suitable according to the following description, approximately the same Has a coefficient of thermal expansion like that of the single crystal silicon substrate 11, and contains essentially no diffused impurities that would otherwise have to Fluctuations in the conductivity type and in the resistance of the SubstrsSsll could give cause.

On the other hand, is also on the second single crystal silicon substrate 12 a silicon dioxide layer 16 by the known thermal oxidation or a similar method formed as shown in Fig. 1B. Additionally will a glass layer 17 on the silicon dioxide layer 16 after a conventional chemical reaction deposited in the gas phase, such as Fig. 1C shows. The glass layer 17 provides a bonding layer for the thermal connection of the two substrates 11 and 12 is under pressure and at the same time forms a filling layer for the isolation grooves 13 in cooperation with the polycrystalline silicon layer 15th

As a typical example, the glass layer 17 can be a composite of 6.5 mol% B 2 O 3 and the remainder SiO 2 and formed in a thickness of about 1.5 μm will. A preferred content range of the boron oxide B203 is from 3 to 10 mol%, since the glass layer 17 has essentially the same coefficient of thermal expansion as the semiconductor material should have. If the B203 content is less than 3 mol%, a high treatment temperature of the order of about 1300 is required 0C or more for the subsequent thermal pressure bonding process, which in turn the use of a special electrical which is unfavorable for mass production Oven requires. On the other hand, when the B203 content is higher than 10 mol%, will the softening point of the glass layer is too low for treatments at high temperatures above 1000 ° C, such as an impurity diffusion treatment for formation integrated circuit elements to withstand. In addition, the hygroscopic increases Behavior of the glass layer noticeable, so that washing treatment becomes impractical.

The thickness of the glass layer 17 should preferably be in the range of 0.5 up to 3 #um can be chosen. With a greater thickness, cracks or the like could. mistake in of the glass layer occur at the time of their formation. By contrast, it will be when the thickness is below 0.5 lum, impossible or at least difficult, possible surface roughness to compensate for the substrates to be connected to one another. In this context may be found that the thickness of the glass layer 17 has no influence from that of the single crystal Substrate 11 experiences, provided that the latter has a thickness in the range from 200 to 500 / µm, which is usually chosen in the manufacture of semiconductor substrates will.

The thickness of the silicon oxide layer 16 should preferably be less than 3 / µm and preferably less than 2 / µm. The presence of the silicon dioxide layer 16 has the advantage that the softening point of the glass layer 17 increases somewhat is, so that the bond strength by interacting with the silicon dioxide layer 16 is improved in the thermal pressure bonding process.

The deposition of the glass layer 17 by chemical reaction in the Gas phase can be carried out in the following way: The single-crystalline silicon substrate 12 is placed in a reaction furnace with the silicon dioxide layer 16 exposed. The surface temperature of the substrate 12 is maintained at about 500 ° C. Thereafter one leads silane (sah4) and diborane (B2H6), which by nitrogen (N2) in certain Dilute concentrations exist in the reaction furnace along with a certain Amount of oxygen (02) a. Then two chemical reactions take place in the gas phase in the furnace, as a result of which a glass of the borosilicate glass series on the silicon dioxide layer 16 is deposited on the single crystal silicon substrate 12.

Alternatively, the glass layer 17 can also be on the remaining polycrystalline Silicon layer 15a of the substrate 11 or formed on both substrates 11 and 12 will.

The next step is the two single crystal substrates 11 and 12, as shown in Fig. 1C, placed one on top of the other, the polycrystalline Silicon layer 15a touches the glass layer 17, as shown in FIG. 1D, and at a Temperature of the order of 1200 0C in the presence of an oxygen containing Atmosphere for connecting both substrates 11 and 12 to each other (thermal pressure bonding treatment) pressed against each other. Then the first substrate 11 is a polishing or Xtz treatment to remove material up to one through the dash-dotted line Line β in Fig. 1D indicated level, which line is the isolation grooves 13 cuts through at the bottom parts, as can be seen in FIG. 1D. So is a semiconductor substrate 10 for integrated circuits according to FIG. 1E available, which shows the bonded and polished substrate of FIG. 1D inverted.

As shown in FIG. 1E, the semiconductor integrated circuit substrate is 10 provided with monocrystalline silicon island regions 11a, 11b and 110 which are mutually are insulated by respective associated silicon dioxide layers 14, which are represented by the Etching away the first monocrystalline silicon substrate to the bottom of the isolation grooves 13 were made incoherent. It should also be noted that the island areas 11a, 11b and 11c through support areas of the second monocrystalline silicon substrate 12 via the interposition of the polycrystalline silicon layer 15a, the connecting Glass layer 17 and the silicon dioxide layer 16 are fixed.

It is important to note that each of the island areas 11a to 11c has such a profile that the island a large area the side of the exposed surface and a small area on the side of the support area 12, the distance between the adjacent island areas at the exposed upper main surface is made tight. Such a system and such a configuration of the island areas allow a markedly increased number of circuit components or to form elements in the individual island area, so that an increased integration density is made possible.

Since the two single-crystal silicon substrates 11 and 12 are essentially have the same coefficient of thermal expansion, the substrate with the Silicon dioxide layer 14 or 16 is provided, and the coefficient of thermal expansion the polycrystalline silicon layer 15a and the glass layer 17 having that described above Composition almost the same as that of substrates 11 and 12 results essentially no curvature of the composite structure after the thermal pressure bonding treatment in the step illustrated in Figure 1D. In these circumstances, if part the first monocrystalline silicon substrate 11 is to be removed by polishing, the upper major surface of the second substrate 12 as a flat reference surface for convenience the formation of the individual single-crystal silicon island regions 11a, 11b and 11c serve with the same thickness.

Each of the single crystal silicon island regions 11a to 11c is for therein taking place formation of circuit components by known photolithography and diffusion techniques. Although the. Bonded substrate high temperature treatments subject to the introduction of the circuit components in the island areas becomes, the possibility of penetration is that contained in the bonding layer 17 Boron contamination inevitably into the island areas through the polycrystalline silicon layer 15a and the silicon dioxide layer 14 suppressed. The line type and the resistance of the individual island areas lla, 11b and llc never subjected to undesired changes due to boron contamination, which in turn means that the electrical properties of those in the island areas formed circuit components any adverse influence of boron contamination can remain insensitive to.

Fig. 2 shows an integrated circuit semiconductor substrate 20 which is obtained by removing the polycrystalline silicon layer 15 such that only the polycrystalline silicon layers 15b of the insulation grooves 13 in the case of FIG Fig. 1C can be left in the step shown.

Reference numerals in Fig. 2 that are the same as those in Figs. 1A through 1E denote the same or equivalent parts in these figures.

Although the glass layer 17 is in direct contact with the silicon dioxide layer 14, the boron impurity does not occur in the single crystal silicon island regions 11a to 11c can penetrate through the silicon dioxide layer 14, since the content of Boron oxide B203 is in the range from 3 to 10 mol. The electrical properties of the circuit components formed in these islands are also opposite protected from the influence of boron contamination.

Fig. 3 shows a structure in which the individual isolation grooves are completely filled with a layer of glass. In Figure 3, the same reference numerals denote the same or equivalent parts in FIGS. 1A to 1E.

In the case of the semiconductor integrated substrate structure shown in FIG is the polycrystalline silicon layer 15 shown in Fig. 1C through a glass layer 17a from the borosilicate (B203-SiO2) -glassrethe replaced by a similar process such as the one for depositing the glass layer 17 on the single crystal silicon substrate 12 in the process step shown in Fig. 1C, i.e. by chemical reaction is deposited in the gas phase. The maximum depth of the glass layer 17a to the floors of the islands 11a to 11c opposite the carrier area of the substrate 12 should be in the The order of 3 µm is chosen as in the case of the structure shown in Figs. 1A to 1E will. The glass layer on the carrier substrate area can thus be saved. Of course, it is also possible to have a thin layer of glass on the carrier area as well 12 should be provided for the purpose of improving the connection strength. In other words the glass layer can be provided in any desired manner, so far its thickness is less than 3 µm, since then there is no possibility of occurrence of There are cracks or breaks in the glass layer in this thickness range. You will find that the thickness of less than 3 µm for a glass layer is independent it applies whether the glass layer on one of the two substrates te 11 and 12 or is provided on both. Of course, the B203 content should be in the range from 3 to 10 mole percent.

4 shows a semiconductor substrate structure for integrated circuits, at which the thickness for the single crystal silicon islands is very small in the order of magnitude of 10 / um with a correspondingly flat design of the insulation grooves 13a. Of the The state shown in Fig. 4 corresponds to the method step shown in Fig. 1D, and like reference numerals are used to denote like or equivalent in Fig. 1 shown parts are used.

In the F; the flat isolation grooves is the surface of the polycrystalline Silicon layer 15 after its formation is essentially free of roughness, there the polycrystalline silicon layer in the isolation groove areas 13a by vapor growth faster than the layer is formed on the flat area. It is accordingly possible, the single-crystal silicon substrates 11 and 12 directly to one another with contact of the polycrystalline silicon layer 15 with the glass layer 17 without Requirement of polishing the layer 15 to connect. The glass layer 17 can after Melting under heating for the thermal pressure bonding process easily into all small concave areas that may flow in the polycrystalline silicon layer 15 are formed, creating a good bond of improved strength between the substrates 11 and 12 is secured.

After the thermal pressure bonding process step, the becomes single crystal Silicon substrate up to the level indicated by a dash-dotted line ff removed by polishing or etching to form a plurality of single crystal silicon island areas low thickness.

As can be seen from the above description, in the case of the exemplary embodiments described above with reference to FIGS. 1 to 4, the dielectric Isolation between the monocrystalline semiconductor islands by forming the isolation grooves, the insulating oxide layer and the polycrystalline silicon layer in this Order received.

However, it is also possible to use the dielectric isolation between to form porous silicon in the islands through a selective oxidation process, that belongs to the state of the art and in Formation and Properties of Porous Silicon and its Applications vsn Y. Watanabe et al., J.

Electrochem. Soc. 122, (10) 1351 (1975).

An explanation will now be given of the selective oxidation method porous silicon given with reference to FIG. 5. First, areas 18 are porous Silicon oxide in a main surface of the single crystal silicon substrate 11 formed on parts in which the isolation grooves by the selective oxidation process porous silicon are to be formed. Thereafter, a silicon oxide layer 14 and then a polycrystalline silicon layer 15 on the same main surface of the substrate 11 is formed. On the other hand, it becomes a single crystal silicon substrate 12 corresponding to the method steps described above in connection with FIGS. 1A to 1C prepared. The substrates 11 and 12 obtained in this way are then placed one on top of the other, the polycrystalline silicon layer 15 touching the glass layer 17, as shown in FIG. FIG. 5 shows, and the thermal pressure bonding treatment for mutually bonding FIGS both substrates 11 and 12 are subjected.

Thereafter, the first single crystal silicon substrate 11 is up to Bottom level of the porous silicon oxide areas 18, which is indicated by a dash-dotted line & indicated is removed by a polishing or xetching process, resulting in formation several, among each other through the respective silicon oxide layer 14 and the porous Silicon oxide areas 18 isolated single crystal silicon island areas leads.

In the case of the substrate structure shown in FIG. 5, the polycrystalline Silicon layer 15, if desired, such as in the case of, for example The illustrated embodiment according to FIG. 3 is omitted.

In all of the exemplary embodiments described above, the Silicon oxide layer 16 on the trigger substrate 12 only with loss of the slope the softening point of the glass layer due to the action of this silicon oxide layer can be saved.

Claims (5)

Patent aA'S claims X Method for manufacturing a semiconductor substrate for integrated semiconductor circuits, g e k e n n z e i c h -n e t d u r c h die the following process steps: a) Production of a first and a second monocrystalline Semiconductor plate (11, 12), b) formation of insulating areas (13) in a specific Patterns on a main surface of the first single crystal semiconductor plate (11), c) Forming a dielectric insulating layer (14) on the one main surface the first monocrystalline semiconductor plate (11) with the insulating regions, d) application of a binding layer (17) on the dielectric insulating layer (14) on the first semiconductor plate (11) and / or on a main surface of the second single crystal semiconductor plate (12), e) firmly connecting the first and second monocrystalline plate (11, 12) with one another by means of the binding layer (17), and f) removing the first monocrystalline semiconductor plate (11) from the others Main surface of up to a corresponding to the bottom parts of the insulating areas Level (ß "r, 2. The method according to claim 1, characterized in that the binding layer (17) is formed from a glass of the borosilicate glass series containing 3 to 10 mol% boron oxide contains. 3. The method according to claim 1, characterized in that a polycrystalline Silicon layer (5) between the dielectric insulating layer (14) and the bonding layer (17) is formed on the first single crystal semiconductor plate (11). 4. The method according to claim 2, characterized in that the binding layer (17) has a thickness in the range of 0.5 to 3 µm. 5. The method according to claim 3, characterized in that the surface the polycrystalline silicon layer (15) before the connection step the first and the second monocrystalline semiconductor plate (11, 12) with one another is leveled.