DE2265257A1 - PROCESS FOR PRODUCING ISLAND-LIKE SINGLE CRYSTAL AREAS FOR INTEGRATED SEMICONDUCTOR CIRCUITS - Google Patents

Description

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FLOSS · <AN NSTRASSH \ t PATENTANWALT TELEFON iCfcli- S «3r; - "3 -et 2c. C

226525 7 ^{TEiEX0S / sias} »

• 72/8749

Fujitsu Limited
Kawasaki-shi, Japan

Method for producing island-like single crystal regions for integrated semiconductor circuits

The invention relates to a method for manufacturing semiconductor devices, in particular diffused planar halves ladder structures in which the three areas of emitter, base and collector lie in the same plane of the semiconductor arrangement

Semiconductor arrangements, especially those with a large number of integrated circuits on a single semiconductor die Contain electrical wiring to provide high density circuitry · Generally unfolded the multilayer wiring is one formed on a silicon substrate Insulating layer made of silicon dioxide · The insulating layer has one or more holes in which the wiring of the outside adjacent layer is formed · As a metal layer for such wiring is usually a layer of aluminum, or whether layers are made of a union of chrome-copper »

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Chromium in terms of adhesion to silicon dioxide and the electrical conductivity used. Each of the metal layers and the silicon dioxide insulating layers generally have a thickness sound approximately 1 ttDcrea on «

However, there are serious problems in semiconductor devices with such multilayer twisting. When the electrically conductive metal is deposited on the semiconductor device by vacuum damping, the obtained metal layer is thinner on the upper surface of the holes formed in the silicon dioxide insulating layer than on the other locations. The cause Beer for lies in the height difference of approximately one micrometre between the bottom of the hole and the outer surface of the insulating layer. The metal layer therefore tends to peel off at the upper edge of the hole wall. If forner on conductor strips with a bead of approximately 1; u '''a silicon dioxide insulating layer with a thickness of approximately 1 μ is formed by chemical deposition and then further conductor strips are formed on the silicon dioxide insulating layer in one direction, which the embedded conductor strips cut, then there is the risk that the two line strips short-circuited at the point of intersection earth. This is because the intermediate silicon dioxide insulating layer at the edge of the embedded conductor strips is thinner than elsewhere. In summary, it can be said that the multilayer wiring contained in known semiconductor arrangements is not sufficiently reliable.

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In the case of a planar transistor, the KUIrwrodsmnotall is not the emitter connected by a window formed in the oxide layerIn cases in which the bitter transition is flat 44%, there is, however, the risk of that it is destroyed by the sintering of the metal electrode, Among other things, it has already been proposed to alleviate this deficiency selective epitaxial growth in the window to build up a layer of semiconductor material and thus the emitter before the migration to protect the electrode metals. However, it is very difficult to stably perform the selective epitaxial growth because the The boundary conditions for the structure of the semiconductor material are very strict are·

It is also a method of manufacturing integrated circuits has been developed in which an oxide film is formed for dielectric isolation, i.e., for isolating islands of the semiconductor · The oxide film is usually made by selective oxidation a Siuiziumsubstrats using a masking Kittels, such as silicon nitride, formed · In this way, a flat surface of the substrate can be obtained. The procedure will referred to as an "isoplanar" process. In general, the isoplanar process before oxidation at least the surface part of the silicon substrate8 to be oxidized so that a la substantially flat surface is obtained. However, Bs is very difficult to determine the amount of silicon to be etched and oxidize the entire depth to produce a completely flat surface precisely control the epitaxial layer "

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The invention is based on the object of a manufacturing method indicate with the «β is possible a semiconductor device with a more flattened conductor surface over which the metal wiring runs to generate than is possible with the known methods. It should also be possible to use the method according to the invention to produce a semiconductor device, the layers of metal wiring contains, which are essentially in the same plane as the semiconductor surfaces on which they are located Semiconductor devices that can be manufactured according to the invention should contain metal wiring layers that ensure a high degree of reliability of the arrangement. They manufacture of Flanar semiconductor devices should be possible in a simple and easy way

The method according to the invention is characterized by the following method steps!

a) it is on a surface of a semiconductor substrate a Insulating layer formed with a closed cough,

b) a cover layer is formed on the entire surface of the semiconductor substrate, of which at least the part deposited on the insulating layer is electrically conductive,

c) the semiconductor substrate treated in this way is in a bath of a At «solution immersed in which an electrolytic etching of the» Art causes the part of the cover layer of conductive material deposited on the insulating layer to be formed as an anode, whereby this part is removed, and the through the insulating layer, part of the cover layer, remains

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The term "insulating layer" is intended to mean a layer of a Material is understood to be »a specific resistance a hundred times higher than that deposited on the insulating layer has conductive top layer

A preferred embodiment of the method according to the invention is characterized by the following method steps t ») a circuit element is formed in a region on a surface of a semiconductor substrate, and the entire surface of the semiconductor substrate is covered with a first insulating layer,

b) a recess is formed in the first insulating layer, to expose a rope in the area of the circuit element,

e) a first wiring layer is formed on the first insulating layer, which is electrically connected to the circuit element is bound,

d) the entire surface of the semiconductor substrate treated in this way is covered with a second insulating layer,

t) a through hole is formed in the second insulating layer in order to accommodate part of the first wiring layer for the To expose the connection between the wiring layers,

f) ta becomes on the entire surface of the semiconductor substrate • Formed in a layer coating of metal, of which the part deposited in the through hole is in a lower level than the part b deposited on the second insulating layer «-

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finds

g) the 00 treated semiconductor substrate is in a bath of a Etching solution is immersed in which electrolytic etching is effected in such a way that the part of the metal coating deposited on the second insulating layer is formed as an anode, whereby this part is removed, and the im Through hole deposited part of the layer coating remains and further

a *) the entire surface of the semiconductor structure with a third Insulating layer is covered,

b *) a cutout is formed in the third insulating layer, to expose at least one toilet of the metal buried in the through hole,

o ') on the entire surface of the semiconductor device Layer coating is formed from wiring metal from which the part deposited on the cutout is at a lower level than the part deposited on the third insulating layer, and

d ') the semiconductor structure treated in this way is immersed in a bath of an etching solution in which an electrolytic etching is carried out it is effected that the part of the layer coating of wiring metal deposited on the third insulating layer al · anode is formed, whereby this part is removed, and the part of the layer coating deposited at the cutout as ■ Far · wiring layer remains. __

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Another advantageous embodiment of the invention The method for manufacturing semiconductor devices is characterized by the following method steps

a) It becomes a semiconductor substrate with a on one surface the active area of a circuit element formed by semiconductor substrates and with an applied insulating layer * put »at least one window to expose a part of the active area «

b) a semiconductor layer is formed on the semiconductor substrate, of which the part deposited on the window is in a lower level than that deposited on the insulating layer Part is located

c) the semiconductor substrate treated in this way is in a bath of a Xtzlösung immersed, in which an electrolytic etching is effected in such a way that the deposited on the insulating layer Part of the semiconductor layer is formed as the anode, thereby removing this part, and the part deposited on the window of the layer coating remains and then

Wiring

d) an exercise layer is formed on the insulating layer, which with

the semiconductor layer is electrically connected *

A further embodiment of the method according to the invention for Manufacturing of semiconductor devices is by the following Process steps marked!

a) it becomes a semiconductor substrate with one on one surface of the semiconductor substrate buried layer and with a Isolation layer of a closed pattern in an isolation

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area, the insulating layer has a closed pattern and surrounds the buried layer »

b) it is made by epitaxial growth on the entire surface of the semiconductor substrate is formed by a semiconductor layer the calibrate the part stored on the semiconductor substrate, the is enclosed by the insulating layer, in a lower level than the part of the semiconductor layer deposited on the insulating layer, and the first-mentioned part is nonocrystalline and the last-mentioned part is polycrystalline is,

c) the semiconductor substrate treated in this way is in a bath of a Etching solution immersed, in which an electrolyte puddle etching is effected in such a way that the deposited on the insulating layer Part of the semiconductor layer is formed as an anode, whereby this part is removed, and the one through the insulating layer enclosed part of the semiconductor layer forms an island and

d) a circuit element is formed on the island

In the case of the embodiment mentioned above, impurities can diffuse into the semiconductor bar before the electrolytic etching will·

In the latter case. the insulating layer is preferably formed by the following process steps! t) a silicon oxide layer is formed by epitaxial growth on the entire surface of the semiconductor substrate,

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the is essentially the same bead as the semiconductor layer to be formed owns,

b) on the whole. Surface of the silicon oxide layer becomes a Silicon nitride layer formed »

e) the silicon nitride layer is provided with a cough, that the silicon nitride remains on the isolated area, and then becomes

d) the silicon add layer using the silicon nitride layer ala mask selectively removed

The invention is explained in more detail by means of exemplary embodiments with the aid of 15 figures

1 to 6 cross-sectional views to explain an embodiment of a method according to the invention in which a wiring metal is buried in an insulating layer,

Fig. 7 and. 8 cross-sectional views illustrating a further embodiment of the method according to the invention, in which a Semiconductor material is formed after a base diffusion in a window for an Eaitterdiffusion and

fig · 9 Ms 15 cross-sectional views of a further embodiment a method according to the invention for producing an integrated semiconductor circuit.

example 1 Examples 1 and 2 illustrate intermediate results of a

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In accordance with the invention, in which a sweeping layer wiring is introduced into an insulating layer in such a way that a flat upper * surface arises. Example 1 relates to the first half step, in which the metal material in a second Through hole formed by insulating layer is buried over the di multilayer wiring is running

According to FIG. 1, a circuit element, such as e.g. B. a transistor formed. A first insulating layer 2 is formed on the entire surface of the semiconductor substrate 1. A recess is formed in this first insulating layer 2 in order to expose part of the region. The first insulating layer consists, for example, of silicon dioxide. A first aluminum wiring layer 3 is then formed both on the insulating layer 2 and on the semiconductor substrate 1 not covered by the first insulating layer. The first aluminum wiring layer is thus electrically connected to the circuit element. It is covered with a wide insulating layer 4. This is designed, for example, as a phosphor • silicate glass layer with a thickness of one / x .

Gemäfi Pig. 2 let aluminum deposited on the entire surface by vacuum evaporation to form an aluminum top layer 6

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a thickness of 1 to 1.5 / i. The part of the aluminum cover layer 6 deposited on the through hole 5 lies in a lower level than that deposited on the second insulating layer 4 © part.

The semiconductor substrate treated in this way is immersed in a bath of an aqueous phosphoric acid solution which is kept at a temperature of approximately 30 ^° C. In this way, electrolytic etching is carried out in the manner described below. The aluminum cover layer 6 deposited on the second insulating layer 4 is designed as an anode. A platinum plate arranged in the solution faces the substrate at a distance which is kept within the range of 10 to 100 approx. The platinum plate is designed as a cathode and the electrolytic etching of the aluminum of the cover layer 6 is carried out with a direct current at a constant voltage of 1.2 V.

In this example, the aluminum of the cover layer 6 with a Etched speed from 2,500 to 3,000 A / min. In comparison for this purpose, in a chemical etching process, the etching takes place only at a speed of approximately 150 A / min.

As the electrolytic etching proceeds, the part of the aluminum layer deposited in the through hole 5 becomes the Remaining part deposited on the second insulating layer 4

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as shown in FIG. fiaca this separation becomes that part of the aluminum layer located in the through-hole β no longer an electrolyte! see etching, but only one more subject to chemical etching "

You electrolytically "etch the part of the Αΐυτηΐnlmadeckschicht 6, which is deposited on the second insulating layer 4 ”is continued, however. It proceeds so rapidly that the part of the aluminum cover layer 6 deposited on the second insulating layer 4 has completely disappeared from the surface when the essential part of the aluminum is still in the through hole 5

The electrolytic etching is continued until the current suddenly drops, which indicates the completion of the removal of the aluminum cover layer 6 from the insulating layer.

The aluminum buried in this way in the through hole 5 has has a substantially flat surface to which a second layer of aluminum wiring is to be applied. The aluminum in the Through hole 5 allows the second wiring layer is firmly and effectively connected to the first wiring layer 3. The production of the second wiring layer is carried out in the following example explained

In the present example aluminum is used · It can however, other metals can also be buried in the through hole with satisfactory results.

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Example 2

This example represents the second step in the process the first half-step, explained in example 1, follows the second half-step comprises the spreading of a multilayer wiring layer, wherein a metal for wiring is buried in a third insulating layer so that the surface of the submerged metal in the. essentially in the same plane as that of the third insulating layer

After the aluminum layer 6 has been buried in the through hole 5 according to FIG. 4, the entire surface is covered with a third insulating layer 7 by chemical vapor deposition. This layer consists of phosphosilicate glass and has a thickness of 2 / x . In the third insulating layer 7, as shown in Pig 5, a cutout 8 is formed with a sexton, which corresponds to that of the second wiring layer to be formed. Thus, at least one rope of the metal buried in the through hole 5 is exposed.

h is deposited by vacuum evaporation on the whole surface of aluminum, not shown, to one in ä ^ he FIG · to form Aluminiundeckschicht having a thickness of 2.0 to 2.5 / 1 · The deposited at the neck 8 of the covering layer of aluminum is located in a lower level than that deposited on the third insulating layer 7 (Deil · It is then applied in the same way · «

609886/0411 bad ORIGINAL

276 525 7

See example 1 with reference to FIGS. 1 to 3, an electrolyte! see etching of the aluminum cover layer carried out. At the As the etching process advances, the part of the aluminum deposited in the cutout 8 is separated from the remaining part deposited on the third insulating layer 7. After the separation, only the part of the aluminum deposited on the third insulating layer 7 is quickly etched away and finally completely removed In the cutout 8 remaining part of the aluminum thus forms the wide aluminum wiring layer 9 · whose surface, as in fig 6, lies essentially in the same plane as that of the third insulating layer 7

fall making a third, a fourth or even more Successive wiring layers is required, can the procedures described are repeated. Hit other words the following steps can be repeated. First, the semiconductor substrate is covered with an insulating layer, then becomes a through hole at the point of the insulating layer at which a connection between wiring layers is to be formed The insulating layer is e.g. designed as a phosphosilicate glass layer. Second is on the entire surface Aluminum is deposited and then by an electrolytic etching process, the aluminum is etched away except for the part that is deposited in the through hole. Thirdly, an insulating layer, e.g. a phosphosilicate glass layer, is applied to the surface again. applied and then "in detail with a sexton, which the

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corresponds to the following wiring layer, formed · close « lent aluminum is buried in the cutout in the same way as in the second process step

Example 3

This example describes a further embodiment of the invention The process of a basic diffusion is carried out in the window (s) formed in an oxidized surface layer epitaxial growth semiconductor material for emitter diffusion constructed so that a flat surface is created for contact with a wiring metal

According to fig. 7, a base 11 is formed in a silicon substrate 10 by a customary selective diffusion process.A window 13 for the Eaitter diffusion is then made in the insulating layer 12 - an oxidized surface layer - at the point where the emitter is to be diffused into the base 11 . A semiconductor layer, such as a polycrystalline silicon layer 14 doped with a large amount of phosphorus, is then formed over the entire surface deposited part. This formation of the polycrystalline silicon layer 14 is preferably effected by decomposition of Konosilan (SiH ^) and phosphine (PH,) in an oven at a temperature of 600 ⁰ C bie TOO. That by such thermal decomposition

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generated gaseous components condense on the surface of the silicon substrate in the furnace and build up the polycrystalline silicon layer. This process step can be a big one Amount of phosphorus above the solubility limit in that polycrystalline silicon are doped

· As a modification of this method kind ride can be used instead of the polycrystalline silicon, a silicon single crystal in the window 13 formed This can be achieved "by this process step by heating the furnace to a temperature of 1100 ⁰ C to 1» 200 ° C on the oxidized layer 12 made up of polycrystalline silicon. ^ "'' '-'-""■ ^: ·

The silicon substrate treated in this way is then immersed in a bath of an etching solution in which electrolytic etching is effected in such a way that part of the polycrystalline silicon layer 12 deposited on the insulating layer 12 is formed as an anode. The etching solution is produced, for example, by mixing eight percent by weight of an aqueous phosphorous acid with a concentration of 85% or more with two percent by weight of an aqueous hydrofluoric acid with a concentration of 7% or more and with 90 percent by weight of water. On the other hand, the etching solution can be prepared by mixing 100 parts by weight of 99 # aqueous acetic acid with 10 parts by weight of 62% aqueous nitric acid and one part by weight of 50% aqueous hydrofluoric acid.

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(Temperature of the bath vird preferably maintained at 35 ⁰ C.

The polycrystalline silicon 1A deposited on the insulating layer 12 is easily carried along by the electrolytic process at a speed of 1,000 to 2,000 4 / min · Beim As the electrolytic process progresses, the polycrystalline silicon remaining in the window 13 (or, in the modified process step, the silicon single crystal) becomes only one little or no etching after it is separated from the polycrystalline silicon deposited on the insulating layer 12. This is how the leveling is effected · This procedure is the method described for Example 1 with reference to Pig · 1 to 3 similar.

The silicon substrate treated in this way is then heated, whereby the Phosphorus is diffused into the polycrystalline silicon or silicon single crystal remaining in the window 13 in the silicon substrate in order to form an emitter (cf. FIG. 8) on the flattened surface a metal 15 for wiring deposited.

In this planar semiconductor device, it is polycrystalline ßili ζ ium or the single crystal la window 13 between the wiring metal 13 and the emitter junction as an intermediate line that connects the wiring metal with the emitter «The wiring metal 13 thus reaches the emitter.

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Transition not even if ee diffuses into the intermediate conductor *

The explained planar semiconductor structure is particularly advantageous « baft in semiconductor devices »those like high frequency transistor gates have flat or narrow transitions «

Example 4

This example represents the process step of flattening or flattening. Flattening a semiconductor surface of an integrated semiconductor circuit. The method step relates to an improved "isoplanar process" in which no selective oxidation is applied.

According to FIG. 9, an η-type buried layer 17 is formed on a surface of a p-type semiconductor substrate 16 by diffusion of antimony in high concentration.

For example, referring to Fig. 10, a thermal oxidation technique oaek an insulating layer 18, e.g. Silicon dioxide layer, -ce formed. The thickness of the insulation layer is between 2 and 3, Ji. It is it is apparent that no selective oxidation technique is used. E.g. by heating the silicon semiconductor substrate in an oven at a temperature of 1,250 ° C for a «time

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a silicon dioxide layer with a thickness of 2.2 u can be formed in a period of 310 minutes while blowing in steam of 10O ^{0 O}

As shown in Fig. 11, the insulating layer is subjected to a photo-etching process subjected to the fact that only the part of the silicon dioxide located in the isolation area remains The isolation area has a closed pattern

According to FIg * 12, a semiconductor 19 (e.g. an n-conducting Silicon layer formed with a thickness of 2.5 fcl »3» 5 / Ü · Zur Formation of this silicon layer can be applied the usual technique of epitaxial growth using monosilane Single crystals 20 and polycrystalline silicon are formed on the silicon substrate or on the insulating layer (silicon dioxide) 18 under the usual conditions of epitaxial growth educated·

According to Pig · 13, an island of the single crystal 20 becomes one of the many other islands laid on the surface of the silicon substrate separated. This separation is effected by electrolytic etching according to this invention, the polycrystalline silicon 21 is etched away in the same way as described for Example 3 · Aue Yig · 13 it can be seen that the insulation of the single crystal 20 is provided by the silicon dioxide layer 18 of a ge closed patterns and the pn junction is guaranteed previously between the single crystal 20 and the semiconductor substrate

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has been formed.

14, the bo becomes a treated silicon semiconductor substrate then subjected to thermal oxidation in order to each silicon single crystal layer 20 to a silicon dioxide layer 22 form. This silicon dioxide layer 22 has essentially the the same surface as the silicon dioxide layer 18. Then, on each isolated single crystal island 20, a symbol shown in FIG. formed circuit element shown, the above The mentioned silicon dioxide layer 22 is used as a mask against diffusion.

In this example, the formation of that shown in FIG The silicon dioxide layer 18 also corresponds to a closed pattern by itching using a silicon nitride mask 23 7ig x 15 can be effected. According to this method, the subsequent separation of the silicon encroachment metal layer 20 can be carried out because of the silicon nitride layer 23 (see FIG. 15) deposited on the tip of the silicon dioxide layer 18 easily by electrolytic iteen to be executed

In this example, the electrolytic process, as explained in connection with FIG high concentration in the silicon semiconductor layer 19 are diffused. This pretreatment has the advantage that the on of the insulating layer (silicon dioxide layer) 18 is deposited

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2f [the silicon semiconductor layer 19t & · · of the silicon-containing polykristallinea! Part is etched far faster than the _a uf the SiIiziumhalbleitersubstrat 16 deposited rope 20, the silicon single crystals contains · This is a easy. Separation of the single crystal layers 20 are obtained because the rate of diffusion of the phosphorus into the polycrystalline silicon 21 is two or three times higher than that of the diffusion into the single crystals 20. The pretreatment is advantageous when etching a silicon layer, in particular with high specific resistance, i.e. applied several onm-cm or more *

^ yin sayings
15 figures

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Claims (1)

. ι Ancestors of the production of an integrated semiconductor circuit, in which a Holbloitorcubatrata on a Cborfläche a buried layer and in an isolation area ^ an insulating layer is formed, further by epitaxiale Growth on the roped surface of the semiconductor substrate an elbloiter layer is formed and the semiconductors »· The layer is treated in such a way that it remains in the fora of islands bounded by the insulating layer and finally on one of the islands a circuit oelonont formed vird, daduroh konnaeichnot, that the insulating layer is designed as a closed tfustor iat and the epitoxialo Vachstrun vird in such a way that ORIGINAL 60988ß / 0A1 1 calibrate the deposited on the semiconductor substrate which is delimited by the insulating layer, in a lower level oils that are deposited on the insulating layer Rope of the semiconductor layer is located, and the former Part monocrystalline and the latter part polycrystalline is formed »furthermore, the treated semiconductor substrate is immersed in a bath of an Xtz solution in which a electrolytic etching is performed in such a way that the on part of the semiconductor layer deposited on the insulating layer is connected as an anode »whereby this part is removed» and the part of the semi-leather layer delimited by the insulating layer remains in the form of islands. 2, Jo * Method according to Claim ^ »characterized in that impurities are diffused into the semiconductor layer before electrolytic It sen. Jt * ancestors according to claim y »thereby g ο k β η E» üeichne t that for the formation of the insulating layer through epitaxial growth on the entire surface of the half " ί conductor substrate a silicon oxide layer is formed, which is in j essentially the same thickness as the semiconductor to be formed « layer, a silicon nitride layer is formed on the entire surface of the silicon oxide layer, which ßilisluanitrideehicht is provided with a pattern in such a way " - 6- BATH 609886/041 1 that the silicon nitride remains in the insulated area, and then the silicon dioxide layer before use and the silicon nitride chidit tlazko is selectively removed BATH ORIGINAL 609886 / OA11