DE1564106A1 - Method for producing a field effect transistor element - Google Patents
Method for producing a field effect transistor elementInfo
- Publication number
- DE1564106A1 DE1564106A1 DE19661564106 DE1564106A DE1564106A1 DE 1564106 A1 DE1564106 A1 DE 1564106A1 DE 19661564106 DE19661564106 DE 19661564106 DE 1564106 A DE1564106 A DE 1564106A DE 1564106 A1 DE1564106 A1 DE 1564106A1
- Authority
- DE
- Germany
- Prior art keywords
- conductivity type
- zone
- zones
- semiconductor layer
- contaminant material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 230000005669 field effect Effects 0.000 title description 5
- 239000004065 semiconductor Substances 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 10
- 239000000356 contaminant Substances 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 230000000873 masking effect Effects 0.000 claims description 5
- 229910052787 antimony Inorganic materials 0.000 claims description 3
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 230000000694 effects Effects 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims 2
- 229910052785 arsenic Inorganic materials 0.000 claims 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims 1
- 238000009792 diffusion process Methods 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 206010035148 Plague Diseases 0.000 description 1
- 241000607479 Yersinia pestis Species 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000010348 incorporation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/761—PN junctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Bipolar Transistors (AREA)
- Bipolar Integrated Circuits (AREA)
- Thyristors (AREA)
- Electrodes Of Semiconductors (AREA)
- Element Separation (AREA)
Description
Dipl.-Ing. Heinz Ciaessen 1564106 P.J.A. McKeown-7 PatentanwaltDipl.-Ing. Heinz Ciaessen 1564106 PJA McKeown-7 Patent Attorney
^7, Stuttgart-1 22. Dez. 1965^ 7, Stuttgart-1 December 22, 1965
ilotebühlstraase 70 . Pat. Go./S.ilotebühlstraase 70. Pat. Go./S.
ISE/Reg. 3320 - Pl 285ISE / Reg. 3320 - Pl 285
INTERNATIONAL STAlTOARD ELECTRIC CORPORATION, NEV/ YORKINTERNATIONAL STALTOARD ELECTRIC CORPORATION, NEV / YORK
Verfahren zum Herstellen eines FeldeffekttransistorelementesMethod for producing a field effect transistor element
Die Priorität der Anmeldung in Grossbritannien vom 29.1.65 Nr. 4030/65 wird beansprucht.The priority of filing in Great Britain from 01/29/65 No. 4030/65 is claimed.
Durch die Erfindung soll ein Verfahren zum Herstellen eines zur Eingliederung in eine monolithische Festkörperschaltung geeigneten Feldeffekttränsistorelementes angegeben werden.The invention is intended to provide a method for producing a device for incorporation into a monolithic solid-state circuit suitable field effect transistors are specified.
Die vorliegende Erfindung betrifft somit ein Verfahren zum Herstellen eines Feldeffekttransistorelementes, insbesondere für eine monolithische Festkörperschaltung.The present invention thus relates to a method for Manufacture of a field effect transistor element, in particular for a monolithic solid-state circuit.
Das Verfahren besteht erfindungsgemäss darin, dass ein Verunreinigungsmaterial des einen Leitfähigkeitstyps auf einen Bereich oder Bereichen der Oberfläche einer Halbleiterplatte des anderen Leitfähigkeitstyps aufgebracht wird, dass auf diese Oberfläche epitaktisch eine Halbleiterschicht des anderen Leitfähigkeitstyps aufgewachsen wird, dass danach örtlich • weiteres Verunreinigungsmaterial des einen Leitfähigkeitstyps auf die freie Oberfläche der epitaktisch gewachsenen Halblei-According to the invention, the method consists in that a contaminant material of one conductivity type is applied to a Area or areas of the surface of a semiconductor wafer of the other conductivity type is applied so that a semiconductor layer of the other is epitaxially applied to this surface Conductivity type is grown that then locally • further contaminating material of one conductivity type onto the free surface of the epitaxially grown semi-
909883/0879909883/0879
ISE/Reg. 3320 - Pl 285 · - 2 - . P.J.A. McKeown-7ISE / Reg. 3320 - Pl 285 - 2 -. P.J.A. McKeown-7
terschicht derartig aufgebracht und das Verunreinigungsmaterial innerhalb der Halbleiterplatte und der Halbleiterachicht unter Bildung einer Zone oder Zonen des anderen Leitfähigkeitstyps innerhalb der epitalctisch gewachsenen Halbleiterschicht diffundiert wird, so dass jede einzelne Zone des anderen Iieitfähigkeitstyps vollständig von einer Zone des einen Leitfähigkeit3typa umgeben ist, dass dann innerhalb der Zone oder Zonen des anderen Leitfühigkeitotyps weiteres Verunreinigungsmaterial des einen Leitfähigkeitstyps als G-itterzone oder -zonen eindiffundiert wird, und dass schliesslich als Quell- und Senk-Elektroden ohmsehe Kontakte an der Zone oder Zonen vom anderen Leitfähigkeitstyp angebracht werden.terschicht so applied and the contaminant material within the semiconductor plate and the semiconductor layer with the formation of a zone or zones of the other conductivity type within the epitalctically grown semiconductor layer is diffused, so that each individual zone of the other conductivity type completely from a zone of one conductivity type is surrounded, that then within the zone or zones of the other conductivity type further contaminant material of one conductivity type as a grid zone or zones is diffused in, and that finally as a source and sink electrodes ohmic contacts on the zone or zones of the other conductivity type can be attached.
Eine Ausführungsform der Erfindung soll im folgenden anhand der Zeichnung beschrieben werden, in derAn embodiment of the invention is described below with reference to of the drawing are described in the
die Pig, 1 die Arbeitsgänge des Verfahrens nach der Erfindung bei der Herstellung eines Feldeffekttransistors erläutert undDie Pig, 1 the operations of the method according to the invention in the production of a field effect transistor explained and
die Pig. 2 die Anordnung eines nach dem unten beschriebenen Verfahren der Erfindung hergestellten Peldeffekttransistorelementes zeigt.the pig. 2 shows the arrangement of a pelde effect transistor element produced by the method of the invention described below shows.
Die Oberfläche einer p-leitenden Siliciumplatte mit einem spezifischen Widerstand von 30 bis 50SL cm wird in Üblicher Weise hergestellt und oxydiert. In das Oxyd werden unter Anwendung photolithographischer Verfahrensmassnahmen Penster geätzt und danach durch diese Penster Antimon in das Silicium diffundiert. Anschliessend wird die Oxydschicht entfernt. In der Pig. 1A i3t im Querschnitt ein Teil einer eine n-leitende diffundierte Zone 2 enthaltender Teil der Platte 1 dargestellt.The surface of a p-conducting silicon plate with a specific resistance of 30 to 50 SL cm is produced and oxidized in the usual way. Pensters are etched into the oxide using photolithographic process measures and then antimony is diffused through this penster into the silicon. The oxide layer is then removed. In the pig. 1A i3t shows a part of a part of the plate 1 containing an n-conducting diffused zone 2 in cross section.
Danach wird gemass Pig. 1B eine p-leitende äiliciumschicht 3Then according to Pig. 1B a p-type silicon layer 3
909883/0 8 79 °-R!G!NAL INSPECTED909883/0 8 79 ° - R! G! NAL INSPECTED
ISE/Reg. 3320 - Fl 285 -5- P.J.1? McTeöW-7ISE / Reg. 3320 - Fl 285 -5- P.J.1? McTeöW-7
mit einem spezifischen Widerstand von ca. 1j~Lcm auf der Oberfläche der Platte aufgewachsen. Ferner werden in dieser Schicht durch Diffusion von Phosphor unter Anwendung der Oxydmaskierung und der Photolithographie η-leitende Zonen 4 gebildet (Pig. 10). Die Diffusionen werden solange fortgesetzt, bis· die Zonen 4 mit den Zonen 2 unter Bildung getrennter und vollständig von n-leltendem Silicium umgebenen p-leitender Zonen 5 sich verbinden (Pig. 1D).with a specific resistance of approx. 1j ~ Lcm on the Surface of the plate grown. Furthermore, in this Layer by diffusion of phosphorus using oxide masking and photolithography η-conductive zones 4 formed (Pig. 10). The diffusions are continued until the zones 4 with the zones 2 with the formation of separate p-conducting silicon completely surrounded by n-conducting silicon Zones 5 connect (Pig. 1D).
Zum Herstellen einer Gitterelektrode 6 in den Zonen 5 (Pig* 1E) wird eine weitere dotierende Diffusion und zum Herstellen Ohmscher Quell- und Senk-Elektroden 7 bzw. 8 eine p-dotieren-•de Diffusion (Flg. 1P) durchgeführt.To produce a grid electrode 6 in zones 5 (Pig * 1E) is another doping diffusion and to produce Ohmic source and sink electrodes 7 and 8, respectively, a p-doping • de Diffusion (Fig. 1P) carried out.
Die Pig. 2 zeigt eine Teilschnittansicht des Elementes. Es ist erkennbar, dass die Zone der Gitterdiffusion 6 sich mit der Zone der einzelnen Diffusionen 2 und 4 vereinigt. Quell-, Gitter- und Senk-Kontakte sind bei 9, 10 bzw. 11 dargestellt. Die Gitterdiffusion 6 könnte auch so durchgeführt werden, dass sie entweder die Quell- oder die Senk-Elektrode umgibt. In diesem Falle braucht sie nicht mit der Zone der einzelnen Diffusionen .2 und 4 zusammenzuhängen. Besondere Kontakte an 6 sowie an 2 und 4 würden dann voneinander unabhängige Gitter-Elektroden ergeben. ' The Pig. Figure 2 shows a partial sectional view of the element. It it can be seen that the zone of the grid diffusion 6 with the zone of the individual diffusions 2 and 4 combined. Source, Grid and countersunk contacts are shown at 9, 10 and 11, respectively. The grid diffusion 6 could also be carried out in such a way that it surrounds either the source or the sink electrode. In this Case it need not be connected with the zone of the individual diffusions .2 and 4. Special contacts at 6 as well at 2 and 4 would then result in independent grid electrodes. '
PUr die anfängliche η-dotierende Diffusion wurde Antimon verwendet, weil es keine besonderen Probleme des Gastransportes während des epitaktischen Aufwachsprozessee verursacht. Es könnten jedoch andere η-dotierende Diffusionssubstanzen bei vaTni geeigneter Umgebungsbedingungen verwendet werden. Ebenso gut könnte ein n-channel Komplement dieses Elementes hergestellt werden. Es könnten andere Halbleiter verwendet werden, obwohl im allgemeinen die Oxydation ihrer Oberflächen keine befriedigende Maskierung ergeben würde. In solchen FällenAntimony was used for the initial η-doping diffusion because it does not cause any particular problems with gas transport during the epitaxial growth process. However, other η-doping diffusion substances could be used with suitable ambient conditions. An n-channel complement of this element could just as well be produced. Other semiconductors could be used, although in general the oxidation of their surfaces would not give a satisfactory masking. In such cases
909883/08 7 9 O^IMAt ,MSPECTED909883/08 7 9 O ^ IMAt, MSPECTED
. .- r .■"■■■ - 4 -. .- r . ■ "■■■ - 4 -
ISE/Reg. 3320 - Fl 285 - 4 ~ISE / Reg. 3320 - Fl 285 - 4 ~
vmrde die Verwendung einer aufgebrachten Schicht eitLeö ge- ■ eigneten Materiales, beispielsweise Siliciunmonoxyty empfehlenswert sein.The use of an applied layer is void Suitable material, for example Siliciunmonoxyty recommended be.
Ein Vorteil der beschriebenen Konstruktionsform beäteht darin» dass das Element gegen das Substrat isoliert ist; Damit ist es besonders vorteilhaft zur Eingliederung iü iiüe monolithische Pestkörperschaltung.One advantage of the described form of construction is that the element is insulated from the substrate; In order to it is particularly advantageous for incorporating iü iiüe monolithic Plague body circuit.
Die beschriebene Ausführungsform soll seibstverötäMliöh nicht als Einschränkung aufgefasst werden.The embodiment described is intended to be self-sufficient should not be taken as a limitation.
ORIGINAL INSPECTED 90988 37 087 9ORIGINAL INSPECTED 90 988 37 087 9
Claims (1)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB4522863A GB1026489A (en) | 1963-11-15 | 1963-11-15 | Semiconductor device fabrication |
| GB403065A GB1022159A (en) | 1963-11-15 | 1965-01-29 | Transistors |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE1564106A1 true DE1564106A1 (en) | 1970-01-15 |
| DE1564106B2 DE1564106B2 (en) | 1973-08-16 |
Family
ID=26238778
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DEST22908A Pending DE1282795B (en) | 1963-11-15 | 1964-11-06 | Method for manufacturing semiconductor devices |
| DE19661564106 Pending DE1564106B2 (en) | 1963-11-15 | 1966-01-14 | METHOD OF MANUFACTURING A FIELD EFFECT TRANSISTOR ELEMENT |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DEST22908A Pending DE1282795B (en) | 1963-11-15 | 1964-11-06 | Method for manufacturing semiconductor devices |
Country Status (6)
| Country | Link |
|---|---|
| BE (2) | BE655773A (en) |
| CH (1) | CH444972A (en) |
| DE (2) | DE1282795B (en) |
| FR (1) | FR1413748A (en) |
| GB (2) | GB1026489A (en) |
| NL (2) | NL6412862A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3538399A (en) * | 1968-05-15 | 1970-11-03 | Tektronix Inc | Pn junction gated field effect transistor having buried layer of low resistivity |
| DE3302025A1 (en) * | 1983-01-22 | 1984-07-26 | Telefunken electronic GmbH, 6000 Frankfurt | Process for producing an epitaxial-base transistor |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL207910A (en) * | 1955-06-20 | |||
| FR1341029A (en) * | 1961-10-04 | 1963-10-25 | Westinghouse Electric Corp | Junction semiconductor diode development |
-
1963
- 1963-11-15 GB GB4522863A patent/GB1026489A/en not_active Expired
-
1964
- 1964-11-04 NL NL6412862A patent/NL6412862A/xx unknown
- 1964-11-06 DE DEST22908A patent/DE1282795B/en active Pending
- 1964-11-13 FR FR994794A patent/FR1413748A/en not_active Expired
- 1964-11-16 BE BE655773D patent/BE655773A/xx unknown
-
1965
- 1965-01-29 GB GB403065A patent/GB1022159A/en not_active Expired
-
1966
- 1966-01-14 DE DE19661564106 patent/DE1564106B2/en active Pending
- 1966-01-18 NL NL6600606A patent/NL6600606A/xx unknown
- 1966-01-26 CH CH104966A patent/CH444972A/en unknown
- 1966-01-27 BE BE675638D patent/BE675638A/xx unknown
Also Published As
| Publication number | Publication date |
|---|---|
| BE655773A (en) | 1965-05-17 |
| NL6412862A (en) | 1965-05-17 |
| DE1564106B2 (en) | 1973-08-16 |
| GB1022159A (en) | 1966-03-09 |
| BE675638A (en) | 1966-07-27 |
| CH444972A (en) | 1967-10-15 |
| GB1026489A (en) | 1966-04-20 |
| FR1413748A (en) | 1965-10-08 |
| NL6600606A (en) | 1966-08-01 |
| DE1282795B (en) | 1968-11-14 |
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