DE1464718A1 - Transistor with a predominantly rectangular structure - Google Patents

Transistor with a predominantly rectangular structure

Info

Publication number
DE1464718A1
DE1464718A1 DE19631464718 DE1464718A DE1464718A1 DE 1464718 A1 DE1464718 A1 DE 1464718A1 DE 19631464718 DE19631464718 DE 19631464718 DE 1464718 A DE1464718 A DE 1464718A DE 1464718 A1 DE1464718 A1 DE 1464718A1
Authority
DE
Germany
Prior art keywords
transistor
emitter
area
areas
predominantly
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE19631464718
Other languages
German (de)
Inventor
Dieter Thor
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Halbleiterwerk Frankfurt Oder VEB
Original Assignee
Halbleiterwerk Frankfurt Oder VEB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Halbleiterwerk Frankfurt Oder VEB filed Critical Halbleiterwerk Frankfurt Oder VEB
Publication of DE1464718A1 publication Critical patent/DE1464718A1/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0804Emitter regions of bipolar transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Bipolar Transistors (AREA)

Description

Transistor mit vorwiegend rechteckiger Struktur Die Erfindung betrifft einen Transistor mit vorwiegend recht.-eokiger Struktur und mit einem kammförmig ausgebildeten Emittergebiet sowie kammförmig ineinandergreifenden, die Oberfläche des Emitter- und Basisgebieteo jeweils zusammenhängend mindestens teilweise bedeckenden Bmitter- und Bagiskontaktgebieteo, Es ist bekannt, daß die verschiedenen leitfähigkeitagebiete einer Halbleiteranordnung, z.B. das Emitter- und Basiogebiet eines Transistorot mit die Oberfläche dieser Gebiete mindestens teilweise bedeckenden Kontaktgebieten versehen sein müßen, die der Stromzuführung dienen, Es ist ferner bekannt, daß bei Tranaistoren für höhere Strombelastung die Emittergebiete großflächig ausgebildet werden mäßen. Da nun aber infolge des Stromverdrängungseffektes am Entitter bei höheren Strömen nur die Randzonen des Emittergebietes wirksam sind, wurde bereits vorgesohlagen,-die Emittergebiete so auszubilden, daß man eine auf ihre Ausdehnung bezogen möglichst große Kantenlänge erhält, So wurden z.B, der Emitter und das Emitterkontaktgebiet in Form mehrerer langgestreokter, such kreisförmig gebogener Streifen angeordnet, zu deren beiden Seiten Basiakontaktstreifen angebracht wurden.The invention relates to a transistor with a predominantly rectangular structure and with a comb-shaped emitter area as well as comb-shaped interlocking, the surface of the emitter and base areas each contiguously at least partially covering the emitter and bagis contact areas. It is known that the Different conductivity areas of a semiconductor arrangement, e.g. the emitter and base area of a transistor, have to be provided with contact areas which at least partially cover the surface of these areas and which are used for power supply. However, since only the edge zones of the emitter area are effective due to the current displacement effect at the emitter at higher currents, it has already been planned to design the emitter areas in such a way that one obtains an edge length that is as large as possible in relation to their extension, for example, the emitter and the emitter contact area arranged in the form of several elongated, such circularly curved strips, on both sides of which base contact strips were attached.

Um nicht mehrere jeweils voneinander getrennte EmUer- und Basiskontaktgebiete mit Stromzuführungen versehen zu müßen, wurde auch bereits vorgeschlagen, mehrere derartige Streifen kammförmig zusammenzufassen, wobei bei Emitter- und Baoiokontakt jeweils ein zusammenhängendes Gebiet entstehen soll, auf dem eine Stromzuführung möglichst günstig angebracht werden kann, Dies ist für die Erzielung kleiner Bahnwiderstände im Transistor erforderlich. insbesondere sind Kamm- und Doppelkammanordnungen bekannt, die symmetrisch zu einer Seitenhalbierenden der rechteckigen Oberfläche des Transistors ausgebildet sind. Bei derartigen Anordnungen sind jedoch die zum großflächigen Anbringen von Stromzuführungen vorgesehenen Gebiete ungünstig geformt, oder es muß die Gesamtkontaktfiäohe und damit auch das Bmittergebiet so groß gewählt werden, daß ungünstige Wirkungen auf andere Transistoreigenschaften, z.B. die Kollektorkapazität, folgen, Auch Yrd bei solchen Anordnungen entweder die auf die Ausdehnung des Emittergebietes bezogene Kantenlänge zu klein, oder die Strompfade im Kontaktgebiet werden unzweckmäßig lang was zu ungünstigem Stromverstärkungaverhalten oder erhöhten Bahnwiderständen im Transistor führt. Aufgabe der Erfindung ist es nun, das kammförmige Bmittergebiet und die entsprechenden kammförmigen Emitter- und Basiskontaktgebiete so zu gestalten, daß bei möglichst klein zu haltendem Emittergebiet und großer auf das Emittergebiet bezogener Kantenlänge sowie möglichst kurzen Strompfaden im jeweiligen Kontaktgebiet die Kontaktgebiete jeweils ein für das Anbringen der Stromzuführungen genügend großflächiges und günstig geformtes Teilgebiet aufweisen, Erfindungsgemäß wird daher vorgeschlagen, vorwiegend rechteokige Teilgebiete des Emitter- bzw. Bmitterkontaktgebietes und des Basiskontaktgebietes symmetrisch zur Flächendiagonalen der Transistoeoberfläche anzuordnen, wie es beispielsweise aus der Figur erdiohtlich ist. Eine derartige Anordnung bietet den Vorteil, Stromzuleitungen großflächig, z.B, durch Löten, anbringen zu können, wobei außerdem die Strompfade im Kontaktgebiet kurz und weiterhin die Gesmtfläohe bei großer Kantenlänge verhältnismäßig klein gehalten werden. Die Erfindung soll an einem Ausführungsbeihpiel gemäß der Figur näher erläutert werden, Die Figur zeigt die Draufsicht auf einen Transistor gemäß der Erfindung. Das das Emittergebiet nahezu bedeckende Emitterkontaktgebiet 1 ist von dem Basiskontaktgebiet 2 umgeben. Die Struktur ineinandergreifender Kämme ist so ausgebildet, daß symmetrisch zur Flächendiagonale der Transistoroberfläohe liegende rechteckige Flächen 3 entstehen, die für das Anbringen großfläohiger StromzußUhrungen gut geeignet sind. Die Strompfade wie z.B. # sind kurz, die Kantenlänge auf die Ylgohe bezogen groß, Die Herstellung von Transistoren mit der erfindungsgemäßen Ausbildung der Imitter- und Basiskontaktgebiete kann teohno- logisoh in itblioher Weise erfolgeng s.B. duroh Vakuumbe-- dampfen oder auoh duroh elektroohemisohes Absoheiden unter Be-. nutsung von Banken. In order not to have to provide several separate EmUer and base contact areas with power leads, it has also already been proposed to combine several such strips in a comb shape, with the emitter and Baoio contact each creating a coherent area on which a power lead can be attached as cheaply as possible, This is necessary to achieve small track resistances in the transistor. In particular, comb and double comb arrangements are known which are symmetrical about a bisector of the rectangular surface of the transistor. In such arrangements, however, the areas provided for the large-area attachment of power leads are unfavorably shaped, or the total contact area and thus also the transmitter area must be selected so large that adverse effects on other transistor properties, e.g. the collector capacitance, follow, including Yrd in such arrangements either the edge length related to the extent of the emitter area is too small, or the current paths in the contact area are inexpediently long, which leads to unfavorable current amplification behavior or increased sheet resistances in the transistor. The object of the invention is to design the comb-shaped emitter area and the corresponding comb-shaped emitter and base contact areas in such a way that with the emitter area to be kept as small as possible and with a large edge length related to the emitter area and the shortest possible current paths in the respective contact area, the contact areas each have one for attachment the power supply lines have sufficiently large and favorably shaped subareas, according to the invention it is therefore proposed that predominantly rectangular subareas of the emitter or emitter contact area and the base contact area be arranged symmetrically to the diagonal of the transistor surface, as can be seen from the figure, for example. To be able to attach by brazing, such an arrangement offers the advantage of current leads over a large area, for example, in which also the current paths in the contact region further, the Gesmtfläohe be kept relatively small at a large edge length and short. The invention will be explained in more detail using an exemplary embodiment according to the figure. The figure shows the top view of a transistor according to the invention. The emitter contact region 1, which almost covers the emitter region, is surrounded by the base contact region 2. The structure of interlocking combs is designed so that symmetrical to the diagonal of the transistor surface lying rectangular surfaces 3 arise, which for the Attaching large-area power supply clocks are well suited. The current paths such as # are short, the edge length to the Ylgohe covered large, The manufacture of transistors with the inventive Training of the central and basic contact areas can teohno- logisoh done in an Italian wayg sB duroh vacuum steam or auoh duroh electroohemisohes Absoheiden under loading. nutsung of banks.

Claims (1)

Patentanspruoh: Transistor mit vorwiegend reohteokiaer Struktur und mit eines kam@Sraia ausgebildeten Bmitteraebiet sowie kemfürmia inein- anderareitendeng die Oberi'läohe den Imitter- und Baeinaebieted jeweils ausamaahän6end mindestens teilweise bedeokenden Emit- ter- und Basinkontaktaebieteng d a d u r o h 6 e k e n n s e i o h n e t 9 daß vorwiegend reohteokige Teilgebiete des Gitters bsw. Bmitterkontaktgebietee und des symmetrisoh zur 7l&tohendiaaonalen der Transistorober- i"läohe angeordnet sind.
Patent claim: Transistor with predominantly reohteokiaer structure and with one came @ Sraia trained Bmittera area and kemfürmia into one- on the other hand the Oberi'läohe the Imitter- and Baeinaebieted at least partially signifying issuers in each case ter and basin contact areas daduroh 6 ekenn se i ohnet 9 that predominantly reohteokige sub-areas of the grid bsw. Bmitterkontaktgebietee and des symmetrical to the 7l & tohendiaaonal of the transistor upper i "läohe are arranged.
DE19631464718 1963-11-23 1963-11-23 Transistor with a predominantly rectangular structure Pending DE1464718A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DEI0024786 1963-11-23
DEJ0024786 1963-11-23

Publications (1)

Publication Number Publication Date
DE1464718A1 true DE1464718A1 (en) 1969-04-24

Family

ID=25981296

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19631464718 Pending DE1464718A1 (en) 1963-11-23 1963-11-23 Transistor with a predominantly rectangular structure

Country Status (1)

Country Link
DE (1) DE1464718A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0125571A2 (en) * 1983-05-13 1984-11-21 Deutsche ITT Industries GmbH Low-noise planar transistor and method of making the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0125571A2 (en) * 1983-05-13 1984-11-21 Deutsche ITT Industries GmbH Low-noise planar transistor and method of making the same
EP0125571A3 (en) * 1983-05-13 1986-12-30 Deutsche Itt Industries Gmbh Low-loss planar transistor and method of making the same

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