DE112013000798T8 - Epitaktische Technik zum Reduzieren von Schraubenversetzungen in unter Spannung befindlichen Halbleiterverbundstoffen - Google Patents

Epitaktische Technik zum Reduzieren von Schraubenversetzungen in unter Spannung befindlichen Halbleiterverbundstoffen Download PDF

Info

Publication number
DE112013000798T8
DE112013000798T8 DE112013000798.3T DE112013000798T DE112013000798T8 DE 112013000798 T8 DE112013000798 T8 DE 112013000798T8 DE 112013000798 T DE112013000798 T DE 112013000798T DE 112013000798 T8 DE112013000798 T8 DE 112013000798T8
Authority
DE
Germany
Prior art keywords
screw dislocations
reducing screw
epitaxial technique
stressed semiconductor
semiconductor composites
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE112013000798.3T
Other languages
English (en)
Other versions
DE112013000798T5 (de
Inventor
Maxim S. Shatalov
Alexander Dobrinsky
Remigijus Gaska
Michael Shur
Wenhong Sun
Rakesh Jain
Jinwei Yang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sensor Electronic Technology Inc
Original Assignee
Sensor Electronic Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sensor Electronic Technology Inc filed Critical Sensor Electronic Technology Inc
Publication of DE112013000798T5 publication Critical patent/DE112013000798T5/de
Application granted granted Critical
Publication of DE112013000798T8 publication Critical patent/DE112013000798T8/de
Active legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02587Structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/0242Crystalline insulating materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02455Group 13/15 materials
    • H01L21/02458Nitrides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02494Structure
    • H01L21/02496Layer structure
    • H01L21/02505Layer structure consisting of more than two layers
    • H01L21/02507Alternating layers, e.g. superlattice
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02538Group 13/15 materials
    • H01L21/0254Nitrides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005Processes
    • H01L33/0062Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/16Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Led Devices (AREA)
DE112013000798.3T 2012-02-01 2013-02-01 Epitaktische Technik zum Reduzieren von Schraubenversetzungen in unter Spannung befindlichen Halbleiterverbundstoffen Active DE112013000798T8 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201261593426P 2012-02-01 2012-02-01
US60/593,426 2012-02-01
US61/593,426 2012-02-01
PCT/US2013/024310 WO2013116622A1 (en) 2012-02-01 2013-02-01 Epitaxy technique for reducing threading dislocations in stressed semiconductor compounds

Publications (2)

Publication Number Publication Date
DE112013000798T5 DE112013000798T5 (de) 2014-12-04
DE112013000798T8 true DE112013000798T8 (de) 2014-12-18

Family

ID=48869493

Family Applications (1)

Application Number Title Priority Date Filing Date
DE112013000798.3T Active DE112013000798T8 (de) 2012-02-01 2013-02-01 Epitaktische Technik zum Reduzieren von Schraubenversetzungen in unter Spannung befindlichen Halbleiterverbundstoffen

Country Status (4)

Country Link
US (1) US10211048B2 (de)
CN (1) CN104160479B (de)
DE (1) DE112013000798T8 (de)
WO (1) WO2013116622A1 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10158044B2 (en) 2011-12-03 2018-12-18 Sensor Electronic Technology, Inc. Epitaxy technique for growing semiconductor compounds
US10490697B2 (en) 2011-12-03 2019-11-26 Sensor Electronic Technology, Inc. Epitaxy technique for growing semiconductor compounds
US9312428B2 (en) 2013-01-09 2016-04-12 Sensor Electronic Technology, Inc. Light emitting heterostructure with partially relaxed semiconductor layer
US9960315B2 (en) 2013-01-09 2018-05-01 Sensor Electronic Technology, Inc. Light emitting heterostructure with partially relaxed semiconductor layer
US10804423B2 (en) 2013-09-03 2020-10-13 Sensor Electronic Technology, Inc. Optoelectronic device with modulation doping
US9647168B2 (en) 2013-09-03 2017-05-09 Sensor Electronic Technology, Inc. Optoelectronic device with modulation doping
CN105518878B (zh) 2013-09-03 2018-05-25 传感器电子技术股份有限公司 具有调制掺杂的光电子器件
US10903391B2 (en) 2013-09-03 2021-01-26 Sensor Electronic Technology, Inc. Optoelectronic device with modulation doping
JP6860293B2 (ja) * 2015-04-28 2021-04-14 日機装株式会社 発光素子および発光素子の製造方法
US10923619B2 (en) 2016-06-01 2021-02-16 Sensor Electronic Technology, Inc. Semiconductor heterostructure with at least one stress control layer
CN117650210A (zh) * 2023-12-29 2024-03-05 聚灿光电科技(宿迁)有限公司 一种具有应力释放层的led外延结构及其生长方法

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2707183B2 (ja) 1992-03-12 1998-01-28 国際電信電話株式会社 ひずみ超格子を有する半導体デバイス
KR100363241B1 (ko) 1995-05-25 2003-02-05 삼성전자 주식회사 다중 양자 우물형 레이저 다이오드 및 그 제조방법
US5880491A (en) * 1997-01-31 1999-03-09 The United States Of America As Represented By The Secretary Of The Air Force SiC/111-V-nitride heterostructures on SiC/SiO2 /Si for optoelectronic devices
EP1016129B2 (de) 1997-06-24 2009-06-10 Massachusetts Institute Of Technology Kontrolle der verspannungsdichte durch verwendung von gradientenschichten und durch planarisierung
JP4214585B2 (ja) * 1998-04-24 2009-01-28 富士ゼロックス株式会社 半導体デバイス、半導体デバイスの製造方法及び製造装置
US6472695B1 (en) * 1999-06-18 2002-10-29 The Regents Of The University Of California Increased lateral oxidation rate of aluminum indium arsenide
WO2001054175A1 (en) * 2000-01-20 2001-07-26 Amberwave Systems Corporation Low threading dislocation density relaxed mismatched epilayers without high temperature growth
US6495894B2 (en) * 2000-05-22 2002-12-17 Ngk Insulators, Ltd. Photonic device, a substrate for fabricating a photonic device, a method for fabricating the photonic device and a method for manufacturing the photonic device-fabricating substrate
US6777253B2 (en) * 2000-12-20 2004-08-17 Matsushita Electric Industrial Co., Ltd. Method for fabricating semiconductor, method for fabricating semiconductor substrate, and semiconductor light emitting device
WO2002080242A1 (en) 2001-03-29 2002-10-10 Toyoda Gosei Co., Ltd. Method for manufacturing group-iii nitride compound semiconductor, and group-iii nitride compound semiconductor device
US6958497B2 (en) * 2001-05-30 2005-10-25 Cree, Inc. Group III nitride based light emitting diode structures with a quantum well and superlattice, group III nitride based quantum well structures and group III nitride based superlattice structures
US6855963B1 (en) 2003-08-29 2005-02-15 International Business Machines Corporation Ultra high-speed Si/SiGe modulation-doped field effect transistors on ultra thin SOI/SGOI substrate
ATE503866T1 (de) * 2004-04-30 2011-04-15 Dichroic Cell S R L Verfahren zur herstellung von virtuellen ge- substraten zur iii/v-integration auf si(001)
US20060160345A1 (en) * 2005-01-14 2006-07-20 Xing-Quan Liu Innovative growth method to achieve high quality III-nitride layers for wide band gap optoelectronic and electronic devices
JP4563230B2 (ja) * 2005-03-28 2010-10-13 昭和電工株式会社 AlGaN基板の製造方法
KR20080086905A (ko) 2006-01-20 2008-09-26 마쯔시다덴기산교 가부시키가이샤 반도체 발광 소자, ⅲ족 질화물 반도체 기판, 및 그 제조방법
US7534638B2 (en) 2006-12-22 2009-05-19 Philips Lumiled Lighting Co., Llc III-nitride light emitting devices grown on templates to reduce strain
US8080833B2 (en) * 2007-01-26 2011-12-20 Crystal Is, Inc. Thick pseudomorphic nitride epitaxial layers
JP2008270172A (ja) 2007-03-26 2008-11-06 Fuji Electric Holdings Co Ltd 有機el素子の製造方法
JP4538476B2 (ja) * 2007-08-27 2010-09-08 独立行政法人理化学研究所 半導体構造の形成方法
JP2009054782A (ja) 2007-08-27 2009-03-12 Institute Of Physical & Chemical Research 光半導体素子及びその製造方法
US8652948B2 (en) * 2007-11-21 2014-02-18 Mitsubishi Chemical Corporation Nitride semiconductor, nitride semiconductor crystal growth method, and nitride semiconductor light emitting element
KR101495381B1 (ko) * 2007-11-21 2015-02-24 미쓰비시 가가꾸 가부시키가이샤 질화물 반도체의 결정 성장 방법
US8067787B2 (en) 2008-02-07 2011-11-29 The Furukawa Electric Co., Ltd Semiconductor electronic device
KR20100033644A (ko) 2008-09-22 2010-03-31 광주과학기술원 스트레인 보상 하이브리드 양자우물 구조를 갖는 반도체 발광소자 및 그 제조방법
JP5199057B2 (ja) 2008-12-24 2013-05-15 スタンレー電気株式会社 半導体素子の製造方法、積層構造体の製造方法、半導体ウエハおよび積層構造体。
CN102439740B (zh) 2009-03-06 2015-01-14 李贞勋 发光器件
TW201037766A (en) 2009-04-06 2010-10-16 Univ Nat Chiao Tung A method of manufacturing III-V group nitride thick film and the structure thereof
US8674406B2 (en) * 2009-07-17 2014-03-18 Lockheed Martin Corp. Extended wavelength digital alloy NBN detector
US8895959B2 (en) 2010-01-08 2014-11-25 Sensor Electronic Technology, Inc. Superlattice structure and method for making the same
JP2011151074A (ja) * 2010-01-19 2011-08-04 Mitsubishi Electric Corp 窒化物半導体装置の製造方法

Also Published As

Publication number Publication date
CN104160479A (zh) 2014-11-19
CN104160479B (zh) 2019-04-30
US10211048B2 (en) 2019-02-19
WO2013116622A1 (en) 2013-08-08
US20130193480A1 (en) 2013-08-01
DE112013000798T5 (de) 2014-12-04

Similar Documents

Publication Publication Date Title
DE112013000798T8 (de) Epitaktische Technik zum Reduzieren von Schraubenversetzungen in unter Spannung befindlichen Halbleiterverbundstoffen
PL2881499T3 (pl) Sposób hodowli kryształu węgliku krzemu
GB201506267D0 (en) Advanced handler wafer debonding method
EP2863440A4 (de) Siliciumcarbid-halbleiterbauelement und verfahren zur herstellung davon
EP2863417A4 (de) Siliciumcarbid-halbleiterbauelement und verfahren zur herstellung davon
EP2752869A4 (de) Halbleitervorrichtung oder kristall und verfahren zur herstellung der halbleitervorrichtung oder des kristalls
BR302012004118S1 (pt) Configuração aplicada em jarra
SG10201510100UA (en) Semiconductor device
EP2717300A4 (de) Halbleiterbauelement
GB201122288D0 (en) Semiconductor device controllers
EP2763160A4 (de) Halbleiterbauelement
SG11201505829VA (en) Semiconductor device and method for driving semiconductor device
EP2725623A4 (de) Halbleiterbauelement
EP2720263A4 (de) Halbleiterbauelement
EP2752875A4 (de) Halbleiterbauelement
SG10201601757UA (en) Semiconductor device
EP2672516A4 (de) Halbleiterbauelement
EP2793260A4 (de) Halbleiterbauelement
EP2765600A4 (de) Halbleiterbauelement
DE112012001694A5 (de) Hilfsvorrichtung zum manuellen Führen von laufenden Fäden
EP2782130A4 (de) Hochspannungsresistente halbleitervorrichtung
EP2991099A4 (de) Handhabung eines substrats für ein verbundsubstrat für einen halbleiter
EP2889397A4 (de) Kristallherstellungsvorrichtung, verfahren zur herstellung von sic-einkristallen und sic-einkristall
EP2717301A4 (de) Halbleiterbauelement
EP2717302A4 (de) Halbleiterbauelement

Legal Events

Date Code Title Description
R082 Change of representative

Representative=s name: WEBER & HEIM PATENTANWAELTE, DE

Representative=s name: WEBER & HEIM PATENTANWAELTE PARTNERSCHAFTSGESE, DE

R082 Change of representative

Representative=s name: SCHIFFER, AXEL, DIPL.-PHYS.UNIV. DR.RER.NAT., DE

R012 Request for examination validly filed
R016 Response to examination communication
R018 Grant decision by examination section/examining division