DE112006000584T8 - Integrationsschema für ein vollständig silizidiertes Gate - Google Patents

Integrationsschema für ein vollständig silizidiertes Gate Download PDF

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Publication number
DE112006000584T8
DE112006000584T8 DE200611000584 DE112006000584T DE112006000584T8 DE 112006000584 T8 DE112006000584 T8 DE 112006000584T8 DE 200611000584 DE200611000584 DE 200611000584 DE 112006000584 T DE112006000584 T DE 112006000584T DE 112006000584 T8 DE112006000584 T8 DE 112006000584T8
Authority
DE
Germany
Prior art keywords
integration scheme
fully silicided
silicided gate
gate
fully
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE200611000584
Other languages
English (en)
Other versions
DE112006000584T5 (de
DE112006000584B4 (de
Inventor
Marcus Culmsee
Lothar Doni
Hermann Wendt
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of DE112006000584T5 publication Critical patent/DE112006000584T5/de
Publication of DE112006000584T8 publication Critical patent/DE112006000584T8/de
Application granted granted Critical
Publication of DE112006000584B4 publication Critical patent/DE112006000584B4/de
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
DE112006000584T 2005-03-30 2006-03-10 Verfahren zum Ausbilden einer Halbleiteranordnung Expired - Fee Related DE112006000584B4 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/094,367 2005-03-30
US11/094,367 US7544553B2 (en) 2005-03-30 2005-03-30 Integration scheme for fully silicided gate
PCT/EP2006/060632 WO2006103158A2 (en) 2005-03-30 2006-03-10 Integration scheme for fully silicided gate

Publications (3)

Publication Number Publication Date
DE112006000584T5 DE112006000584T5 (de) 2008-01-10
DE112006000584T8 true DE112006000584T8 (de) 2008-04-17
DE112006000584B4 DE112006000584B4 (de) 2010-04-29

Family

ID=36588794

Family Applications (1)

Application Number Title Priority Date Filing Date
DE112006000584T Expired - Fee Related DE112006000584B4 (de) 2005-03-30 2006-03-10 Verfahren zum Ausbilden einer Halbleiteranordnung

Country Status (3)

Country Link
US (1) US7544553B2 (de)
DE (1) DE112006000584B4 (de)
WO (1) WO2006103158A2 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1914800A1 (de) * 2006-10-20 2008-04-23 Interuniversitair Microelektronica Centrum Verfahren zur Herstellung eines Halbleiterbauelements mit mehreren Dielektrika
WO2009153712A1 (en) 2008-06-17 2009-12-23 Nxp B.V. Finfet method and device
US8148227B2 (en) * 2008-10-27 2012-04-03 Infineon Technologies Ag Method for providing a self-aligned conductive structure

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5225896A (en) * 1989-02-01 1993-07-06 U.S. Philips Corporation Protection element and method of manufacturing same
US5891784A (en) * 1993-11-05 1999-04-06 Lucent Technologies, Inc. Transistor fabrication method
JPH1117181A (ja) * 1997-06-26 1999-01-22 Sony Corp 半導体装置の製造方法
US6777759B1 (en) * 1997-06-30 2004-08-17 Intel Corporation Device structure and method for reducing silicide encroachment
US6013569A (en) * 1997-07-07 2000-01-11 United Microelectronics Corp. One step salicide process without bridging
US6087271A (en) * 1997-12-18 2000-07-11 Advanced Micro Devices, Inc. Methods for removal of an anti-reflective coating following a resist protect etching process
US6090653A (en) * 1998-03-30 2000-07-18 Texas Instruments Method of manufacturing CMOS transistors
US6100173A (en) * 1998-07-15 2000-08-08 Advanced Micro Devices, Inc. Forming a self-aligned silicide gate conductor to a greater thickness than junction silicide structures using a dual-salicidation process
US6479166B1 (en) * 1998-10-06 2002-11-12 Case Western Reserve University Large area polysilicon films with predetermined stress characteristics and method for producing same
US6271133B1 (en) * 1999-04-12 2001-08-07 Chartered Semiconductor Manufacturing Ltd. Optimized Co/Ti-salicide scheme for shallow junction deep sub-micron device fabrication
US6287925B1 (en) * 2000-02-24 2001-09-11 Advanced Micro Devices, Inc. Formation of highly conductive junctions by rapid thermal anneal and laser thermal process
US6555453B1 (en) * 2001-01-31 2003-04-29 Advanced Micro Devices, Inc. Fully nickel silicided metal gate with shallow junction formed
US6787424B1 (en) * 2001-02-09 2004-09-07 Advanced Micro Devices, Inc. Fully depleted SOI transistor with elevated source and drain
US6753242B2 (en) * 2002-03-19 2004-06-22 Motorola, Inc. Integrated circuit device and method therefor
US6784101B1 (en) * 2002-05-16 2004-08-31 Advanced Micro Devices Inc Formation of high-k gate dielectric layers for MOS devices fabricated on strained lattice semiconductor substrates with minimized stress relaxation
DE10234931A1 (de) * 2002-07-31 2004-02-26 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung eines Metallsilizidgates in einer standardmässigen MOS-Prozesssequenz
JP2006511083A (ja) 2002-12-20 2006-03-30 コーニンクレッカ　フィリップス　エレクトロニクス　エヌ　ヴィ 半導体装置の製造方法並びにそのような方法で得られる半導体装置
FR2853134B1 (fr) 2003-03-25 2005-07-01 St Microelectronics Sa Procede de fabrication d'un transistor a grille metallique, et transistor correspondant
KR100481185B1 (ko) 2003-07-10 2005-04-07 삼성전자주식회사 완전 게이트 실리사이드화 공정을 사용하여 모스트랜지스터를 제조하는 방법
US6902994B2 (en) * 2003-08-15 2005-06-07 United Microelectronics Corp. Method for fabricating transistor having fully silicided gate
FR2881575B1 (fr) * 2005-01-28 2007-06-01 St Microelectronics Crolles 2 Transistor mos a grille totalement siliciuree

Also Published As

Publication number Publication date
WO2006103158A2 (en) 2006-10-05
DE112006000584T5 (de) 2008-01-10
US20060228844A1 (en) 2006-10-12
US7544553B2 (en) 2009-06-09
WO2006103158A3 (en) 2006-12-07
DE112006000584B4 (de) 2010-04-29

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8696 Reprint of erroneous front page
OP8 Request for examination as to paragraph 44 patent law
8364 No opposition during term of opposition
R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee