DE112005003852A5 - Verfahren und Vorrichtung zum Vektorisieren mehrerer Eingabebefehle - Google Patents

Verfahren und Vorrichtung zum Vektorisieren mehrerer Eingabebefehle Download PDF

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Publication number
DE112005003852A5
DE112005003852A5 DE112005003852T DE112005003852T DE112005003852A5 DE 112005003852 A5 DE112005003852 A5 DE 112005003852A5 DE 112005003852 T DE112005003852 T DE 112005003852T DE 112005003852 T DE112005003852 T DE 112005003852T DE 112005003852 A5 DE112005003852 A5 DE 112005003852A5
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Germany
Prior art keywords
vectoring
multiple input
input commands
commands
vectoring multiple
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE112005003852T
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DE112005003852B4 (de
Inventor
Ronny Ronen
Yoav Almog
Roni Rosner
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Intel Corp
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Intel Corp
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Publication of DE112005003852A5 publication Critical patent/DE112005003852A5/de
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Publication of DE112005003852B4 publication Critical patent/DE112005003852B4/de
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3808—Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3887—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple data lanes [SIMD]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Devices For Executing Special Programs (AREA)
  • Advance Control (AREA)
DE112005003852.1T 2004-06-24 2005-05-25 Verfahren und Vorrichtung zum Vektorisieren mehrerer Eingabebefehle Expired - Fee Related DE112005003852B4 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/874,744 2004-06-24
US10/874,744 US7802076B2 (en) 2004-06-24 2004-06-24 Method and apparatus to vectorize multiple input instructions

Publications (2)

Publication Number Publication Date
DE112005003852A5 true DE112005003852A5 (de) 2012-10-25
DE112005003852B4 DE112005003852B4 (de) 2016-05-04

Family

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Family Applications (2)

Application Number Title Priority Date Filing Date
DE112005001277T Expired - Fee Related DE112005001277B4 (de) 2004-06-24 2005-05-25 Verfahren und Vorrichtung zum Vektorisieren mehrerer Eingabebefehle
DE112005003852.1T Expired - Fee Related DE112005003852B4 (de) 2004-06-24 2005-05-25 Verfahren und Vorrichtung zum Vektorisieren mehrerer Eingabebefehle

Family Applications Before (1)

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DE112005001277T Expired - Fee Related DE112005001277B4 (de) 2004-06-24 2005-05-25 Verfahren und Vorrichtung zum Vektorisieren mehrerer Eingabebefehle

Country Status (6)

Country Link
US (1) US7802076B2 (de)
JP (2) JP2008503836A (de)
CN (1) CN1977241B (de)
DE (2) DE112005001277B4 (de)
GB (1) GB2429554B (de)
WO (1) WO2006007193A1 (de)

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US8051247B1 (en) 2005-09-28 2011-11-01 Oracle America, Inc. Trace based deallocation of entries in a versioning cache circuit
US7877630B1 (en) 2005-09-28 2011-01-25 Oracle America, Inc. Trace based rollback of a speculatively updated cache
US7937564B1 (en) 2005-09-28 2011-05-03 Oracle America, Inc. Emit vector optimization of a trace
US7814298B1 (en) 2005-09-28 2010-10-12 Oracle America, Inc. Promoting and appending traces in an instruction processing circuit based upon a bias value
US8037285B1 (en) 2005-09-28 2011-10-11 Oracle America, Inc. Trace unit
US8032710B1 (en) 2005-09-28 2011-10-04 Oracle America, Inc. System and method for ensuring coherency in trace execution
US8370576B1 (en) 2005-09-28 2013-02-05 Oracle America, Inc. Cache rollback acceleration via a bank based versioning cache ciruit
US7987342B1 (en) 2005-09-28 2011-07-26 Oracle America, Inc. Trace unit with a decoder, a basic-block cache, a multi-block cache, and sequencer
US7870369B1 (en) 2005-09-28 2011-01-11 Oracle America, Inc. Abort prioritization in a trace-based processor
US8024522B1 (en) 2005-09-28 2011-09-20 Oracle America, Inc. Memory ordering queue/versioning cache circuit
US8019944B1 (en) 2005-09-28 2011-09-13 Oracle America, Inc. Checking for a memory ordering violation after a speculative cache write
US7949854B1 (en) 2005-09-28 2011-05-24 Oracle America, Inc. Trace unit with a trace builder
US7953933B1 (en) 2005-09-28 2011-05-31 Oracle America, Inc. Instruction cache, decoder circuit, basic block cache circuit and multi-block cache circuit
US7966479B1 (en) 2005-09-28 2011-06-21 Oracle America, Inc. Concurrent vs. low power branch prediction
US7783863B1 (en) 2005-09-28 2010-08-24 Oracle America, Inc. Graceful degradation in a trace-based processor
US7606975B1 (en) 2005-09-28 2009-10-20 Sun Microsystems, Inc. Trace cache for efficient self-modifying code processing
US7849292B1 (en) 2005-09-28 2010-12-07 Oracle America, Inc. Flag optimization of a trace
US7953961B1 (en) 2005-09-28 2011-05-31 Oracle America, Inc. Trace unit with an op path from a decoder (bypass mode) and from a basic-block builder
US7681019B1 (en) 2005-11-18 2010-03-16 Sun Microsystems, Inc. Executing functions determined via a collection of operations from translated instructions
US7797517B1 (en) * 2005-11-18 2010-09-14 Oracle America, Inc. Trace optimization via fusing operations of a target architecture operation set
US8904151B2 (en) * 2006-05-02 2014-12-02 International Business Machines Corporation Method and apparatus for the dynamic identification and merging of instructions for execution on a wide datapath
US8370609B1 (en) 2006-09-27 2013-02-05 Oracle America, Inc. Data cache rollbacks for failed speculative traces with memory operations
US8010745B1 (en) 2006-09-27 2011-08-30 Oracle America, Inc. Rolling back a speculative update of a non-modifiable cache line
US8056067B2 (en) * 2006-09-29 2011-11-08 International Business Machines Corporation Method, computer program product, and device for reducing delays in data processing
US8640112B2 (en) * 2011-03-30 2014-01-28 National Instruments Corporation Vectorizing combinations of program operations
JP5887811B2 (ja) * 2011-10-05 2016-03-16 富士通株式会社 コンパイル装置、コンパイル方法、コンパイルプログラム、記録媒体
US9009686B2 (en) * 2011-11-07 2015-04-14 Nvidia Corporation Algorithm for 64-bit address mode optimization
TWI447646B (zh) 2011-11-18 2014-08-01 Asmedia Technology Inc 資料傳輸裝置及多個指令的整合方法
US8984499B2 (en) * 2011-12-15 2015-03-17 Intel Corporation Methods to optimize a program loop via vector instructions using a shuffle table and a blend table
JP5413473B2 (ja) * 2012-03-01 2014-02-12 日本電気株式会社 ベクトル処理装置およびベクトル処理方法
US9513915B2 (en) * 2012-03-28 2016-12-06 International Business Machines Corporation Instruction merging optimization
US9292291B2 (en) * 2012-03-28 2016-03-22 International Business Machines Corporation Instruction merging optimization
JP5846006B2 (ja) * 2012-03-29 2016-01-20 富士通株式会社 プログラム、コード生成方法および情報処理装置
JP5846005B2 (ja) * 2012-03-29 2016-01-20 富士通株式会社 プログラム、コード生成方法および情報処理装置
JP5966509B2 (ja) * 2012-03-29 2016-08-10 富士通株式会社 プログラム、コード生成方法および情報処理装置
US9170789B2 (en) * 2013-03-05 2015-10-27 Intel Corporation Analyzing potential benefits of vectorization
US9348596B2 (en) 2013-06-28 2016-05-24 International Business Machines Corporation Forming instruction groups based on decode time instruction optimization
CN103440229B (zh) * 2013-08-12 2017-11-10 浪潮电子信息产业股份有限公司 一种基于mic架构处理器的向量化优化方法
GB2520571B (en) 2013-11-26 2020-12-16 Advanced Risc Mach Ltd A data processing apparatus and method for performing vector processing
JP6237278B2 (ja) 2014-01-31 2017-11-29 富士通株式会社 コンパイルプログラム、コンパイル方法およびコンパイル装置
US11042929B2 (en) 2014-09-09 2021-06-22 Oracle Financial Services Software Limited Generating instruction sets implementing business rules designed to update business objects of financial applications
DE102015013627A1 (de) * 2015-10-20 2017-04-20 Fresenius Medical Care Deutschland Gmbh Blutbehandlungsgerät und Verfahren zur Erstellung einer Verschreibung
US10061580B2 (en) 2016-02-25 2018-08-28 International Business Machines Corporation Implementing a received add program counter immediate shift (ADDPCIS) instruction using a micro-coded or cracked sequence
KR102593320B1 (ko) 2016-09-26 2023-10-25 삼성전자주식회사 전자 장치, 프로세서 및 그 제어 방법
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CN110858150A (zh) * 2018-08-22 2020-03-03 上海寒武纪信息科技有限公司 一种具有局部实时可重构流水级的运算装置
JP7468650B2 (ja) * 2020-06-25 2024-04-16 日本電気株式会社 情報処理装置、情報処理方法、及び、プログラム

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Also Published As

Publication number Publication date
GB2429554A (en) 2007-02-28
JP2008503836A (ja) 2008-02-07
JP5646390B2 (ja) 2014-12-24
GB2429554B (en) 2009-04-22
CN1977241A (zh) 2007-06-06
DE112005001277T5 (de) 2007-05-16
CN1977241B (zh) 2011-08-03
DE112005003852B4 (de) 2016-05-04
JP2011165216A (ja) 2011-08-25
GB0619968D0 (en) 2006-11-29
DE112005001277B4 (de) 2012-10-31
WO2006007193A1 (en) 2006-01-19
US7802076B2 (en) 2010-09-21
US20050289529A1 (en) 2005-12-29

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