DE10297185T5 - Verfahren zur Ausbildung einer gemusterten Metallschicht - Google Patents

Verfahren zur Ausbildung einer gemusterten Metallschicht Download PDF

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Publication number
DE10297185T5
DE10297185T5 DE10297185T DE10297185T DE10297185T5 DE 10297185 T5 DE10297185 T5 DE 10297185T5 DE 10297185 T DE10297185 T DE 10297185T DE 10297185 T DE10297185 T DE 10297185T DE 10297185 T5 DE10297185 T5 DE 10297185T5
Authority
DE
Germany
Prior art keywords
forming
metal layer
patterned metal
patterned
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE10297185T
Other languages
English (en)
Inventor
James Francis O'sullivan
Stephen Robert Burgess
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Aviza Europe Ltd
Original Assignee
Aviza Europe Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GBGB0127075.0A external-priority patent/GB0127075D0/en
Application filed by Aviza Europe Ltd filed Critical Aviza Europe Ltd
Publication of DE10297185T5 publication Critical patent/DE10297185T5/de
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0272—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers for lift-off processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/04—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching
    • H05K3/046—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching by selective transfer or selective detachment of a conductive layer
    • H05K3/048—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching by selective transfer or selective detachment of a conductive layer using a lift-off resist pattern or a release layer pattern

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Physical Vapour Deposition (AREA)
  • Electroluminescent Light Sources (AREA)
  • Electrodes Of Semiconductors (AREA)
DE10297185T 2001-11-10 2002-11-08 Verfahren zur Ausbildung einer gemusterten Metallschicht Withdrawn DE10297185T5 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
GBGB0127075.0A GB0127075D0 (en) 2001-11-10 2001-11-10 Method of forming a patterned metal layer
US39197102P 2002-06-28 2002-06-28
PCT/GB2002/005090 WO2003043062A1 (en) 2001-11-10 2002-11-08 Method of forming a patterned metal layer

Publications (1)

Publication Number Publication Date
DE10297185T5 true DE10297185T5 (de) 2004-10-07

Family

ID=26246757

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10297185T Withdrawn DE10297185T5 (de) 2001-11-10 2002-11-08 Verfahren zur Ausbildung einer gemusterten Metallschicht

Country Status (3)

Country Link
DE (1) DE10297185T5 (de)
GB (1) GB2404084A (de)
WO (1) WO2003043062A1 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ITMI20050616A1 (it) * 2005-04-12 2006-10-13 Getters Spa Processo per la formazione di depositi getter miniaturizzati e depositi getrter cosi'ottenuti

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1190294B (it) * 1986-02-13 1988-02-16 Selenia Ind Elettroniche Una struttura di fotopolimero a multistrati (mlr) per la fabbricazione di dispositivi mesfet con gate submicrometrico e con canale incassato (recesse) di lunghezza variabile
EP0341843A3 (de) * 1988-05-09 1991-03-27 International Business Machines Corporation Verfahren zur Herstellung eines Leitermusters
FR2658362A1 (fr) * 1990-02-09 1991-08-16 Philips Electronique Lab Procede de realisation par autoalignement, d'un dispositif semiconducteur integre, comprenant au moins la formation d'un premier contact d'electrode encapsule et muni d'espaceurs et d'un second contact d'electrode autoaligne sur celui-ci.
JPH07161711A (ja) * 1993-12-10 1995-06-23 Hitachi Ltd パターン形成法
US5773200A (en) * 1994-06-23 1998-06-30 Shin-Etsu Chemical Co., Ltd. Positive resist composition suitable for lift-off technique and pattern forming method
US5568335A (en) * 1994-12-29 1996-10-22 International Business Machines Corporation Multi-layer gap structure for high resolution magnetoresistive read head
US5658469A (en) * 1995-12-11 1997-08-19 Quantum Peripherals Colorado, Inc. Method for forming re-entrant photoresist lift-off profile for thin film device processing and a thin film device made thereby
JP4258960B2 (ja) * 2000-07-28 2009-04-30 株式会社村田製作所 薄膜形成方法

Also Published As

Publication number Publication date
WO2003043062A1 (en) 2003-05-22
GB2404084A (en) 2005-01-19
GB0403552D0 (en) 2004-03-24

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Legal Events

Date Code Title Description
8128 New person/name/address of the agent

Representative=s name: ZEITLER, VOLPERT, KANDLBINDER, 80539 MUENCHEN

8139 Disposal/non-payment of the annual fee