DE10202274B4 - Integrated semiconductor circuit arrangement - Google Patents

Abstract

Integrated semiconductor circuit arrangement with at least one semiconductor component arrangement (10 ', 20') having at least one semiconductor component (10, 20), which is provided with a drift region (2) in a semiconductor substrate (1), wherein between the drift region (2) and the semiconductor substrate ( 1) for the electrical insulation of the respective semiconductor component arrangement (10 ', 20') and / or the respective semiconductor components (10, 20), a double well insulation structure (30) with a first or inner doping well region (8) and with a second or outer doping well region (9) is provided, the sequence of conduction types of the drift region (2), the adjoining inner doping well region (8), the adjoining outer doping well region (9) and the adjoining semiconductor substrate region (1) alternating between a first conductivity type and a second Conduction type is formed alternately and the two doping wells ete (8, 9) are significantly more heavily doped than the drift region (2) and the semiconductor substrate (1), wherein between the doping well regions (8, 9) of a semiconductor component arrangement (10 ', 20') one made of the same material as the drift region (2 ) educated or ...

Description

The invention relates to a semiconductor integrated circuit arrangement having at least one semiconductor component arrangement having at least one semiconductor component, which is provided with a drift region in a semiconductor substrate, wherein between the drift region and the semiconductor substrate for electrically insulating the respective semiconductor component arrangement and / or the respective semiconductor components a double-well isolation structure having a first or inner doping well region and with a second or outer doping well region, the sequence of conductivity types or conductivity types of the drift region, the adjoining inner doping well region, the adjoining outer doping well region and the adjoining semiconductor substrate region alternating between a first conductivity type or conductivity type and a second conductivity type or conductivity type is alternately formed and the two doping well regions are doped significantly higher than the drift region and the semiconductor substrate.

Particular attention has been paid to the advancement of integrated circuit technology, including achieving ever higher integration densities and improving the functional reliability of semiconductor integrated circuit devices in the applications. This applies in particular to the field of so-called power semiconductor electronics. A particular problem in this area is the need for electrical isolation of areas of the semiconductor circuitry which vary greatly in the electrical potentials applied to them.

For example, in the field of power semiconductor electronics, it is necessary to isolate control circuits which operate on a ground-specific basis and which are therefore referred to as the low-side of the circuit, which do not operate on a ground-related basis and which therefore are referred to as a so-called high-side of the integrated semiconductor circuit arrangement become.

To achieve such isolation mechanisms, so-called double-well isolation structures have been provided which have a first or inner doping well region and a second or outer doping well region and in which a respective semiconductor component arrangement is embedded, each having at least one semiconductor component with a corresponding drift region. This arrangement is then embedded in a corresponding semiconductor substrate region. The provision of such a double-well insulation structure on the one hand ensures the required isolation or plasma isolation of the respective component or of the semiconductor component arrangement and in particular of the respective high-injection component, also with respect to leakage currents. The dual nature of the isolation well structure is necessary to also accommodate and isolate any transient currents that may occur during operation due to stray inductances. This dual nature is therefore also necessary in order to ensure the voltage isolation of transient over and under voltages during operation, in which the voltage at one or the other terminal of the surrounding component or the component arrangement rises or falls above the intermediate circuit voltage due to the influence of the load inductance or stray inductances can fall below the mass.

Known double-well insulation structures, as for example from the DE 199 06 384 A1 but are limited to certain types of semiconductor devices and additionally to certain terminal configurations with respect to the underlying semiconductor substrate. Furthermore, additional high voltage insulation is often required with respect to the terminal metallizations because the nature of the prior art dual well isolation structures enforces particular termination geometries of the semiconductor device arrays in the drift zones.

From the US Pat. No. 6,288,424 B1 For example, a laterally-formed DMOS transistor is known that avoids minority carrier injections in the substrate and suppresses parasitic vertical bipolar NPN transistors. For this purpose, an oppositely doped double well structure is provided, which surrounds the DMOS transistor, wherein an inner p-well is connected to a low impedance via a plurality of drain extensions. An outer tub is formed relatively high impedance and thus has a comparatively low dopant concentration. In this way, an isolation of a charge carrier plasma can not be achieved, because it requires a high doping for the double-insulation well structure.

Furthermore, from the EP 0 915 508 A1 Semiconductor devices and in particular integrated circuits with junction isolation known in which also inductive overvoltages and minority carrier injections in the substrate should be avoided and parasitic transistors to be suppressed. It is essential that this is achieved without a local separation of the respective affected components. Is achieved This is achieved by providing an oppositely doped double well structure which surrounds an area with active structures, wherein the respective inner well structure is p-doped and the outer well structure is n-doped.

The outer n-well structure and connections of the p- and n-well structure are not indicated as heavily doped.

In the US 5 591 662 A is the so-called Power Integrated Circuit (PIC) technology, which is concretely composed of a vertical power device, for example a DMOS or an NPN transistor, and lateral drive components. In this case, NMOS and PMOS devices are to be integrated as part of the PIC technology, but no restrictions with respect to the application of the respective power device as a low or high-side switch should be present. This is accomplished by introducing a simple p-well to isolate the drive devices, such as the NMOS and PMOS devices, from the power device.

Furthermore, from the DE 37 25 429 A1 a monolithic integrated circuit arrangement is known in which in a semiconductor substrate, two transistors are provided, which are surrounded by two well regions, resulting in an isolation from a substrate. There is a direct contact between the two well regions, so that a diode structure results in each case through the direct contact of the well regions.

Finally, an essay by GÓMEZ, R .; BASHIR, R .; NEUDECK, G.W .: On the design and fabrication of novel lateral bipolar transistors in a deep-submicron technology, in Microelectronics Journal, No. 31, 2000, pp. 199-205 a semiconductor device with well structures, which enclose components. Again, a p-well and an n-well are formed in direct mechanical and electrical contact with each other.

The invention has for its object to provide a semiconductor integrated circuit arrangement and in particular an integrated semiconductor device for low and high-injecting low-side and high-side devices with low and high voltage resistance, which can be used particularly flexible and nevertheless reliable and protected with increasing integration densities is.

The object is achieved in an integrated semiconductor circuit arrangement of the aforementioned type according to the invention that between the doping well regions of a semiconductor device arrangement a distance or from the same material as the drift region formed or doped with the same dopant material as the semiconductor substrate gap area is provided, and that the Do not touch the doping bath areas directly. Advantageous developments of the integrated semiconductor circuit arrangement according to the invention are the subject of the dependent subclaims.

The generic integrated semiconductor circuit arrangement has at least one semiconductor component arrangement having at least one semiconductor component, which is provided with a drift region in a semiconductor substrate region, wherein between the drift region and the semiconductor substrate region for electrical isolation of the respective semiconductor component arrangement and / or the respective semiconductor components themselves a double well isolation structure having a first or a second well isolation structure inner doping well region and a second or outer doping well region is provided.

In this semiconductor integrated circuit device, the sequence of conduction types or conductivity types of the drift region, the adjoining inner doping well region, the adjoining outer doping well region, and the adjoining semiconductor substrate region are alternately formed between a first conductivity type and a second conductivity type or conductivity type.

The sequence of conduction types or conductivity types of the drift region, of the adjoining inner doping well region, of the adjoining outer doping well region and of the adjoining semiconductor substrate region is thus alternately formed between a first conduction or conductivity type and a second conduction or conductivity type, so that pairs adjacent to each other Material regions have different conductivity types or conductivity types and that between drift region and substrate and between the inner doping well and substrate is always at least one blocking pn junction, no matter which. Polarity has the applied voltage. By these measures is achieved on the one hand, that an electrical insulation of the inner drift region to the outside Semiconductor substrate region can be ensured in a particularly simple manner. Furthermore, due to the alternating sequence of the conductivity types or conductivity types, a particularly flexible configuration of the semiconductor components of the semiconductor component arrangements in the interior of the drift zones or drift regions is possible. Whereas the feasibility of an n-channel IGBT has hitherto occasionally been extremely problematic or impossible, this restriction has been abolished in accordance with the above procedure. Furthermore, existing geometrical limitations with regard to the formation of the semiconductor device arrangement are eliminated, in particular with regard to the terminal metallizations and their electrical insulation.

The effect of the double trough with regard to its voltage insulation properties can be clearly imagined as in a series connection of two oppositely directed diodes (antiserial circuit). In this way, there is always at least one blocking pn junction between the drift region and the substrate and between the inner doping well and the substrate, regardless of the polarity of the applied voltage. The plasma insulation properties of the double trough, on the other hand, are achieved by the high doping of its two individual troughs.

The first and second conductivity types or conductivity types may each be n-type and / or p-type so as to give a sequence npnp or pnpn with respect to the drift region, the inner and outer doping well regions, and the semiconductor substrate region, but with gap regions to be provided between the doping well areas are not considered here.

The fact that this npnp or pnpn structure, which is strongly reminiscent of a thyristor, but does not behave like a thyristor, is due to the high doping of the two isolation wells, which is significantly higher than that of the drift region or of the substrate.

The drift region and the semiconductor substrate region have different conductivity types or conductivity types.

The doping well regions each have a bottom region and sidewall regions.

According to an advantageous embodiment of the integrated semiconductor circuit arrangement according to the invention, the bottom region is formed in each case as a buried layer.

In another embodiment of the integrated semiconductor circuit arrangement according to the invention, sidewall regions are formed as a sequence of implantation and / or diffusion regions.

Alternatively or additionally, sidewall regions may be formed as a sequence of correspondingly filled and / or out-diffused trench or trench structures.

Especially in the field of power semiconductor electronics, it is provided that the drift region and / or the semiconductor substrate region are formed comparatively low doped.

This is necessary to accommodate the comparatively high voltages across the switches or between the high-side and low-side devices.

In another embodiment of the integrated semiconductor circuit arrangement according to the invention, provision is made for the first and / or the second doping well region to be comparatively highly doped. As a result, in particular the insulating effect of the double-tub insulation structure is realized in a particularly reliable manner. The mode of operation of the double trough with regard to its voltage insulation properties can clearly be imagined as the series connection of two oppositely directed diodes (antiserial circuit). In this way, there is always at least one blocking pn junction between the drift region and the substrate and between the inner doping well and the substrate, regardless of the polarity of the applied voltage. The plasma insulation properties of the double trough, on the other hand, are achieved by the high doping of its two individual troughs.

Between the first doping well region and the second doping well region, according to the invention, a gap or gap region is provided such that the first and second doping well regions do not touch each other materially. Rather, a material region is provided in the gap region or spacing region, which is preferably formed from the same material as the drift region itself or which is doped with the same dopant material as the substrate. By this measure it is achieved that in addition to the electrical insulation with respect to leakage currents or in addition to the plasma insulation also transiently appearing voltage and / or current peaks can be recorded and isolated from the rest of the integrated circuit semiconductor device.

In the field of power semiconductor electronics, these transient voltage and / or current peaks occur due to existing inductive loads and / or stray inductances when switching or switching currents and / or current loads and, if they are not absorbed by a blocking pn junction and to other areas , in particular low-voltage areas, are transmitted to the integrated semiconductor circuit arrangement, where they lead to undesired currents in the semiconductor and thus to temporary or permanent malfunctions.

In a particularly preferred embodiment of the semiconductor integrated circuit device according to the invention, a first semiconductor device array and a second semiconductor device array are provided, wherein in particular the first semiconductor device array is associated with and / or at least partially associated with a high voltage area and / or the second semiconductor device array is associated with a low voltage area of the semiconductor integrated circuit device. By virtue of this measure, therefore, high-voltage regions in the power electronics with the corresponding low-voltage regions controlling them can be formed within a common integrated circuit, without causing mutual and negative influences and malfunctions on account of the differing operating peculiarities.

In a particularly advantageous embodiment of the integrated semiconductor circuit arrangement according to the invention, it is provided that directly adjacent semiconductor component arrangements have at least one common sidewall area with respect to their outer doping well areas.

In a further preferred embodiment of the integrated semiconductor circuit arrangement according to the invention, it is provided that a first semiconductor component arrangement assigned to a switch region and / or a high-side region has at least one semiconductor component and in particular at least one high-voltage and / or high-injection semiconductor component an IGBT, a bipolar transistor, a MOS transistor and / or the like, in particular in lateral construction. These are, in particular, those components which are used as high-voltage and / or high-injection components in the switch region and / or high-side region of integrated semiconductor circuit arrangements of power electronics.

In another preferred embodiment of the semiconductor integrated circuit arrangement according to the invention, it is provided that a semiconductor component arrangement assigned to a drive region and / or a low-side region of the semiconductor circuit arrangement has at least one semiconductor component and in particular at least one low-voltage semiconductor component a bipolar transistor, a MOS transistor and / or The like, in particular in a lateral construction.

It is particularly advantageous if the outer doping well region is not contacted, in particular is designed to be floating.

Advantageously, the semiconductor integrated circuit arrangement according to the invention is designed as a half-bridge driver, as a single-chip inverter and / or the like.

Advantageously, it is further provided that the provided low-side device and high-side components, in particular low-side and high-side switches and / or -Ansteuerungen are monolithically integrated on a common chip.

• – Gewährleistung einer Spannungsfestigkeit von mindestens 600 V sollte gegeben sein.
• – Das typische transiente Über- bzw. Unterschwingen des Lastknotens über die Versorgungsspannung bzw. unter Masse darf zu keiner nachteiligen Beeinflussung der beteiligten IC-Bauelemente führen (Eigenverträglichkeit).
• – Das Ladungsträgerplasma von Hochinjektionsbauelementen wie zum Beispiel IGBTs darf sich nicht unkontrolliert auf dem Chip ausbreiten (Eigenverträglichkeit).
• – Die Technologie sollte möglichst billig sein, damit entsprechende Produkte am Markt bestehen können.

These and other aspects of the present invention will become more apparent from the following remarks: In the course of the general trend for system integration, high-side applications, such as half-bridge drivers, single-chip inverters, monolithic integration of the high- and Low-side drive modules as well as the power transistors were considered. Among other things, the following requirements must be fulfilled by a corresponding HVIC technology:

• - Ensure a dielectric strength of at least 600 V should be given.
• - The typical transient overshoot or undershoot of the load node via the supply voltage or ground must not adversely affect the IC components involved (inherent compatibility).
• - The charge carrier plasma of Hochinjektionsbauelementen such as IGBTs may not uncontrolled spread on the chip (Eigenverträglichkeit).
• - The technology should be as cheap as possible so that corresponding products can exist on the market.

• a) Der klassische Ansatz, um die genannten technischen Probleme zu lösen, besteht in der Verwendung eines dielektrisch isolierten Ausgangsmaterialws, z. B. von Silicon-On-Insulator-(SOI-)Wafern, bei denen die aktiven Bauelemente an der Chip-Oberfläche durch eine vergrabene isolierende Schicht wie zum Beispiel Buried-Oxide (BOX) vom restlichen Silizium-Substrat isoliert sind und bei denen tiefe dielektrisch aufgefüllte Trenches verwendet werden, um diese Bauelemente lateral voneinander zu isolieren. Da das Ausgangsmaterial sehr teuer ist, sind auch fertig prozessierte Wafer nicht kostengünstig. Typischerweise kosten derartige Wafer zweimal soviel wie Wafer, die in einer konventionellen Junction Isolation-(JI-)Technologie hergestellt sind.
• b) Es wurde auch vorgeschlagen, eine JI-Technologie mit einer doppelten und entgegengesetzt dotierten PN-Isolationswanne zu verwenden. Diese erfüllt zwar die wirtschaftlichen Anforderungen, hat aber auf der anderen Seite folgende Nachteile: – Für die Realisierung eines bevorzugten n-Kanal IGBTs ist ein n-Substrat erforderlich, das an das Versorgungspotential angeschlossen sein muss. Letzteres ist ungünstig, da sich zum Einen die Masse als Bezugspontential weltweit eingebürgert hat und da zum Anderen mit EMV-Problemen zu rechnen ist, wenn ICs mit unterschiedlichen Bezugssystemen aneinander angeschlossen werden. – Wählt man stattdessen ein p-Substrat, um die Systemmasse als Bezugspotential verwenden zu können, so lässt sich nur ein p-Kanal IGBT realisieren, der über deutlich schlechtere Kurzschlusseigenschaften als ein n-Kanal IGBT verfügt. – Das Gate des IGBTs lässt sich nur über eine Leitung anschließen, welche über den Kollektor (hohe Spannung) geführt werden muss, und erfordert deshalb eine HV-Isolation der Metallisierung. – Da der Kollektor am Rand der Isolationsdoppelwanne liegt, benötigt der IGBT einen zusätzlichen Rand zu benachbarten Bauelementen und insbesondere zu seinen Ansteuerbauelementen, um die hohe Kollektorspannung abzubauen (Randabschluss). – Ein transientes Überschwingen (Unterschwingen) führt bei einem n-Kanal-Low-Side-IGBT (p-Kanal-High-Side) zwangsläufig zu einer Minoritätsträgerinjektion in das Substrat, was zu EMV-Problemen oder auch zu Funktionsstörungen benachbarter Bauelemente führen kann.

So far, the procedure has been as follows:

• a) The classical approach to solve the above technical problems is to use a dielectrically isolated starting material, e.g. Silicon On On Insulator (SOI) wafers in which the active devices on the chip surface are isolated from the remainder of the silicon substrate by a buried insulating layer such as buried oxide (BOX), and where deep dielectrically filled trenches can be used to isolate these components laterally from each other. Since the starting material is very expensive, finished processed wafers are not cost-effective. Typically, such wafers cost twice as much as wafers made in conventional Junction Isolation (JI) technology.
• b) It has also been proposed to use a JI technology with a double and opposite doped PN isolation well. Although this fulfills the economic requirements, it has the following disadvantages, on the other hand: For the realization of a preferred n-channel IGBT, an n-type substrate is required, which must be connected to the supply potential. The latter is unfavorable since, on the one hand, the mass has become established as reference potential worldwide and, on the other hand, EMC problems can be expected when ICs with different reference systems are connected to one another. If one instead selects a p-type substrate in order to be able to use the system ground as the reference potential, then only a p-channel IGBT can be realized which has significantly worse short-circuit properties than an n-channel IGBT. The gate of the IGBT can only be connected via a line which must be conducted across the collector (high voltage) and therefore requires HV insulation of the metallization. Since the collector is located at the edge of the insulation double well, the IGBT requires an additional edge to neighboring components and in particular to its drive components in order to reduce the high collector voltage (edge termination). - Transient overshoot (undershoot) inevitably leads to a minority carrier injection into the substrate in the case of an n-channel low-side IGBT (p-channel high-side), which can lead to EMC problems or malfunction of neighboring components.

• – Billige Technologie, da JI-Technologie.
• – Realisierbarkeit eines n-Kanal-IGBT auf einem an Masse angeschlossenen p-Substrat.
• – Keine HV-Isolation der Metallisierung erforderlich, da der Emitter/Gate-Komplex am Rand und der Kollektor im Zentrum der Isolationswanne zu liegen kommt.
• – Spannungsfestigkeit auch gegen transientes Über- bzw. Unterschwingen des Lastknotens (keine Minoritätsträgerinjektion ins Substrat).

The invention consists inter alia in an improved structure of a JI technology with double and oppositely doped PN wells. It has the following advantages:

• - Cheap technology, since JI technology.
• Realizability of an n-channel IGBT on a p-type substrate connected to ground.
• - No HV insulation of the metallization required, since the emitter / gate complex at the edge and the collector comes to rest in the center of the insulation pan.
• - Dielectric strength also against transient overshoot or undershoot of the load node (no minority carrier injection into the substrate).

• a) eine optimierte JI-Struktur,
• b) die Verwendung einer floatenden (nicht angeschlossenen) n-Wanne und
• c) kein flächenintensiver Randabschluss für HV-Bauelemente erforderlich.

Basic aspects of the invention are thus:

• a) an optimized JI structure,
• b) the use of a floating (not connected) n-tub and
• c) no area-intensive edge termination for HV components required.

The invention will be explained in more detail with reference to a schematic drawing based on preferred embodiments.

1 shows a first embodiment of the semiconductor integrated circuit arrangement according to the invention using the example of a low-side switch and a low-side drive.

2 shows a second embodiment of the inventive semiconductor circuit arrangement using the example of a high-side switch and a high-side drive.

3 shows in schematic form a possible application of the semiconductor integrated circuit arrangement according to the invention.

In the embodiments of the semiconductor circuit arrangement according to the invention described below in accordance with FIGS 1 to 3 Denote identical reference numerals the same or equivalent structures or components without a detailed description is repeated in each case of their occurrence.

To make the motivation of the invention clear, is on 3 which shows a part of a possible application of the semiconductor integrated circuit device according to the invention. Goal of this so-called half-bridge arrangement 3 it is the burden III with the help of the switch Ia and IIa alternating with the ground and the intermediate circuit voltage 600 V to connect and in this way the load III to control. The drive circuits ib and IIb serve to control (switching on and off) of the switch Ia and IIa ,

In this context, the terms "low-side" and "high-side" become clear. Low-side identifies the switches and drivers that operate on a per-mass basis; d. H. connected to ground. "High-side" characterizes the switches and control components that are not ground-referenced, but based on the DC link voltage 600 V or based on the switched load node.

Basically now are between the involved circuit parts Ia . ib . IIa . IIb to ensure two different types of insulation. On the one hand, the very different voltages must be isolated from each other ("voltage isolation"). This concerns, for example, the isolation of Ia and ib versus IIa and IIb , but also the isolation of the collector of Ia versus ib and against the gate and emitter of Ia , On the other hand, the charge carrier plasma of each high-injection device must be kept away from the remaining devices ("plasma isolation"). This concerns in particular the switches Ia and IIa but u. U. also one or the other component of the control ib and IIb , High injection device Lower injection device High-voltage component Ia . IIa (eg IGBT, diode) Ia . IIa (eg MOSFET) Nidervoltbauelement ib . IIb (eg BJT, diode ib . IIb (eg CMOS)

1 shows a schematic and sectional side view of a first embodiment of the semiconductor integrated circuit arrangement according to the invention 100 using the example of a low-side switch and a low-side control. It is intended in the context of a first semiconductor device arrangement 10 ' a switch and / or high-side area, high voltage area and / or high injection area. The second semiconductor device arrangement 20 ' on the other hand, denotes a drive, low-side and / or low-voltage region of the integrated semiconductor circuit arrangement according to the invention 100 ,

Based on the embodiment of the 1 a semiconductor substrate region 1 , which in the in 1 embodiment is formed by a p-type substrate of comparatively low doping. To the semiconductor substrate area 1 closes a layer of material 2 ' in the form of an n-doped epitaxial layer. This n-doped epitaxial layer 2 ' forms the basis for the trainee drift zones 2 the embodiment of the 1 , This drift area 2 , which in the embodiment of the 1 exclusively for the first semiconductor device arrangement 10 ' of the high-side area is formed by clipping in the material area 2 ' namely, the n epitaxial layer, by means of the double well isolation structure to be provided 30 realized.

In the embodiment of the 1 has the double-well isolation structure 30 a first or inner doping well region 8th which is complete, namely with its bottom area 8b and its sidewall areas 8s , lies in the n-epitaxial layer. Furthermore, a second or outer doping well region 9 provided, whose bottom area 9b still in the semiconductor substrate area 1 is formed buried. The sidewall areas 8s and 9s the first and second or inner and outer doping well regions 8th and 9 range from the surface area 2a ' the n-epitaxial layer up to the respective floor area 8b respectively. 9b , Between the first and second or inner or outer doping well regions 8th respectively. 9 is an n-doped material region of the n-epitaxial layer 2 ' as a gap area or distance range 31 intended.

In the surface area 2a of the drift area 2 inside the first or inner doping well 8th is the first semiconductor device 10 the first semiconductor device arrangement 10 ' a laterally formed IGBT provided with corresponding doping and terminal regions, which define via corresponding metallizations an anode A or a collector, a cathode K or an emitter or a corresponding gate G, the cathode K or the emitter and the gate electrode G via an n ^{+ region} 5 and a p-body area 4 whereas the anode A or the collector of the IGBT are arranged 10 above a p-region 6 is provided. This p-region for the anode terminal A or the collector terminal is embedded in an n-doped buffer layer 6n , Between the n-buffer 6 and the p-body area 5 is a combination of compensation layers or compensation layers 3n and 3p intended.

On the left side of the 1 is the so-called low-voltage range or the drive range and / or the low-side of the semiconductor circuit arrangement according to the invention 100 which of a sequence of second semiconductor devices 20 the second semiconductor devices 20 ' can be formed. This may be the sequence of PMOS, NMOS, PNP and / or NPN bipolar transistors as well as other active or passive devices commonly used in IC technologies. Shown here is a PMOS transistor for simplicity.

In the embodiment of the 1 are the sidewall areas 8s and 9s as sequences of doping regions and diffusion regions 8d respectively. 9d formed and arranged in the vertical direction.

2 shows you one 1 similar structure for another embodiment of the semiconductor circuit arrangement according to the invention 100 using the example of a high-side switch and a high-side control.

A difference to the embodiment of 1 is that instead of forming the sidewall areas 8s and 9s for the first and second doping regions 8th respectively. 9 no implantation and diffusion technique are used, but that here a trench 8t was provided with a corresponding filling.

Another difference to the embodiment of 1 is that on the left side of the 2 and the 1 lying drive range or the low-side of the semiconductor circuit arrangement according to the invention 100 also in a double tub insulation structure 30 is embedded. This is to ensure the voltage isolation of the illustrated high-side control against transient over or under voltages. To save space, the two adjacent twin tub structures 30 the first and the second semiconductor device arrangement 10 ' and 20 ' with respect to their outer doping well areas 9 a common sidewall area 9s on, so that the first and the second semiconductor device arrangement 10 ' respectively. 20 ' to achieve a particularly high integration density can be formed particularly close to each other.

LIST OF REFERENCE NUMBERS

1

Semiconductor substrate region, p ⁺ substrate

2

Drift area, n epitaxial layer

2a

surface area

2 '

Material area, n-epitaxial layer

2a

surface area

3n

n-balancing layer

3p

p-well region

4

p-body region

5

n ⁺ area

6

p-type region

6n

buffer layer

8th

first doping well area, p ⁺ tub

8b

floor area

8d

diffusion regions

8s

Sidewall region

8t

trench structures

9

second doping well region, n ⁺ well

9b

floor area

9d

diffusion regions

9s

Sidewall region

9t

trench structures

10

first semiconductor device

10 '

first semiconductor device arrangement

20

second semiconductor device

20 '

second semiconductor device arrangement

30

Double well isolation structure

31

Gap area, distance range

100

integrated semiconductor device arrangement

A

Annode, collector

G

gate

K

Cathode, emitter

Ia

Low-side switch, z. B. IGBT with freewheeling diode

ib

Low-side control, low-voltage components such. B. from conventional IC technologies

IIa

High-side switch, z. B. IGBT with freewheeling diode

IIb

High-side control, low-voltage components, such as B. from conventional IC technologies

III

Load, usually an inductive load z. B. an engine

Claims (15)

Integrated semiconductor circuit arrangement having at least one at least one semiconductor component ( 10 . 20 ) semiconductor device arrangement ( 10 ' . 20 ' ) associated with a drift area ( 2 ) in a semiconductor substrate ( 1 ) is provided, wherein between the drift area ( 2 ) and the semiconductor substrate ( 1 ) for electrical isolation of the respective semiconductor device arrangement ( 10 ' . 20 ' ) and / or the respective semiconductor components ( 10 . 20 ) a double-well insulation structure ( 30 ) with a first or inner doping well region ( 8th ) and with a second or outer doping well region ( 9 ), the sequence of the line types of the drift region ( 2 ), the adjoining inner doping well region ( 8th ), of the adjoining outer doping well region ( 9 ) and the adjoining semiconductor substrate region ( 1 ) alternately formed between a first conductivity type and a second conductivity type and the two doping well regions ( 8th . 9 ) are significantly higher doped than the drift region ( 2 ) and the semiconductor substrate ( 1 ), between the doping well regions ( 8th . 9 ) a semiconductor device arrangement ( 10 ' . 20 ' ) of the same material as the drift area ( 2 ) or with the same doping material as the semiconductor substrate ( 1 ) doped gap area ( 31 ) is provided such that the doping well regions ( 8th . 9 ) do not touch directly, Integrated semiconductor circuit arrangement according to Claim 1, characterized, that the first conductivity type is an n-type and that the second conductivity type is a p-type. Integrated semiconductor circuit arrangement according to Claim 1, characterized, that the first conductivity type is a p-type and that the second conductivity type is an n-type. Integrated semiconductor circuit arrangement according to one of the preceding claims, characterized in that the doping well regions ( 8th . 9 ) each have a floor area ( 8b . 9b ) and sidewall areas ( 8s . 9s ) exhibit. Integrated semiconductor circuit arrangement according to Claim 4, characterized in that the bottom region ( 8b . 9b ) is formed in each case as a buried layer. Integrated semiconductor circuit arrangement according to Claim 4 or 5, characterized in that sidewall regions ( 8s . 9s ) are formed as a sequence of implantation and / or diffusion regions. Integrated semiconductor circuit arrangement according to Claim 4 or 5, characterized in that sidewall regions ( 8s . 9s ) are formed as a sequence corresponding to filled and / or out-diffused trench or trench structures. Integrated semiconductor circuit arrangement according to one of the preceding claims, characterized in that the drift region ( 2 ) and / or the semiconductor substrate region ( 1 ) are formed comparatively low doped. Integrated semiconductor circuit arrangement according to one of the preceding claims, characterized in that a first semiconductor component arrangement ( 10 ' ) and a second semiconductor device arrangement ( 20 ' ) and in particular that the first semiconductor device arrangement ( 10 ' ) a switch, high-side and / or high-voltage region and / or the second semiconductor device arrangement ( 20 ' ) a drive, low-side and / or low-voltage region of the semiconductor integrated circuit device ( 100 ) or at least partially form them. Integrated semiconductor circuit arrangement according to one of the preceding claims, characterized in that directly adjacent semiconductor component arrangements ( 10 ' . 20 ' ) with respect to their outer doping well regions ( 9 ) at least one common sidewall region ( 9s ) exhibit. Integrated semiconductor circuit arrangement according to one of the preceding claims, characterized in that a switch and / or high-side region of the semiconductor circuit arrangement ( 100 ) assigned first semiconductor device arrangement ( 10 ' ) as at least one semiconductor device ( 10 ) and in particular as at least one high-voltage and / or high-injection semiconductor component ( 10 ) has an IGBT, a bipolar transistor, a MOS transistor and / or the like, in particular in a lateral construction. Integrated semiconductor circuit arrangement according to one of the preceding claims, characterized in that one of a drive and / or low-side region of the semiconductor circuit arrangement ( 100 ) assigned to semiconductor device assembly ( 20 ' ) as at least one semiconductor device ( 20 ) and in particular as at least one low-voltage component ( 20 ) identifies a bipolar transistor, a MOS transistor and / or the like, in particular in lateral construction. Integrated semiconductor circuit arrangement according to one of the preceding claims, characterized in that the outer doping well region ( 9 ) not contacted, in particular is designed to float. Integrated semiconductor circuit arrangement according to one of the preceding claims, characterized in that provided low-side components and high-side components, in particular low-side and high-side switches and / or -Ansteuerungen are monolithically integrated on a common chip. Integrated semiconductor circuit arrangement according to one of the preceding claims, characterized in that the first and the second doping well region ( 8th . 9 ) are formed comparatively highly doped.

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