DE102014103183A1 - Aufzeichnungspuffer-basiertes, dynamisches Checkpointing zum Wiederherstellen einer Umbenennungstabelle - Google Patents
Aufzeichnungspuffer-basiertes, dynamisches Checkpointing zum Wiederherstellen einer Umbenennungstabelle Download PDFInfo
- Publication number
- DE102014103183A1 DE102014103183A1 DE102014103183.0A DE102014103183A DE102014103183A1 DE 102014103183 A1 DE102014103183 A1 DE 102014103183A1 DE 102014103183 A DE102014103183 A DE 102014103183A DE 102014103183 A1 DE102014103183 A1 DE 102014103183A1
- Authority
- DE
- Germany
- Prior art keywords
- rename
- data
- rob
- cpt
- checkpoint
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/22—Microcontrol or microprogram arrangements
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
- G06F9/384—Register renaming
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
- G06F9/3856—Reordering of instructions, e.g. using queues or age tags
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
- G06F9/3863—Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Retry When Errors Occur (AREA)
- Advance Control (AREA)
- Executing Machine-Instructions (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/831,488 | 2013-03-14 | ||
| US13/831,488 US9448799B2 (en) | 2013-03-14 | 2013-03-14 | Reorder-buffer-based dynamic checkpointing for rename table rebuilding |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE102014103183A1 true DE102014103183A1 (de) | 2014-09-18 |
| DE102014103183A8 DE102014103183A8 (de) | 2014-11-13 |
Family
ID=51419101
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE102014103183.0A Pending DE102014103183A1 (de) | 2013-03-14 | 2014-03-11 | Aufzeichnungspuffer-basiertes, dynamisches Checkpointing zum Wiederherstellen einer Umbenennungstabelle |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP6399772B2 (https=) |
| KR (1) | KR102010317B1 (https=) |
| CN (1) | CN104050027B (https=) |
| DE (1) | DE102014103183A1 (https=) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9448800B2 (en) * | 2013-03-14 | 2016-09-20 | Samsung Electronics Co., Ltd. | Reorder-buffer-based static checkpointing for rename table rebuilding |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5630149A (en) * | 1993-10-18 | 1997-05-13 | Cyrix Corporation | Pipelined processor with register renaming hardware to accommodate multiple size registers |
| WO1996025705A1 (en) * | 1995-02-14 | 1996-08-22 | Fujitsu Limited | Structure and method for high-performance speculative execution processor providing special features |
| JP2000285082A (ja) * | 1999-03-31 | 2000-10-13 | Toshiba Corp | 中央演算装置及びコンパイル方法 |
| US6742112B1 (en) * | 1999-12-29 | 2004-05-25 | Intel Corporation | Lookahead register value tracking |
| US6629233B1 (en) * | 2000-02-17 | 2003-09-30 | International Business Machines Corporation | Secondary reorder buffer microprocessor |
| US20060149931A1 (en) * | 2004-12-28 | 2006-07-06 | Akkary Haitham | Runahead execution in a central processing unit |
| US20070043934A1 (en) * | 2005-08-22 | 2007-02-22 | Intel Corporation | Early misprediction recovery through periodic checkpoints |
| US7747841B2 (en) * | 2005-09-26 | 2010-06-29 | Cornell Research Foundation, Inc. | Method and apparatus for early load retirement in a processor system |
| US7809926B2 (en) * | 2006-11-03 | 2010-10-05 | Cornell Research Foundation, Inc. | Systems and methods for reconfiguring on-chip multiprocessors |
| JP5547208B2 (ja) * | 2008-11-24 | 2014-07-09 | インテル コーポレイション | シーケンシャル・プログラムを複数スレッドに分解し、スレッドを実行し、シーケンシャルな実行を再構成するシステム、方法および装置 |
| US9052890B2 (en) * | 2010-09-25 | 2015-06-09 | Intel Corporation | Execute at commit state update instructions, apparatus, methods, and systems |
-
2013
- 2013-12-20 KR KR1020130160343A patent/KR102010317B1/ko active Active
-
2014
- 2014-03-11 DE DE102014103183.0A patent/DE102014103183A1/de active Pending
- 2014-03-13 JP JP2014050469A patent/JP6399772B2/ja active Active
- 2014-03-14 CN CN201410097569.4A patent/CN104050027B/zh active Active
Non-Patent Citations (1)
| Title |
|---|
| IEEE 802.20 |
Also Published As
| Publication number | Publication date |
|---|---|
| DE102014103183A8 (de) | 2014-11-13 |
| JP6399772B2 (ja) | 2018-10-03 |
| JP2014179096A (ja) | 2014-09-25 |
| CN104050027A (zh) | 2014-09-17 |
| CN104050027B (zh) | 2018-11-27 |
| KR102010317B1 (ko) | 2019-08-13 |
| KR20140113305A (ko) | 2014-09-24 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| R409 | Internal rectification of the legal status completed | ||
| R409 | Internal rectification of the legal status completed | ||
| R012 | Request for examination validly filed |