CN104050027B - 用于重命名表重建基于重新排序缓冲区的动态检查点设置 - Google Patents

用于重命名表重建基于重新排序缓冲区的动态检查点设置 Download PDF

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Publication number
CN104050027B
CN104050027B CN201410097569.4A CN201410097569A CN104050027B CN 104050027 B CN104050027 B CN 104050027B CN 201410097569 A CN201410097569 A CN 201410097569A CN 104050027 B CN104050027 B CN 104050027B
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CN
China
Prior art keywords
rename
rob
data
cpt
checkpoint
Prior art date
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Active
Application number
CN201410097569.4A
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English (en)
Chinese (zh)
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CN104050027A (zh
Inventor
R.伊恩加
P.桑萨纳克里什南
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication date
Priority claimed from US13/831,488 external-priority patent/US9448799B2/en
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CN104050027A publication Critical patent/CN104050027A/zh
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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3856—Reordering of instructions, e.g. using queues or age tags
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3863—Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Retry When Errors Occur (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
CN201410097569.4A 2013-03-14 2014-03-14 用于重命名表重建基于重新排序缓冲区的动态检查点设置 Active CN104050027B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/831,488 2013-03-14
US13/831,488 US9448799B2 (en) 2013-03-14 2013-03-14 Reorder-buffer-based dynamic checkpointing for rename table rebuilding

Publications (2)

Publication Number Publication Date
CN104050027A CN104050027A (zh) 2014-09-17
CN104050027B true CN104050027B (zh) 2018-11-27

Family

ID=51419101

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410097569.4A Active CN104050027B (zh) 2013-03-14 2014-03-14 用于重命名表重建基于重新排序缓冲区的动态检查点设置

Country Status (4)

Country Link
JP (1) JP6399772B2 (https=)
KR (1) KR102010317B1 (https=)
CN (1) CN104050027B (https=)
DE (1) DE102014103183A1 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9448800B2 (en) * 2013-03-14 2016-09-20 Samsung Electronics Co., Ltd. Reorder-buffer-based static checkpointing for rename table rebuilding

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5630149A (en) * 1993-10-18 1997-05-13 Cyrix Corporation Pipelined processor with register renaming hardware to accommodate multiple size registers
CN100485607C (zh) * 2004-12-28 2009-05-06 英特尔公司 中央处理单元中的提前执行的方法和系统
CN102171650A (zh) * 2008-11-24 2011-08-31 英特尔公司 用于将顺序程序分解为多个线程、执行所述线程和重构该顺序执行的系统、方法和装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996025705A1 (en) * 1995-02-14 1996-08-22 Fujitsu Limited Structure and method for high-performance speculative execution processor providing special features
JP2000285082A (ja) * 1999-03-31 2000-10-13 Toshiba Corp 中央演算装置及びコンパイル方法
US6742112B1 (en) * 1999-12-29 2004-05-25 Intel Corporation Lookahead register value tracking
US6629233B1 (en) * 2000-02-17 2003-09-30 International Business Machines Corporation Secondary reorder buffer microprocessor
US20070043934A1 (en) * 2005-08-22 2007-02-22 Intel Corporation Early misprediction recovery through periodic checkpoints
US7747841B2 (en) * 2005-09-26 2010-06-29 Cornell Research Foundation, Inc. Method and apparatus for early load retirement in a processor system
US7809926B2 (en) * 2006-11-03 2010-10-05 Cornell Research Foundation, Inc. Systems and methods for reconfiguring on-chip multiprocessors
US9052890B2 (en) * 2010-09-25 2015-06-09 Intel Corporation Execute at commit state update instructions, apparatus, methods, and systems

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5630149A (en) * 1993-10-18 1997-05-13 Cyrix Corporation Pipelined processor with register renaming hardware to accommodate multiple size registers
CN100485607C (zh) * 2004-12-28 2009-05-06 英特尔公司 中央处理单元中的提前执行的方法和系统
CN102171650A (zh) * 2008-11-24 2011-08-31 英特尔公司 用于将顺序程序分解为多个线程、执行所述线程和重构该顺序执行的系统、方法和装置

Also Published As

Publication number Publication date
DE102014103183A8 (de) 2014-11-13
JP6399772B2 (ja) 2018-10-03
JP2014179096A (ja) 2014-09-25
CN104050027A (zh) 2014-09-17
KR102010317B1 (ko) 2019-08-13
KR20140113305A (ko) 2014-09-24
DE102014103183A1 (de) 2014-09-18

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