DE102013100062A8 - Verfahren zum Entwerfen eines Ein-Chip-Systems mit einer Tapless-Standardzelle, Entwurfssystem und Ein-Chip-System - Google Patents
Verfahren zum Entwerfen eines Ein-Chip-Systems mit einer Tapless-Standardzelle, Entwurfssystem und Ein-Chip-System Download PDFInfo
- Publication number
- DE102013100062A8 DE102013100062A8 DE102013100062A DE102013100062A DE102013100062A8 DE 102013100062 A8 DE102013100062 A8 DE 102013100062A8 DE 102013100062 A DE102013100062 A DE 102013100062A DE 102013100062 A DE102013100062 A DE 102013100062A DE 102013100062 A8 DE102013100062 A8 DE 102013100062A8
- Authority
- DE
- Germany
- Prior art keywords
- tapeless
- designing
- cell
- standard
- tap
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3315—Design verification, e.g. functional simulation or model checking using static timing analysis [STA]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/31—Design entry, e.g. editors specifically adapted for circuit design
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
- G06F30/3312—Timing analysis
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2115/00—Details relating to the type of the circuit
- G06F2115/02—System on chip [SoC] design
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
- G06F2119/12—Timing analysis or timing optimisation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Geometry (AREA)
- Evolutionary Computation (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2012-0004714 | 2012-01-16 | ||
| KR1020120004714A KR20130084029A (ko) | 2012-01-16 | 2012-01-16 | 탭리스 스탠다드 셀을 포함하는 시스템-온-칩의 설계 방법, 설계 시스템 및 시스템-온-칩 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE102013100062A1 DE102013100062A1 (de) | 2013-07-18 |
| DE102013100062A8 true DE102013100062A8 (de) | 2013-09-19 |
Family
ID=48693322
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE102013100062A Withdrawn DE102013100062A1 (de) | 2012-01-16 | 2013-01-07 | Verfahren zum Entwerfen eines Ein-Chip-Systems mit einer Tapless-Standardzelle, Entwurfssystem und Ein-Chip-System |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US8522188B2 (de) |
| JP (1) | JP2013145550A (de) |
| KR (1) | KR20130084029A (de) |
| CN (1) | CN103207930B (de) |
| DE (1) | DE102013100062A1 (de) |
| TW (1) | TWI560543B (de) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102187640B1 (ko) | 2014-10-22 | 2020-12-08 | 삼성전자주식회사 | 타이밍 분석기의 타이밍 정합 방법 및 그것을 이용한 집적회로 설계 방법 |
| US9280630B1 (en) | 2014-11-07 | 2016-03-08 | International Business Machines Corporation | Modified standard cells to address fast paths |
| US9646123B2 (en) * | 2014-12-31 | 2017-05-09 | Texas Instruments Incorporated | Standard cell design with reduced cell delay |
| KR102324782B1 (ko) * | 2015-01-22 | 2021-11-11 | 삼성전자주식회사 | 집적 회로의 정적 타이밍 분석 방법 |
| US9842184B2 (en) * | 2015-09-11 | 2017-12-12 | Globalfoundries Inc. | Method, apparatus and system for using hybrid library track design for SOI technology |
| KR20180092692A (ko) * | 2017-02-10 | 2018-08-20 | 삼성전자주식회사 | Beol을 고려하여 집적 회로를 설계하기 위한 컴퓨터 구현 방법 및 컴퓨팅 시스템 |
| CN108647390B (zh) * | 2018-01-31 | 2022-04-22 | 深圳大学 | 标准单元库设计方法、设计装置、标准单元库和cmos图像传感芯片 |
| TWI722360B (zh) * | 2018-11-13 | 2021-03-21 | 大陸商創意電子（南京）有限公司 | 測試系統與測試方法 |
| US10868526B2 (en) * | 2018-12-14 | 2020-12-15 | Nxp Usa, Inc. | Synchronizer with controlled metastability characteristics |
| KR102157355B1 (ko) * | 2019-04-23 | 2020-09-18 | 삼성전자 주식회사 | 표준 셀들을 포함하는 집적 회로, 이를 제조하기 위한 방법 및 컴퓨팅 시스템 |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6300819B1 (en) * | 1997-06-20 | 2001-10-09 | Intel Corporation | Circuit including forward body bias from supply voltage and ground nodes |
| WO1998059419A1 (en) * | 1997-06-20 | 1998-12-30 | Intel Corporation | Forward body bias transistor circuits |
| US6966022B1 (en) * | 2002-04-04 | 2005-11-15 | Adaptec, Inc. | System and method for determining integrated circuit logic speed |
| US7116705B2 (en) * | 2004-11-08 | 2006-10-03 | Interdigital Technology Corporation | Method and apparatus for reducing the processing rate of a chip-level equalization receiver |
| CN101416408A (zh) * | 2004-11-08 | 2009-04-22 | 美商内数位科技公司 | 降低晶片级等化器接收器处理速率的方法及装置 |
| JP2008153415A (ja) | 2006-12-18 | 2008-07-03 | Renesas Technology Corp | 半導体集積回路およびその製造方法 |
| JP2008182004A (ja) | 2007-01-24 | 2008-08-07 | Renesas Technology Corp | 半導体集積回路 |
| US7868667B2 (en) | 2008-03-26 | 2011-01-11 | Hynix Semiconductor Inc. | Output driving device |
| KR100996193B1 (ko) | 2008-03-26 | 2010-11-24 | 주식회사 하이닉스반도체 | 출력 드라이빙장치 |
| US8255851B1 (en) * | 2008-06-24 | 2012-08-28 | Marvell Israel (M.I.S.L) Ltd. | Method and system for timing design |
| KR20120004714A (ko) | 2010-07-07 | 2012-01-13 | 이상민 | 회전 조절이 가능한 선풍기 |
| WO2012037544A1 (en) * | 2010-09-17 | 2012-03-22 | Marvell World Trade, Ltd. | Method and apparatus for timing closure |
| US8332802B2 (en) * | 2010-10-25 | 2012-12-11 | Avago Technologies Enterprise IP (Singapore) Pte. Ltd. | Systems, methods, and programs for leakage power and timing optimization in integrated circuit designs |
-
2012
- 2012-01-16 KR KR1020120004714A patent/KR20130084029A/ko not_active Application Discontinuation
- 2012-09-25 US US13/626,121 patent/US8522188B2/en active Active
- 2012-10-31 TW TW101140326A patent/TWI560543B/zh active
- 2012-11-08 JP JP2012246472A patent/JP2013145550A/ja active Pending
-
2013
- 2013-01-07 DE DE102013100062A patent/DE102013100062A1/de not_active Withdrawn
- 2013-01-16 CN CN201310014808.0A patent/CN103207930B/zh active Active
Also Published As
| Publication number | Publication date |
|---|---|
| TW201331746A (zh) | 2013-08-01 |
| KR20130084029A (ko) | 2013-07-24 |
| US20130185692A1 (en) | 2013-07-18 |
| JP2013145550A (ja) | 2013-07-25 |
| TWI560543B (en) | 2016-12-01 |
| DE102013100062A1 (de) | 2013-07-18 |
| CN103207930B (zh) | 2017-10-13 |
| CN103207930A (zh) | 2013-07-17 |
| US8522188B2 (en) | 2013-08-27 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| R012 | Request for examination validly filed | ||
| R079 | Amendment of ipc main class |
Free format text: PREVIOUS MAIN CLASS: G06F0017500000 Ipc: G06F0030000000 |
|
| R119 | Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee |