DE102007057222A1 - Isolated gate transistor - Google Patents
Isolated gate transistor Download PDFInfo
- Publication number
- DE102007057222A1 DE102007057222A1 DE102007057222A DE102007057222A DE102007057222A1 DE 102007057222 A1 DE102007057222 A1 DE 102007057222A1 DE 102007057222 A DE102007057222 A DE 102007057222A DE 102007057222 A DE102007057222 A DE 102007057222A DE 102007057222 A1 DE102007057222 A1 DE 102007057222A1
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- Germany
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- trenches
- source
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- base layer
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- 239000004065 semiconductor Substances 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 230000015556 catabolic process Effects 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- BUHVIAUBTBOHAG-FOYDDCNASA-N (2r,3r,4s,5r)-2-[6-[[2-(3,5-dimethoxyphenyl)-2-(2-methylphenyl)ethyl]amino]purin-9-yl]-5-(hydroxymethyl)oxolane-3,4-diol Chemical compound COC1=CC(OC)=CC(C(CNC=2C=3N=CN(C=3N=CN=2)[C@H]2[C@@H]([C@H](O)[C@@H](CO)O2)O)C=2C(=CC=CC=2)C)=C1 BUHVIAUBTBOHAG-FOYDDCNASA-N 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
- H01L29/0834—Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Eine Ladungsspeicherschicht (12) eines ersten Leitungstyps ist auf der ersten Hauptoberfläche eines Halbleitersubstrates (11) ausgebildet. Eine Basisschicht (13) des zweiten Leitungstyps ist auf der Ladungsspeicherschicht (12) ausgebildet. Jeder Graben (14), der durch die Basisschicht (13) und die Ladungsspeicherschicht (12) hindurch ausgebildet ist, ist mit einem isolierenden Film (15) ausgekleidet und mit einer Graben-Gate-Elektrode (16) ausgefüllt. Dummy-Gräben (17) sind auf beiden Seiten jedes Grabens (14) ausgebildet. Sourceschichten (21) des ersten Leitungstyps sind selektiv in der Oberfläche der Basisschicht (13) und in Kontakt mit den Seitenwänden der Gräben (14) ausgebildet. Die Sourceschichten (21) sind voneinander beabstandet und entlang der Längsrichtung der Gräben (14) angeordnet. Eine Kontaktschicht (22) des zweiten Leitungstyps ist in der Oberfläche der Basisschicht (13) und zwischen jeweils zwei benachbarten Sourceschichten (21), die entlang der Längsrichtung der Gräben (14) angeordnet sind, ausgebildet. Eine Kollektorschicht (24) des zweiten Leitungstyps ist auf der zweiten Hauptoberfläche des Halbleitersubstrates (11) ausgebildet.A Charge storage layer (12) of a first conductivity type is on first main surface of a semiconductor substrate (11) educated. A base layer (13) of the second conductivity type is formed on the charge storage layer (12). Each trench (14), the through the base layer (13) and the charge storage layer (12) is formed through, is lined with an insulating film (15) and filled with a trench gate electrode (16). Dummy trenches (17) are formed on both sides of each trench (14). source layers (21) of the first conductivity type are selectively in the surface the base layer (13) and in contact with the side walls the trenches (14) formed. The source stories (21) are spaced apart and along the longitudinal direction of the Trenches (14) arranged. A contact layer (22) of the second Conductivity type is in the surface of the base layer (13) and between each two adjacent source layers (21), the arranged along the longitudinal direction of the trenches (14) are, trained. A collector layer (24) of the second conductivity type is on the second main surface of the semiconductor substrate (11) educated.
Description
Die vorliegende Erfindung bezieht sich auf Transistoren mit isoliertem Gate, die zum Ausbilden eines Wechselrichters, etc. verwendet werden, und spezieller auf Transistoren mit isoliertem Gate, die so ausgelegt sind, dass sie im Kurzschlussmodus eine verringerte Schwankung im Strom zeigen und eine hinreichende Widerstandsfähigkeit gegenüber einem elektrischen Durchbruch aufweisen.The The present invention relates to insulated-type transistors Gate used to form an inverter, etc. and more particularly to insulated gate transistors designed in this way are that they have a reduced fluctuation in the short circuit mode Show current and sufficient resistance have an electrical breakdown.
Zum
Verringern des Stroms in einem Kurzschlussmodus und zur Verhinderung
eines elektrischen Durchbruchs gibt es einen Typ eines Bipolartransistors
mit isoliertem Gate (IGBT) mit einer Graben-Gate-Struktur, welcher
Dummy-Gräben (welche nicht einen Teil der Kanäle
bilden) aufweist (siehe z. B.
Somit
sind in bekannten Transistoren mit isoliertem Gate die Sourceschichten
Die vorliegende Erfindung wurde gemacht zum Lösen der obigen Probleme. Es ist deshalb eine Aufgabe der vorliegenden Erfindung, einen Transistor mit isoliertem Gate bereitzustellen, der so ausgelegt ist, dass er eine verringerte Schwankung des Stroms in seinem Kurzschlussmodus zeigt und eine hinreichende Widerstandsfähigkeit gegenüber einem elektrischen Durchbruch aufweist.The The present invention has been made for solving the above Problems. It is therefore an object of the present invention To provide an insulated gate transistor designed so is that he has a reduced fluctuation of the current in his short circuit mode shows and a sufficient resistance to having an electrical breakdown.
Die Aufgabe wird gelöst durch einen Transistor mit isoliertem Gate gemäß Anspruch 1.The Task is solved by a transistor with insulated Gate according to claim 1.
Weiterbildungen der Erfindung sind in den Unteransprüchen beschrieben.further developments The invention are described in the subclaims.
Gemäß eines Aspektes der vorliegenden Erfindung ist eine Ladungsspeicherschicht des ersten Leitungstyps auf der ersten Hauptoberfläche eines Halbleitersubstrates ausgebildet. Eine Basisschicht des zweiten Leitungstyps ist auf der Ladungsspeicherschicht ausgebildet. Jeder Graben, der durch die Basis schicht und die Ladungsspeicherschicht hindurch ausgebildet ist, ist mit einem isolierenden Film überzogen und mit einer Graben-Gateelektrode ausgefüllt. Dummy-Gräben sind auf beiden Seiten jedes Grabens ausgebildet. Sourceschichten des ersten Leitungstyps sind an einzelnen Stellen in der Oberfläche der Basisschicht und in Kontakt zu den Seitenwänden der Gräben ausgebildet. Die Sourceschichten sind voneinander beabstandet und entlang der Längsrichtung der Gräben angeordnet. Eine Kontaktschicht des zweiten Leitungstyps ist in der Oberfläche der Basisschicht und zwischen jeweils zwei an sie angrenzenden Sourceschichten entlang der Längsrichtung der Gräben angeordnet. Eine Kollektorschicht des zweiten Leitungstyps ist auf der zweiten Hauptoberfläche des Halbleitersubstrates ausgebildet.According to one Aspect of the present invention is a charge storage layer of the first conductivity type on the first main surface a semiconductor substrate formed. A base layer of the second Conduction type is formed on the charge storage layer. Everyone Digging through the base layer and the charge storage layer is formed through, is coated with an insulating film and filled with a trench gate electrode. Dummy trenches are formed on both sides of each trench. source layers of the first conductivity type are at individual points in the surface the base layer and in contact with the sidewalls of the Trained trenches. The source stories are from each other spaced and along the longitudinal direction of the trenches arranged. A contact layer of the second conductivity type is in the surface of the base layer and between each two Sourceschichten adjoining them along the longitudinal direction arranged the trenches. A collector layer of the second Conduction type is on the second main surface of the semiconductor substrate educated.
Somit ermöglicht die vorliegende Erfindung, dass ein Transistor mit isoliertem Gate eine verringerte Schwankung des Stroms in seinem Kurzschlussmodus zeigt und eine hinreichende Widerstandsfähigkeit gegenüber einem elektrischen Durchbruch aufweist.Consequently allows the present invention that a transistor with insulated gate a reduced variation of the current in his Short circuit mode shows and sufficient resistance has an electrical breakdown.
Weitere Merkmale und Zweckmäßigkeiten der Erfindung ergeben sich aus der Beschreibung von Ausführungsformen anhand der Zeichnungen. Von den Figuren zeigen:Further Features and benefits of the invention result from the description of embodiments based the drawings. From the figures show:
Erste AusführungsformFirst embodiment
Bezug
nehmend auf
Eine
Mehrzahl von Gräben
N+-Typ-Sourceschichten
Eine
n+-Typ-Pufferschicht
Somit
ist der Transistor mit isoliertem Gate der vorliegenden Ausführungsform
ein "Ladungsspeicher-Graben-IGBT", welcher die n-Typ-Ladungsspeicherschicht
Da
die n+-Typ-Sourceschichten
Weiterhin
sind gemäß der vorliegenden Ausführungsform
die Sourceschichten
Es
sollte bemerkt werden, dass die Abmessungen der Sourceschichten
Weiterhin
werden die Dummy-Graben-Gateelektroden
Weiterhin
beträgt die Breite Wch der Sourceschichten
Zweite AusführungsformSecond embodiment
ZITATE ENTHALTEN IN DER BESCHREIBUNGQUOTES INCLUDE IN THE DESCRIPTION
Diese Liste der vom Anmelder aufgeführten Dokumente wurde automatisiert erzeugt und ist ausschließlich zur besseren Information des Lesers aufgenommen. Die Liste ist nicht Bestandteil der deutschen Patent- bzw. Gebrauchsmusteranmeldung. Das DPMA übernimmt keinerlei Haftung für etwaige Fehler oder Auslassungen.This list The documents listed by the applicant have been automated generated and is solely for better information recorded by the reader. The list is not part of the German Patent or utility model application. The DPMA takes over no liability for any errors or omissions.
Zitierte PatentliteraturCited patent literature
- - JP 2002-16252 A [0002] - JP 2002-16252 A [0002]
Claims (5)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007064995A JP2008227251A (en) | 2007-03-14 | 2007-03-14 | Insulated gate transistor |
JP2007-064995 | 2007-03-14 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE102007057222A1 true DE102007057222A1 (en) | 2008-09-25 |
DE102007057222B4 DE102007057222B4 (en) | 2012-05-31 |
Family
ID=39713294
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE102007057222A Expired - Fee Related DE102007057222B4 (en) | 2007-03-14 | 2007-11-28 | Isolated gate transistor |
Country Status (4)
Country | Link |
---|---|
US (1) | US7675113B2 (en) |
JP (1) | JP2008227251A (en) |
KR (1) | KR100935165B1 (en) |
DE (1) | DE102007057222B4 (en) |
Cited By (1)
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---|---|---|---|---|
DE112013006666B4 (en) | 2013-02-13 | 2019-04-11 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device |
Families Citing this family (39)
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US7785946B2 (en) | 2007-09-25 | 2010-08-31 | Infineon Technologies Ag | Integrated circuits and methods of design and manufacture thereof |
JP4256901B1 (en) * | 2007-12-21 | 2009-04-22 | 株式会社豊田中央研究所 | Semiconductor device |
JP4688901B2 (en) * | 2008-05-13 | 2011-05-25 | 三菱電機株式会社 | Semiconductor device |
JP5216801B2 (en) | 2010-03-24 | 2013-06-19 | 株式会社東芝 | Semiconductor device |
JP5566272B2 (en) * | 2010-11-26 | 2014-08-06 | 三菱電機株式会社 | Semiconductor device |
US10249721B2 (en) | 2013-04-04 | 2019-04-02 | Infineon Technologies Austria Ag | Semiconductor device including a gate trench and a source trench |
US9666663B2 (en) | 2013-08-09 | 2017-05-30 | Infineon Technologies Ag | Semiconductor device with cell trench structures and contacts and method of manufacturing a semiconductor device |
US9076838B2 (en) | 2013-09-13 | 2015-07-07 | Infineon Technologies Ag | Insulated gate bipolar transistor with mesa sections between cell trench structures and method of manufacturing |
US9385228B2 (en) | 2013-11-27 | 2016-07-05 | Infineon Technologies Ag | Semiconductor device with cell trench structures and contacts and method of manufacturing a semiconductor device |
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JP6515484B2 (en) * | 2014-10-21 | 2019-05-22 | 株式会社デンソー | Semiconductor device |
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JPWO2016113865A1 (en) * | 2015-01-14 | 2017-07-13 | 三菱電機株式会社 | Semiconductor device and manufacturing method thereof |
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US10529839B2 (en) * | 2015-05-15 | 2020-01-07 | Fuji Electric Co., Ltd. | Semiconductor device |
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CN105226090B (en) | 2015-11-10 | 2018-07-13 | 株洲中车时代电气股份有限公司 | A kind of igbt and preparation method thereof |
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WO2018074425A1 (en) * | 2016-10-17 | 2018-04-26 | 富士電機株式会社 | Semiconductor device |
WO2018092787A1 (en) * | 2016-11-17 | 2018-05-24 | 富士電機株式会社 | Semiconductor device |
CN106783951B (en) * | 2016-12-23 | 2020-03-24 | 株洲中车时代电气股份有限公司 | Semiconductor device and forming method thereof |
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US10600867B2 (en) * | 2017-05-16 | 2020-03-24 | Fuji Electric Co., Ltd. | Semiconductor device having an emitter region and a contact region inside a mesa portion |
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US10388726B2 (en) * | 2017-10-24 | 2019-08-20 | Semiconductor Components Industries, Llc | Accumulation enhanced insulated gate bipolar transistor (AEGT) and methods of use thereof |
CN109192771B (en) * | 2018-08-29 | 2020-06-30 | 电子科技大学 | Charge storage type insulated gate bipolar transistor and preparation method thereof |
CN110504305B (en) * | 2019-08-06 | 2021-02-05 | 电子科技大学 | SOI-LIGBT device with self-biased pmos clamp carrier storage layer |
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JP7305589B2 (en) | 2020-03-19 | 2023-07-10 | 株式会社東芝 | Semiconductor devices and semiconductor circuits |
JP7459703B2 (en) * | 2020-07-15 | 2024-04-02 | 富士電機株式会社 | Semiconductor Device |
JP7320910B2 (en) * | 2020-09-18 | 2023-08-04 | 株式会社東芝 | Semiconductor device and its control method |
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JP4823435B2 (en) | 2001-05-29 | 2011-11-24 | 三菱電機株式会社 | Semiconductor device and manufacturing method thereof |
JP2004022941A (en) * | 2002-06-19 | 2004-01-22 | Toshiba Corp | Semiconductor device |
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JP4252039B2 (en) * | 2005-01-20 | 2009-04-08 | 株式会社日立国際電気 | Wireless base station equipment |
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-
2007
- 2007-03-14 JP JP2007064995A patent/JP2008227251A/en active Pending
- 2007-08-22 US US11/843,301 patent/US7675113B2/en not_active Expired - Fee Related
- 2007-11-28 DE DE102007057222A patent/DE102007057222B4/en not_active Expired - Fee Related
- 2007-11-30 KR KR1020070123240A patent/KR100935165B1/en not_active IP Right Cessation
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002016252A (en) | 2000-06-27 | 2002-01-18 | Toshiba Corp | Insulation gate type semiconductor element |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE112013006666B4 (en) | 2013-02-13 | 2019-04-11 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
KR100935165B1 (en) | 2010-01-06 |
KR20080086963A (en) | 2008-09-29 |
US7675113B2 (en) | 2010-03-09 |
US20080224207A1 (en) | 2008-09-18 |
JP2008227251A (en) | 2008-09-25 |
DE102007057222B4 (en) | 2012-05-31 |
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