DE102006008929A1 - Layer structure production for nitride semiconductor component on silicon surface, involves preparation of substrate having silicon surface on which nitride nucleation layer is deposited with masking layer - Google Patents

Abstract

The process involves the preparation of a substrate with a silicon surface on which a nitride nucleation layer is deposited which contains aluminum. A masking layer is deposited on the nitride nucleation layer or on a nitride buffer layer if it is present. The nitride buffer layer is present in such a manner that separate crystallites first inter-grow in the deposition step of the first nitride semiconductor layer, above a coalescence layer thickness, and cover an average surface of at least 0.16 mu m 2> in a layer plane of the nitride semiconductor layer perpendicularly to the direction of growth. Independent claims are also included for the following: (1) a nitride semiconductor component which has gallium containing a nitride semiconductor layer; (2) a carrier disk with multiple nitride semiconductor components; and (3) a nitride semiconductor product with a substrate.

Description

The The present invention relates to a process for the preparation of a Layer structure of a nitride semiconductor device on a silicon surface. Farther The invention relates to a method for producing a nitride semiconductor device. After all The invention relates to a nitride semiconductor device, in particular a thin film light emitting diode nitride semiconductor base, as well as a nitride semiconductor product.

nitride are semiconductor compounds that contain one or more elements of the third Main group and one or more elements of the fifth main group of the periodic table. They include, for example, the semiconductors GaN, InGaN, InGaAsN, AlGaN, etc. Other common names for nitride semiconductors For the purposes of the present application are group III nitrides, III-V nitrides. These terms will coexist in the present application used with the same meaning.

nitride find particular application in light emitting structures, which are used in the emit visible and ultraviolet spectral range. Next to it are Also known electronic nitride semiconductor devices, such as HEM (high electron mobility) transistors, in particular for high frequency applications such as in radio transmission technology are suitable. Nitride semiconductor devices find in the form of so-called "Power Devices "also in the high performance electronics application.

Cost-effective homoepitaxy of the layer structure of a nitride semiconductor component is currently of little commercial interest due to the small size and quality of available substrates made of nitride semiconductors. Thus, available nitride semiconductor devices, such as blue or green LEDs, include layered structures deposited on sapphire (Al ₂ O ₃ ) or silicon carbide (SiC) substrates. These substrate materials have several disadvantages. For one thing, they are expensive. On the other hand, common substrates of these materials are comparatively small, so that the production costs per component are additionally increased due to the relatively low yield for a given substrate area. Added to this is the high hardness of these materials, which is above 9 on the Mohs scale and enables machining only with expensive diamond saws and abrasive materials.

Therefore be for a large-scale growth reinforced Silicon substrates used, which are known to be of large diameter are available inexpensively.

typical Growth temperatures for the layer structures of nitride semiconductors are in the commercially usual Gas phase epitaxy at temperatures above 1,000 ° C. Different thermal Expansion coefficients of silicon and nitride semiconductor materials to lead then deposited on cooling Nitride semiconductor layer structures after growth to a strong Tensile stress of the nitride semiconductor layers of about 0.7 GPa / μm and from Layer thicknesses of less than 1 micron to Cracking.

to Prevent cracking during the growth of GaN layers Silicon becomes thin, at unusual low temperatures (below 1000 ° C) grown, so-called low-temperature AlN or AlGaN intermediate layers used. The effect of these layers is based on a partial Compensa tion of the tensile stress by growth of a GaN layer with compressive stress on the AlN or AlGaN interlayer. At the cooling down After layer deposition, this compressive stress of the GaN layer due to the different thermal expansion coefficients caused tensile stress and results in a reduced Tensile stress.

Disadvantage of this technique is a high dislocation density in the growing on the intermediate layer GaN layer. In the DE 101 51 092 A1 , which is hereby incorporated by reference into the disclosure of the present application, therefore, to reduce the dislocation density, additional insertion of silicon nitride interlayers into the growing GaN layer is proposed. A not necessarily completely closed Si _x N _y interlayer serves as a mask for subsequent growth of GaN. The thickness of the intermediate layer is determined according to DE 101 51 092 A1 chosen so that only a few growth islands at a distance of 100 nm to a few microns, which have grown together in the further course of growth with increasing distance of the growth surface of the SiN intermediate layer from a so-called Koaleszenzdicke and form a closed layer surface. It is true that only a SiN intermediate layer in GaN epitaxy on silicon causes marked island growth and thus a significant coalescence thickness, which increases with increasing SiN thickness. By taking appropriate measures to accelerate the coalescence of these growth islands, however, it can be prevented that the mentioned critical crack thickness is already reached before the growth islands coalesce.

From the document A. Dadgar et al., "Reduction of Stress at the Initial Stages of GaN Growth on Si (III)", Applied Physics Letters, Vol. 82, 2003, No. 1, Pages 28-30, (hereinafter "Dadgar et al."), Which is hereby incorporated by reference into the disclosure of the present application, it is also known to deposit GaN layers after deposition of a silicon-doped AlN seed layer and a SiN layer. In contrast to growth without such a SiN masking layer, the tensile stress in the growing GaN layer can be reduced.

This Effect shows as a function of SiN masking layer thickness above a certain thickness saturation phenomena and lets not complete stress compensation expect. For one thing, the SiN masking layer can increase with increasing Thickness the structural coupling between the AlN seed layer and the following (ie after the SiN masking layer) interfere with the growing GaN layer or even prevent. As a result, then a desired compressive effect the AlN seeding layer no longer enter and it remains one undesirable high tensile stress in the finished nitride semiconductor layer. On the other hand increases a thick SiN layer the coalescence thickness to values consistent with the known methods no longer below the cracking critical layer thickness can be held.

in the The result can also be the insertion of a SiN masking layer the tensile stress in the nitride semiconductor layer structure not remove.

inhomogeneous Tensile stress has other disadvantages. He causes next to the already mentioned high dislocation density and a curvature of the growing layer structure and the underlying substrate. This problem also affects thin-film devices, like thin film light emitting diodes, where the silicon substrate is removed in the course of manufacture becomes. Already the processing of curved nitride semiconductor layer structures prepares Difficulties and increases therefore, effort and cost of component manufacturing. A curved nitride semiconductor layer structure, which is then typically connected to a carrier dissolves light from the carrier, and corresponding components have an undesirably low life.

Out Document C. Mo et al., "Growth and characterization of InGaN blue LED structure on Si (III) by MOCVD ", Journal of Crystal Growth, 285 (2005), 312-317 (hereafter "Mo et al.) hereby incorporated by reference into the disclosure of the present application Registration is known, it is known the tensile stress through Growth of a GaN buffer layer on the AlN seed layer to reduce. It is for the growth of the GaN buffer layer in the high-temperature gas phase epitaxy low ratio the gas flow densities of gallium precursor to nitrogen precursor set. This promotes the island growth of the subsequent GaN layer. The disadvantage is in this case, however, that furthermore tensile stress in the nitride semiconductor layer structure remains. additionally this known light-emitting diode is undesirably high-impedance.

The the technical problem underlying the present invention it is therefore a method for producing a layered structure a nitride semiconductor device on a silicon surface and to provide a nitride semiconductor device in which the tensile stress in the finished layer structure over known solutions on is reduced.

One Another of the present invention underlying technical Problem is, a method for producing a layered structure a nitride semiconductor device on a silicon surface and To specify a nitride semiconductor device, which the curvature of the Reduced nitride semiconductor layer structure over prior art solutions.

• – Bereitstellen eines Substrats, das eine Siliziumoberfläche hat;
• – Abscheiden einer aluminiumhaltigen Nitridankeimschicht auf der Siliziumoberfläche des Substrats;
• – Optional: Abscheiden einer aluminiumhaltigen Nitridpufferschicht auf der Nitridankeimschicht;
• – Abscheiden einer Maskierungsschicht auf der Nitridankeimschicht oder, wenn vorhanden, auf der ersten Nitridpufferschicht;
• – Abscheiden einer galliumhaltigen ersten Nitridhalbleiterschicht auf der Maskierungsschicht,

wobei die Maskierungsschicht derart abgeschieden wird, dass im Abscheideschritt der ersten Nitridhalbleiterschicht zunächst getrennte Kristallite wachsen, die oberhalb einer Koaleszenzschichtdicke zusammenwachsen und in einer Schichtebene der zusammengewachsenen Nitridhalbleiterschicht senkrecht zur Wachstumsrichtung eine durchschnittliche Fläche von mindestens 0,16 μm² einnehmen.According to a first aspect of the invention, the stated technical problems are solved by a method for producing a layer structure of a nitride semiconductor component on a silicon surface, with the following steps:

• Providing a substrate having a silicon surface;
• Depositing an aluminum nitride nitrile layer on the silicon surface of the substrate;
• Optionally: depositing an aluminum-containing nitride buffer layer on the nitride resin inlayer;
• Depositing a masking layer on the nitride shellimide layer or, if present, on the first nitride buffer layer;
• Depositing a gallium-containing first nitride semiconductor layer on the masking layer,

wherein the masking layer is deposited such that in the deposition step of the first nitride semiconductor layer first separate crystallites grow, which grow together above a coalescence layer thickness and occupy an average area of at least 0.16 μm ² in a layer plane of the coalesced nitride semiconductor layer perpendicular to the growth direction.

Surprisingly, it is possible with the method according to the invention, during the growth of the first nitride semiconductor layer, to produce an increased compressive stress which, with suitable further process control, can even lead to complete or almost complete compensation of the tensile stress .sigma different thermal expansion coefficient arises. It is possible to grow a layered structure which, after cooling at room temperature, is either completely stress-free or with a value of σ, which in any case is well below 0.2 GPa / μm, but generally even below 0.1 GPa / μm - almost free of tension and above also has a very low dislocation density and very little or no cracks.

The inventive method is also suitable for the production of layered structures with special high or even infinite radius of curvature, in particular in the manufacture of thin-film components such as light-emitting diodes of great Advantage are.

In order to will be a cost effective Growth of thin-film devices on nitride semiconductor basis also on large-scale silicon or SOI (Silicon-on-Insulator) wafers allows.

These advantages are presumably due to the fact that the growing together crystallites above a suitably deposited masking layer, which preferably consists of SiN, during growth with an average crystallite area of 0.16 μm ² and more in the nitride semiconductor layer by their coalescence a sufficiently strong compressive stress produce. This stronger compressive stress can better compensate for the later unknown stress.

The average crystallite area the crystallites in a layer plane above the coalescence layer thickness in a nitride semiconductor layer can be determined by means of a image-based Analysis method such as an evaluation of plan-view determine transmission electron micrographs (TEM) as will be explained in more detail below with reference to two examples. The analysis is Of course a sufficiently large sample of crystallites.

Of the previous state of the art was due to the observed saturation effects in use as described above a SiN masking layer (Dadgar et al.) and the observed and also described above, only partial stress reduction at Using a GaN buffer layer (Mo et al.) The occurrence of this Effect and the possibility almost complete Do not expect stress compensation. This surprising effect is according to the present Invention for producing particularly slightly strained or completely unstressed Used nitride semiconductor layer structures on silicon surface, which then special advantageous nitride semiconductor components can be produced.

If in the claims of an aluminum-containing nitride layer with respective function (Ankeimschicht, buffer layer, interlayer, etc.) spoken is to be understood as a layer of the respective function, containing aluminum either as sole Group III metal or in combination with other Group III metals. Of dopings with elements of other groups of the periodic table, such as silicon or magnesium, is hereby omitted for purposes of definition. Of course, however, you can also contain such dopants.

A Anchor layer is only a few nanometers thick, not mandatory closed layer, despite possibly poor crystalline and / or stoichiometric Properties a basis for a subsequent one Layer growth of the layer growing on it, or of the another layer growth emanates.

A Masking layer serves for complete or partial coverage a surface and is common just a few monolayers or even less than a monolayer thick.

• – Herstellung einer Schichtstruktur eines Nitrid-Halbleiterbauelements auf einer Siliziumoberfläche nach einem Verfahren gemäß dem ersten Aspekt der Erfindung oder einem der in dieser Anmeldung nachfolgend beschriebenen Ausführungsbeispiele oder einem der zugehörigen abhängigen Ansprüche;
• – Bonden der Schichtstruktur mit einem Träger derart, dass die Wachstumsoberseite der Schichtstruktur dem Träger zugewandt ist;
• – Entfernen des Substrats;
• – Herstellung einer Kontaktstruktur.

A second aspect of the present invention relates to a method for producing a nitride semiconductor device, comprising the steps of:

• - Producing a layer structure of a nitride semiconductor device on a silicon surface according to a method according to the first aspect of the invention or one of the embodiments described below in this application or one of the dependent claims thereof;
• - Bonding the layer structure with a carrier such that the growth top of the layer structure faces the carrier;
• - removing the substrate;
• - Production of a contact structure.

The Method according to the second Aspect of the invention is an advantageous development of the method of the first aspect of the invention and allows a particularly simple and cost-effective Processing of nitride semiconductor devices.

• – einer galliumhaltigen ersten Nitridhalbleiterschicht, die eine Struktur zusammengewachsener Kristallite aufweist, die in einer Schichtebene senkrecht zur Wachstumsrichtung eine durchschnittliche Fläche von mindestens 0,16 μm² einnehmen,
• – einer aluminiumhaltigen Nitridzwischenschicht, die an die erste Nitridhalbleiterschicht angrenzt, und,
• – angrenzend an letztere Schicht, einer galliumhaltigen weiteren, zweiten Nitridhalbleiterschicht.

According to a third aspect of the invention, the above-mentioned technical problems are solved by a nitride semiconductor device having

• A gallium-containing first nitride semiconductor layer having a structure of coalesced crystallites occupying an average area of at least 0.16 μm ² in a layer plane perpendicular to the growth direction,
• An aluminum-containing nitride intermediate layer adjacent to the first nitride semiconductor layer, and
• Adjacent to the latter layer, a gallium-containing further, second nitride semiconductor layer.

Such Components that have a for the production on a silicon surface characteristic structure have the nitride semiconductor layer, have low production costs one for commercial applications essential long life and cheap Operating parameters.

The Nitride semiconductor device of the third aspect of the invention has Structural features necessary for the inventive process characteristic and allow a nitride semiconductor device manufactured by this method to differentiate from other nitride semiconductor devices.

So it is basically also possible and known per se, crystallites with a large average area at Use of a sapphire substrate to produce. However, point Sapphire substrate produced nitrite semiconductor devices that do not exceed 100 nm thick AlGaN layers, no aluminum-containing nitride semiconductor interlayers, in particular no aluminum nitride intermediate layers. The growth of semiconductor layers on sapphire substrate is completely different Boundary conditions than growth on silicon substrate, as in of the present invention. Because the layer growth on Sapphire substrate leads always to a biaxially compressively strained layer after cooling. A StrAlN engineering with the help of aluminum-containing nitride intermediate layers, the a compressive strain of the GaN layers during growth leads, is not necessary there and even undesirable in LED structures, since This leads to a very strong substrate curvature during the growth of InGaN Layer around 800 ° C and at the end of the process leads. As explained at the beginning, It is also known per se in the growth of nitride semiconductor layers on silicon aluminum-containing nitride semiconductor interlayers for the StrAlN engineering to use.

But a combination of these two features was not technically reachable. Only with the process control according to the first aspect of the present Invention has managed to layers with crystallites sufficient huge Surface up To produce silicon substrate. With continued growth of this Nitride semiconductor layers for producing thicker nitride semiconductor layers greater than about 1300 nm Thickness will be alone for growth based on a substrate with silicon surface StrAlN engineering interlayers required to do so while of growth to set a sufficiently large compressive stress, the one at the final cooling down completely or almost completely compensate for a tensile stress then occurring can. In the art, it has not been possible to date, a nitride semiconductor device according to the present third Aspect of the invention.

The when deposited on the silicon surface initially produced layers, namely the aluminum-containing Nitridankeimschicht and the masking layer be for a production of thin-film components like thin-film LEDs after the replacement of the grown layers of the silicon surface in the context of the other Processing typically removed. Therefore, with the inventive method Nitride semiconductor components are produced, which, although the process control according to the invention do not detect the presence of the seeding and masking layers but where the presence of aluminum-containing nitride semiconductor layers is intermediate in the layer structure a clear indication of the use of a silicon substrate during growth.

• – einem Substrat, das eine Siliziumoberfläche hat,
• – einer an die Siliziumoberfläche angrenzenden aluminiumhaltigen Nitridankeimschicht,
• – optional: einer an die Nitridankeimschicht angrenzenden aluminiumhaltigen Nitridpufferschicht,
• – einer Maskierungsschicht auf der Nitridankeimschicht oder, wenn vorhanden, auf der Nitridpufferschicht, und mit
• – einer an die Maskierungsschicht angrenzend angeordneten galliumhaltigen ersten Nitridhalbleiterschicht, die eine Struktur zusammengewachsener Kristallite aufweist, wobei die Kristallite oberhalb einer Koaleszenzschichtdicke und in einer Schichtebene senkrecht zur Wachstumsrichtung eine durchschnittliche Fläche von mindestens 0,16 μm² einnehmen.

According to a fourth aspect of the invention, the above-mentioned technical problems are solved by a nitride semiconductor product

• A substrate having a silicon surface,
• An aluminum-containing nitride tine layer adjacent to the silicon surface,
• Optionally an aluminum-containing nitride buffer layer adjacent to the nitride resin inlay,
• A masking layer on the nitride resin layer or, if present, on the nitride buffer layer, and with
• A gallium-containing first nitride semiconductor layer arranged adjacent to the masking layer and having a structure of coalesced crystallites, the crystallites occupying an average area of at least 0.16 μm ² above a coalescence layer thickness and in a layer plane perpendicular to the growth direction.

The Nitride semiconductor product of the invention is typically a self-negotiable one Intermediate of component manufacturing. It can be used for manufacturing of components both on the existing substrate with silicon surface as also, after detachment of the substrate, used on another carrier, or for the production large-scale cantilever Layers, large-area nitride semiconductor substrates or cantilevered components.

Embodiments of the various method and apparatus aspects of the present invention will now be described. The execution examples can be combined with each other, unless expressly stated is closed.

First, be embodiments of the method for producing a layer structure of a nitride semiconductor device on a silicon surface according to the first Aspect of the invention described.

With particularly large crystallite surfaces, the layer quality is improved. In a preferred embodiment, the masking layer is therefore deposited in such a way that separated crystallites initially grow together above a coalescence layer thickness and occupy an average area of at least 0.36 μm ² in a layer plane of the coalesced nitride semiconductor layer perpendicular to the growth direction in the deposition step of the first nitride semiconductor layer.

In a further exemplary embodiment, the masking layer is deposited with a layer thickness which, when the first nitride semiconductor layer first grows in the form of growth islands, results in a layer area which is at least 80% closed at a distance of at least 600 nm from the masking layer. The process control of this embodiment has resulted in studies with good reproducibility to gallium nitride semiconductor layers that are largely grown together above a layer thickness of 600 nm and having in layer planes above this distance from the seed layer large crystallites whose average surface area is in excess of 0.16 microns. ²

Prefers is in the process control according to the invention and especially in litigation in the embodiment just described assumed a masking layer, which is a covering of underlying Nitridankeimschicht or, if available, the first nitride buffer layer of at least 95%. In this Degree of coverage arises relatively above the masking layer few growth nuclei, which in the course of further layer deposition by a three-dimensional growth (island growth) to large crystallites can develop.

The The best results have so far been with silicon nitride masking layers achieved. in principle However, it is also conceivable other suitable materials for the masking layer to use, such as anti-Surfactands, which is a wetting prevent the Ankeimschicht. Here, in principle, for example all metal nitrides, which at the high growth temperatures of the Nitride semiconductor deposition can be used. substances which grow up amorphous, but are more appropriate because often on such surfaces no or only one delayed Germination takes place.

The process management is in a preferred embodiment accompanied by a follow-up measurement of the reflection intensity of the growth surface (Reflectometry). This per se known method of monitoring the layer growth allows a control and defined setting of the duration of the deposition the masking layer, which is preferably chosen so that in the deposition step the first nitride semiconductor layer contributes to the follow-up measurement of the reflection intensity of the growth surface a wavelength of light of about 600 nm an oscillating intensity curve with increasing Oscillation amplitude shows that after at least five oscillation cycles one then reached about constant maximum value. The exact value the duration of the deposition of the masking layer depends on numerous parameters ranging from growth reactor to growth reactor can vary. With the guidance of the present embodiment can in few experiments a suitable duration of deposition of the masking layer for a respective growth reactor can be determined.

Nice the first nitride semiconductor layer grows according to the method according to the invention compressive stress. There is no preference for coalescence promoting Growth parameters (such as an increased growth temperature or a high V / III ratio) set. Under these conditions, one obtains a particularly compressive Layer growth and can thus a lower tensile stress after cooling and thus a homogeneously strained or unstrained nitride semiconductor layer structure produce.

Should a nitride semiconductor with a higher layer thickness are deposited, the first nitride semiconductor layer is preferably with a layer thickness of 800-1600 nm deposited before further growth as explained below become the higher Layer thickness lead. Namely then is preferred on the first nitride semiconductor layer, an aluminum-containing nitride intermediate layer separated and then on the latter layer a gallium-containing further nitride semiconductor layer deposited, also referred to as the second nitride semiconductor layer becomes. With the aluminum-containing nitride intermediate layer, which in the case of Growth of GaN as the first nitride semiconductor layer preferably one Low-temperature AlN layer can be, the most compressive stress in the Layer structure further increased become. The function of the aluminum-containing nitride intermediate layer This is the StrAlN engineering.

The sequence of steps of depositing an alu Miniumhaltigen nitride intermediate layer and a gallium-containing further nitride semiconductor layer can be carried out repeatedly. In this way, the first nitride semiconductor layer may be followed by a second, third, fourth, etc. nitride semiconductor layer, each with aluminum-containing intermediate layers deposited therebetween. The result, apart from the nitride intermediate layers, a thick nitride semiconductor layer, which is composed of the first, second, possibly third, etc. nitride semiconductor layer. If desired, other intermediate layers with a different function can of course be incorporated herein.

The thickness of the aluminum-containing nitride intermediate layer is, for example, 8 to 15 nm in the case of using a low-temperature AlN intermediate layer. It is also conceivable to use an AlGaN intermediate layer, whereby approximately the same layer thicknesses are suitable here. From the DE 10 2004 038 573 A1 Applicant is aware of the use of thicker, high temperature AlN interlayers for StrAlN engineering purposes. It should be noted that experience has shown that starting from a thickness of this layer of about 30 nm, a tendency to form a high-resistance layer structure arises, which is disadvantageous for the production of light emitters. Also, the tendency for cracking increases.

Becomes to the use of aluminum-containing nitride intermediate layers omitted, the first nitride semiconductor layer is preferably with a thickness of 1300 nm (for the case GaN) deposited. Above this layer thickness can at Cool down due The then occurring tensile stress component cracks occur.

to Production of Light Emitting Nitride Semiconductor Devices preferably on the second or, after process control with an above explained repeated layer deposition, another other nitride semiconductor layer a multi-quantum well structure of nitride semiconductor material deposited. Multi-quantum-well structures for light-emitting Nitride semiconductor devices are known per se and need it here not closer explained become.

It It has been found that depositing at least one second masking layer of silicon just prior to the deposition of those of the others Nitride semiconductor layers on which the multi-quantum well structure is deposited, a particularly good coating quality in the for the light emission achieved crucial area of the layer structure.

to Production of an optoelectronic component is preferred into the first and, if present, those further nitride semiconductor layers, which are deposited in front of the multi-quantum well structure, one introduced n-doping. For producing a p-doped zone preferably becomes one on the multi-quantum well structure p-doped gallium-containing nitride semiconductor cap layer deposited.

In particular for the growth of thick layer structures, the problem is to be considered that a stress arising in the nitride semiconductor layer structure also acts on the substrate and can lead to a substrate curvature. Such a curvature is also known from other heterosubstrates, such as sapphire. The reduction of this curvature in a preferred embodiment includes the step of providing a substrate providing a particularly conductive silicon substrate whose thickness is at least D _GaN x, where D _{GaN is} the layer thickness of the nitride semiconductor layer to be deposited on the substrate or if more than one nitride semiconductor layer is the sum of the layer thicknesses of the nitride semiconductor layers to be deposited on the substrate and the existing nitride intermediate layer, and wherein x is at least 110 in the case of using a doped silicon substrate and at least 200 in the case of using an undoped substrate. With these values of the layer thickness, it is possible in each case to prevent the possible plastic deformation due to the compressive bias in the Si substrate. This is advantageous because a crystal deformed in this way could not plan anymore.

This additional Feature of the present embodiment represents an independent protection worthy idea of the invention an independent legitimate Method for producing a layer structure of a nitride semiconductor component a silicon surface thus includes the step of providing a silicon substrate according to the additional Feature of the last-mentioned embodiment. The others Steps of the method of the first aspect of the invention and the Embodiments described herein of the method of the first aspect of the invention form embodiments this independently protectable Process. Especially with stronger strained layer structures can be obtained by the method of this independent invention prevents the silicon substrate from bending too much.

ist, wobei

Diese zusätzliche Bedingung ist insbesondere bei Leuchtdioden mit InGaN oder AlGaN-Schichten von Vorteil.The above embodiment is further improved when the silicon substrate has a thickness which is additionally greater than or equal to

is, where

This additional condition is particularly advantageous for light-emitting diodes with InGaN or AlGaN layers.

following Be exemplary embodiments of Method according to the second Aspect of the invention, which describes the production of a nitride semiconductor device concerns. This procedure contains all steps of the method of the first aspect of the invention and thus also shares its advantages.

at a preferred embodiment of this Method according to the second aspect of the invention is an electrical conductive Contact layer on the growth top of the after process according to the first Aspect of the invention produced layer structure.

abgeschieden wird, wobei m = 0, 1, 2, 3, ...; λ eine Wellenlänge einer Lichtemission der Multi-Quantum-Well-Struktur im Betrieb des Nitrid-Halbleiterbauelements, n_Nitrid den Brechungsindex des Nitrids bei der Wellenlänge λ und d_MQW die Dicke der Multi-Quantum-Well-Struktur bezeichnet. Dies erhöht die Lichtausbeute, wenn die Nitridhalbleiterdeckschicht im fertigen Bauelement in Material mit n > n(Nitrid) eingebettet ist. Hierzu zählen Metalle oder höherbrechende Materialien, beispielsweise höherbrechende Halbleiter.In a first of two alternative embodiments described below, the contact layer has a higher refractive index than the p-type nitride semiconductor cap layer. The contact layer may additionally be metallized, as well as the growth top of the nitride semiconductor layer structure, if no contact layer is present. In this way, the luminous efficacy of the nitride semiconductor device is increased. In this first alternative embodiment having a contact layer whose refractive index is greater than that of the p-doped nitride semiconductor cap layer, this nitride semiconductor cap layer is preferably formed to have a thickness of

is deposited, where m = 0, 1, 2, 3, ...; λ denotes a wavelength of a light emission of the multi-quantum well structure in the operation of the nitride semiconductor device, n _nitride, the refractive index of the nitride at the wavelength λ and d _MQW the thickness of the multi-quantum well structure. This increases the light output when the nitride semiconductor cap layer is embedded in the finished device in n> n (nitride) material. These include metals or higher refractive materials, such as higher refractive semiconductors.

abgeschieden, wobei m = 1, 2, 3, 4, ...; λ eine Wellenlänge einer Lichtemission der Multi-Quantum-Well-Struktur im Betrieb des Nitrid-Halbleiterbauelements, n_Nitrid den Brechungsindex des Nitrids bei der Wellenlänge λ und d_MQW die Dicke der Multi-Quantum-Well-Struktur bezeichnet. Diese Formel gilt für den Fall der Abdeckung der Nitridhalbleiterdeckschicht mit einem Material mit kleinerem Brechungsindex, wie z. B. verschiedene Kunststoffe, Luft etc.. Dies ist der üblichere Fall bei Standard LEDs, nicht jedoch bei abgelösten LEDs.In the second of the two alternative embodiments, the contact layer has a lower refractive index than the p-doped nitride semiconductor cap layer. In this embodiment, the nitride semiconductor cap layer is preferably made with a thickness of

deposited, where m = 1, 2, 3, 4, ...; λ denotes a wavelength of a light emission of the multi-quantum well structure in the operation of the nitride semiconductor device, n _nitride, the refractive index of the nitride at the wavelength λ and d _MQW the thickness of the multi-quantum well structure. This formula applies to the case of covering the nitride semiconductor cap layer with a material having a smaller refractive index, such as. Different plastics, air, etc. This is the more common case with standard LEDs, but not with detached LEDs.

It has proven to be particularly advantageous to use a carrier its surface used for bonding electrically conductive, reflective or metallic. It is well known that most metals combine these Properties in an advantageous manner. In this way, the heat dissipation improved from the device. Preferably, the metallic surface or the entire carrier made of copper, aluminum, aluminum nitride, silicon or aluminum-silicon or aluminum-silicon-carbon educated.

A particularly suitable other support material is aluminum-silicon (Al / Si) with a high, ideally over at least 70% silicon content, an electrically and thermally very good conductive connection with, unlike copper or aluminum, almost identical coefficient of expansion compared to GaN or at higher Si content even identical expansion coefficient. This prevents problems when mounting and operating the LEDs, since the resulting stresses can lead to the detachment of the component or cracking of the layer. Therefore, currently, for example, LEDs mounted on Al-carriers with elastic adhesives, because only then the very different coefficients of thermal expansion (GaN ~ 5.6 ppmK ^-1, Al> 20 ppmK ^-1) can be controlled. However, the use of elastic adhesive has disadvantages. A further independent invention therefore forms the use of an Al / Si carrier for the production of a light-emitting thin-film nitride semiconductor component, and a light-emitting thin-film nitride semiconductor component with an Al / Si carrier as such, the composition of the Al / Si carrier. Carrier according to the invention is chosen so that it has an identical or nearly identical thermal expansion coefficient as the nitride semiconductor material of the device. The disadvantages of elastic adhesives can be completely avoided with an Al / Si support (coefficient of expansion of AlSi (30/70), for example 7.5 ppmK ^-1 ). After all, the heat conduction of this carrier material is half that of aluminum, which is more than an order of magnitude better than that of Si.

The bonding is preferably at low Temperatures are carried out in a range between 280 and 500 ° C. At present, a temperature of 280 ° C. is particularly preferred. In this way, no or only small additional tensions are generated during cooling after bonding. Below 280 ° C, the metal does not become liquid. A temperature of 500 ° C represents a tendency for some wearers due to possibly occurring stress, even a critical upper limit, but may still be useful for other carriers. At temperatures higher than 500 ° C, depending on the material used, the contact metal may also suffer greatly.

The Removing the substrate in the method of the second aspect of the present invention Invention is preferably carried out by grinding. In addition, can Wet or dry chemical etching used become.

In a further embodiment becomes the growth back exposed by removal of the substrate structured to form an antireflective layer. For example, this can be done very easily by etching with KOH (potassium hydroxide). from the N-face, ie the nitrogen face (000-1) of the material and, with suitable process control, gives structures which are well suited, the approximately pyramidal are.

• – Herstellung einer Schichtstruktur eines Nitrid-Halbleiterbauelements auf einer Siliziumoberfläche;
• – Bonden der Schichtstruktur mit einem Träger derart, dass die Wachstumsoberseite der Schichtstruktur dem Träger zugewandt ist;
• – Entfernen des Substrats bis auf eine dünne Siliziumschicht, die vorzugsweise 5 bis 10 μm dick ist;
• – Oxidieren der Siliziumschicht zur Bildung einer Siliziumdioxid-Schicht;
• – Herstellen einer Kontaktstruktur.

According to an alternative process management, which also forms a fourth independent invention worthy of protection, the substrate according to the described process control according to the second aspect of the invention or one of its embodiments is not complete, but thinned to a remaining layer thickness of 3-10 microns and then oxidized. The resulting silicon oxide layer is rough structured as a transparent layer. The method thus comprises the steps

• - Producing a layer structure of a nitride semiconductor device on a silicon surface;
• - Bonding the layer structure with a carrier such that the growth top of the layer structure faces the carrier;
• - Removing the substrate except for a thin silicon layer, which is preferably 5 to 10 microns thick;
• - oxidizing the silicon layer to form a silicon dioxide layer;
• - Creating a contact structure.

These process management has the advantage of being for an improved light extraction can be used. Furthermore the oxidation of the silicon substrate causes an expansion of the former Substrate and thus in the wake of a slightly compressive strain the nitride semiconductor (eg GaN) layer. This is especially true of Advantage, if this GaN layer is slightly tensioned. By the Compressive stress thus becomes cracking and bending of the GaN layer safely avoided. The by the remaining of the oxidized Si substrate thicker layer stacks with thicknesses in the range of 6-20 microns in particular a higher one mechanical strength on what the manufacture of the components simplified.

following Be exemplary embodiments of Nitride semiconductor device according to the invention according to the third Aspect of the invention described, unless they are already directly from the embodiments described above the method according to the invention result. Preferably contains the nitride semiconductor device comprises a carrier of the nitride semiconductor layer structure, which is different from the substrate on which the layer structure has grown has been. A particularly suitable carrier consists essentially made of copper, aluminum or Al / Si. In this way, the derivative becomes of heat improved, which generates during operation of the nitride semiconductor device becomes.

embodiments with p- and n-doped regions, as used for semiconductor light-emitting devices (LEDs, laser diodes), but also for electronic Components (transistors, etc.) are common in one preferred embodiment each provided with an electrical contact element.

One Another preferred embodiment contains at least one further masking layer of silicon nitride directly arranged adjacent to that of the further nitride semiconductor layers, on the the multi-quantum well structure is deposited, but at the of the multi-quantum well structure opposite side of this further nitride semiconductor layer. To this Way, the shift quality improved in the area of the device, that of the multi-quantum well structure the next lies and therefore a big one Influence on the carrier lifetime Has. By improving the quality of the coating, a longer charge carrier lifetime can be achieved be achieved, indicating the suppression of unwanted Recombination due to defects.

One Intermediate, which in the production of the nitride semiconductor component according to the invention is generated, is a carrier disk, on a variety of inventive nitride semiconductor devices is arranged. The carrier disk forms an intermediate, which with a processed wafer of the Silicon technology is comparable. The isolation of the on the carrier disc arranged nitride semiconductor devices can be at the manufacturer of in this respect, the carrier disk was processed yourself or after being transported by a component manufacturer respectively.

Of the Advantage of the invention lies in this aspect is that particular size Carrier discs used can be because the inventive method can on big, be carried out commercially widely used silicon wafers. To Separating the grown on the silicon wafer nitride semiconductor layer structure can this with a carrier disk corresponding size connected become. The invention allows therefore a particularly cost-effective Production of components. The nitride semiconductor devices can on the carrier For example, in its entirety a lateral extent of have at least 24 cm.

following Be exemplary embodiments of Nitride semiconductor product according to the fourth Aspect of the invention described, unless they are immediate from the embodiments described above of the other aspects of the invention.

In a preferred embodiment the nitride semiconductor product one, at the substrate in one to the back substrate surface vertical direction measurable curvature, the one radius of curvature of at least 10 m or an infinitely large radius of curvature. So high radii of curvature are possible with the process control according to the invention, if by inserting of low-temperature StrAlN engineering intermediate layers sufficient high compressive stress during of the growth produced by the subsequent cooling the resulting tensile stress is compensated as accurately as possible.

Further embodiments and advantages of the invention will become apparent from the following description the enclosed figures. Show it:

1 an embodiment of a nitride semiconductor product which forms an intermediate in the manufacture of a nitride semiconductor device according to the invention;

2 a diagram showing the evolution of the radius of curvature of the semiconductor product of 1 during its manufacture, as well as by comparison the radius of curvature of a prior art nitride semiconductor product during its manufacture;

3 a graph showing the time evolution of the reflected light from the growth surface of the nitride semiconductor product during its manufacture;

4a and b) Differential Interference Contrast Microscope (DIC) images of GaN films prepared by prior art methods;

4c ) a DIC image of a GaN layer produced by a method according to the invention;

5a ) an in-plane transmission electron micrograph of a GaN layer prepared by a prior art method;

5b ) an in-plane transmission electron micrograph of a GaN layer prepared by a method of the invention; and

6a ) - 6f ) Different process stages in the production of a light emitting diode from the nitride semiconductor product of 1 ,

1 shows a schematic view of the layer structure of a nitride semiconductor product 100 , The nitride semiconductor product 100 forms an intermediate in the manufacture of a nitride semiconductor device, as described below with reference to FIGS 6a ) - 6f ) is explained in more detail.

The representation in 1 is not to scale. In particular, the exact ratio of the layer thicknesses of the individual layers shown to one another can not be determined from the FIG. The layer thickness ratios shown in the figure only provide a very rough indication. In the following description, the shortage of representing half process aspects in parallel to device aspects will be explained.

The nitride semiconductor product 100 contains a layer structure 102 on a silicon wafer 104 , The used growth surface of the wafer perpendicular to the paper plane of the 1 is a (III) silicon surface. Instead of a silicon wafer, it is also possible to use an SOI substrate or any other substrate, preferably with a (III) silicon surface.

A

eine Nitridankeimschicht im Verbund mit einer Pufferschicht,

B

eine Maskierungsschicht,

C

Nitridhalbleiterschichten, hier insbesondere n-leitende GaN-Schichten

D

eine Multi-Quantum-Well-Struktur,

E

eine p-dotierte Nitridhalbleiterdeckschicht, hier insbesondere p-GaN und

F

eine Niedertemperatur-AlN oder AlGaN-Zwischenschicht für das StrAlN-Engineering.

In 1 are to denote the layers for the sake of clarity in addition to the numbers formed by numbers 106 to 122 Letters A to F are placed to the left of the individual layers. The same letters identify layers of the same type. Specify in detail

A

a Nitridankeimschicht in conjunction with a buffer layer,

B

a masking layer,

C

Nitride semiconductor layers, in particular n-type GaN layers

D

a multi-quantum well structure,

e

a p-doped nitride semiconductor cap layer, in particular p-GaN and

F

a low-temperature AlN or AlGaN intermediate layer for StrAlN engineering.

Further details The layer structure and its production are described below.

Before depositing layers, the growth surface of the wafer becomes 104 passivated. This means that it is deoxidized either by wet-chemical treatment or by heating in vacuo or under hydrogen at temperatures above 1000 ° C and a hydrogen-terminated surface is produced.

The Ankeimschicht 106 has a thickness of between 10 and 50 nm. In combination with a deposited in the present example, but in principle in the process management optional optional buffer layer, a layer thickness of at most 400 nm.

Suitable is an AlN seed layer, either at low temperature, ie below 1,000 ° C, for example 600-800 ° C or at high temperature, so ordinary Growth temperatures of AlN above 1000 ° C, is grown. The optional Buffer layer is preferably also made of AlN and is at high Growth temperatures applied. However, the buffer layer can also consist of AlGaN. When using AlGaN, the Ankeimschicht also a bigger thickness have, for example, about 600 nm.

At the Growth of the germ layer is favorable, the supply of the aluminum precursors into the reactor before feeding the nitrogen precursor to so as to prevent nitridation of the substrate. A nitridation of the substrate can lead to unwanted polycrystalline growth lead by AlN.

On the combination of Ankeim- and buffer layer 106 a masking layer of silicon nitride is deposited. This is done by simultaneously passing a silicon precursor such as silane or disilane or an organic silicon compound, and a nitrogen precursor such as ammonia or dimethylhydrazine. On the growth surface, the two precursors react to form silicon nitride.

The thickness of the SiN masking layer is chosen so that in the subsequent growth of the first nitride semiconductor layer 110 in a continuous re flektometriemessung at a wavelength of 630 nm, the full oscillation strength is reached only after more than four oscillations. This corresponds to approx. 600 nm layer thickness. In general, this results in a surface with only a small hole density, ie not yet planarized areas between the original islands, of <5%, which is generally not resolvable in reflectometry. A suitable SiN layer thickness is to be determined according to this rule by simple experiments. A transfer of this technical teaching to other wavelengths used in reflectometry is easy for a person skilled in the art.

In the growth of the first nitride semiconductor layer 110 , which in the present example the 1 consists essentially of GaN and therefore also as a GaN layer 110 is designated, no coalescing promoting growth parameters are set in the present embodiment. That is, the temperature and ratio of nitrogen and gallium precursors are not increased. Using such parameters, a sufficiently compressive growth of the GaN layer is obtained 110 and thus a much lower tensile stress after cooling, and thus a much less curved and homogeneous relaxed component structure.

The leading to growth conditions to a higher one Island size, the an improvement in the layer quality causes and also a lower Rising tendency shows.

The layer thickness of the GaN layer 110 is between 800 and 1600 nm. This is followed by an aluminum-containing nitride semiconductor intermediate layer in the form of a low-temperature AlN intermediate layer for the StrAlN engineering 112 deposited. The low-temperature AlN intermediate layer here has a thickness of 8 to 15 nm.

The low temperature AlN interlayer increases the compressive stress component. If this layer were omitted, it could be due to the SiN masking layer 108 a GaN layer of 1300 nm thickness without cracks gewach sen, because when cooled in this case, the tensile stress component above this thickness would cause cracks.

The insertion of the low temperature AlN interlayer 112 Thus, it is possible to achieve a higher overall layer thickness of the GaN layer by growing a sequence of further GaN layers and low-temperature AlN intermediate layers. The low temperature AlN interlayer 112 Accordingly, a second GaN layer follows 114 again from about 800 to 1600 nm thickness, again followed by another low temperature AlN interlayer 115 , On this is a third GaN layer 116 deposited. This in turn becomes a second masking layer 117 deposited from SiN. The second SiN masking layer 117 causes a reduction in the dislocation density in the subsequent fourth GaN layer 118 , The four GaN layers 110 . 114 . 116 and 118 are n-doped. The doping takes place during growth by adding a suitable dopant precursor.

The procedure described so far already leads in the first GaN layer 110 , which corresponds to the first nitride semiconductor layer of the above description, to a growth with compressive stress. The achievable reduced tensile stress facilitates the subsequent removal and sticking of the wafer 104 on a carrier. Because the forces acting on the glue are less. The entire layer structure 102 therefore remains easier to hang on the carrier. The improved crystal structure and the reduced tensile strain already in the first GaN layer 110 moreover reduce the tendency to crack during and after peeling of the layered structure 102 ,

On the fourth GaN layer 118 a multi-quantum-well structure is deposited. The choice of material and exact layer structure of this multi-quantum well structure 120 is set according to the desired wavelength of the light emission. The parameters to be set for this, such as layer stoichiometry and layer thickness, are known to the person skilled in the art. As is known, the addition of indium reduces the band gap of a nitride semiconductor, for example starting from pure GaN, in the direction of the band gap of indium nitride. By adding aluminum, the band gap is increased in the direction of the value of AlN. In this way, a light emission with a desired wavelength can be set which lies between the red and the ultraviolet spectral range.

On the multi-quantum well structure 120 Optionally, an injection barrier of about 10 to 30 nm thickness may be provided, which in 1 not shown.

Rather, it is a representation directly to the multi-quantum-well structure 120 subsequent cover layer 122 from p-GaN.

The The above description concerned an embodiment of a nitride semiconductor device according to the invention. It is understood that in another device such as a field effect transistor, the details of the layer structure and the layer doping are set in a conventional manner.

2 Figure 11 is a graph showing the evolution of the curvature of a nitride semiconductor product during its fabrication by the method of the present invention, and compared to the curvature of a prior art nitride semiconductor product during its fabrication. On the abscissa of the graph, the time in minutes elapsed between the beginning of the layer deposition on a (III) silicon substrate and the end of the cooling of the grown layer structure. The curvature is plotted on the ordinate, that is, the reciprocal of the radius of curvature of the nitride semiconductor product. The measurement of the curvature is possible with modern measuring methods with great precision. Details of the curvature measurement can be found in the publications A. Krost et al., Phys. Stat. sol. (b) 242, 2570-2574 (2005) and A. Krost et al., phys. stat. sol. (a) 200, 26-35 (2003). The values of curvature between -0.2 and 0.2, which are plotted on the ordinate, correspond to curvatures with an amount of the radius of curvature between 5 m and infinity.

In the diagram of 2 two different curves are plotted. Dashed lines show a curve of curvature during the growth of the conventional prior art nitride guide. A solid line shows the time course of the curvature of the nitride semiconductor product according to the invention.

It can be distinguished in the process of the invention four different growth phases, which in 2 are separated by vertical dashed lines. The time intervals thus defined are with Arabic numerals 1 to 4 characterized. In a time interval 1 the growth of the AlN seed layer occurs 106 and heating to a growth temperature suitable for depositing GaN above 1000 ° C. Starting from an initially vanishing curvature (corresponding to an infinite radius of curvature), a slight positive curvature arises in this time interval for both different structures. In a subsequent time interval 2 which extends from just over 30 minutes to about 45 minutes after the onset of growth, the SiN masking layer ( 108 in the example of 1 ) and the first GaN layer ( 110 in 1 ) grew up. In this time interval, the beginning of the coalescence of the GaN growth islands falls. It can clearly be seen that the curvature of the layer structure produced by the method according to the invention assumes higher values at this stage than in the comparison structure which is grown by a conventional method without SiN masking layer.

In a subsequent time interval 3 becomes the first GaN layer ( 110 in 1 ) grown. In the comparative sample according to conventional process management, the method procedure is deviating here because of the absence of intermediate layers and the time interval extends 3 between 30 and just over 80 minutes after the start of growth. In the present case, no low-temperature AlN growth phase is used to produce the AlN intermediate layer 112 inserted.

Both structures are cooled after completion of the layer deposition (time interval 4 ). In the comparative sample prepared according to the prior art as in the sample according to the invention, the cooling takes place about 90 minutes after the start of the process and results in the comparison sample as a result to a relatively large curvature of the sample of about 0.17 m ^-1 , which Radius of curvature of about 5.8 m corresponds. In the layer structure produced according to the invention, the curvature after completion of the cooling process is about 0.12 m ^-1 , which corresponds to a radius of curvature of about 8.3 m. This value can be achieved by inserting further low temperature AlN layers, as in the layered structure of 1 are further optimized so that a nitride semiconductor product with vanishing curvature can be made.

3 FIG. 15 is a graph showing the time evolution of the light reflected from the growth surface of the nitride semiconductor product during its manufacture during the process of FIG 2 method described for the comparative sample (dashed curve) and the sample prepared according to the invention. The diagram thus shows the result of a reflectometry measurement with a light wavelength of about 600 nm during the growth of the layer structure according to the 2 explained process control. Plotted is the reflected light intensity over time. The diagram is the same as 2 in time periods 1 . 2 . 3 and 4 divided. With arrows are in the section 2 initial intensity maxima of the known in the case of layer growth oscillating reflected light intensity. It can be seen that in contrast to the comparative sample in the sample produced according to the invention, the full stroke between intensity minima and maxima is reached after 5 to 6 oscillations. If the duration of the growth of the masking layer is adjusted so that such a course occurs in the reflectometry measurement, according to experience in the deposition step of the GaN layer initially separate crystallites are present, which grow together above a coalescence layer thickness and in a layer plane of the coalesced nitride semiconductor layer perpendicular to the growth direction an average area of at least 0.16 μm ² to 0.36 μm ² . It is to be expected that with further optimization of the growth parameters even larger average areas can be achieved.

4a ) and b) show differential interference contrast microscopy (DIC) images of GaN films prepared by prior art methods. 4c ) shows a DIC image of a GaN film produced by a prior art process.

The scanning electron micrographs of the 4a ) to 4c ) show surfaces of differently prepared GaN layers imaged on the same scale. In the 4a ) was prepared without SiN masking layer and has a thickness of about 2.5 μm. It can be clearly seen that the surface has a multiplicity of cracks. In the 4b ) surface belongs to a sample that was prepared with a SiN masking layer, but without AlN intermediate layer for StrAlN engineering with a thickness of 2.4 microns. This layer shows a clearly improved structure with only a few cracks compared to the previously described sample.

In the 4c ) surface of a sample, which was grown according to the invention, ie with a suitable SiN masking layer and with low-temperature AlN interlayers up to a thickness of 2.8 microns, however, shows a greatly improved quality without any cracking in the illustrated section.

5a ) shows an in-plane transmission electron micrograph of a GaN layer prepared by a prior art method. 5b ) shows an in-plane transmission electron micrograph of a GaN layer produced by a method according to the invention. The images show differently grown GaN layers with approximately the same scale. In the growth of in 5a ), no SiN masking layer was used. In the growth of in 5b In contrast, the process sequence according to the invention has been observed.

to Evaluation of the footage was the size of the one pictured Layer plane visible crystallites were estimated, and this was the recording circular or elliptical rings superimposed, the approximately the recognizable border of the coalesced crystallites consequences.

By way of illustration, it is added that dislocations in heteroepitaxy arise, first, as interface dislocation displacements, and secondly, as a result of most island growth. Islands grow stronger Mismatch of the crystal structures always slightly tilted or twisted. The tilting at the interface of two crystallites causes the formation of screw dislocations. The twist causes the formation of step dislocations at the interface of two crystallites. Accordingly, these dislocations occur at the boundary of two crystallists, precisely because of the coalescence process that occurs as the layer thickness increases. Only a few dislocations occur independently of these effects, for example directly from the interface to the substrate. Therefore, the detectable step and screw dislocations approximate the boundary of the coalescing crystallites because, if the adjacent crystallite is slightly misoriented, they decorate it. To check the average area of the crystallites, a layer plane at a distance of 700 ± 50 nm from the masking layer should be used.

From the ratio of the imaged area and the number of crystallites thus identified, an average area was determined which the crystallites occupy in the illustrated section plane. This section plane is above the coalescence layer thickness in both investigated samples. At the in 5a ) were counted on an area of 894 nm × 1195 nm = 1.0681 μm ² 38 crystallites. This gives an average area of 0.0281 μm ² per crystallite.

At the in 5b ) sample of a nitride semiconductor product according to the invention, however, were counted on a surface 2982 nm × 2238 nm = 6.67 microns ² 35 crystallites. This gives an average area of 0.19 μm ² per crystallite.

It should be noted that the examined sample of the 5b ) in quality at the lower edge of the achievable with the method according to the invention values. The process is preferably carried out such that the average area is at least 0.36 μm ² . In this way, the compressive stress in the GaN layer can be significantly increased, resulting in better results of the radius of curvature and the tensile stress in the finished device.

6a ) - 6f ) show different process stages in the production of a light emitting diode from the nitride semiconductor product of 1 , The procedure described here is followed by the production of the nitride semiconductor component of 1 at.

This is done on the nitride semiconductor product 100 initially provided a top side metallization. This serves on the one hand for subsequent bonding to a carrier 126 and on the other hand to improve the light extraction from the resulting device.

The carrier 126 is made of copper or AlSi and has on one side 128 used for bonding, a metallization 130 , 6b ) shows a process stage after bonding. The bonding is carried out at a temperature of 280 ° C. The use of such a low temperature has the advantage that no additional strains caused by the thermal cycle during bonding.

In a subsequent step, the Si wafer becomes 104 away. This is in 6c ) shown schematically. The Si wafer 104 is removed by grinding and etching. The etching can be wet or dry chemical. It arises so in the 6d ) structure in which the previously associated with the Si wafer Ankeimschicht 106 now the top forms and the p-cover layer 122 directly to the metallization 124 / 130 anknüpft. In a subsequent step, the top is patterned by etching. The etching, for example with KOH or H ₃ PO _4, results in pyramidal structures which improve the light extraction from the component. Finally, contact structures are created. For a flux polarity of the LED is a negatively poling contact 136 provided on the surface and a positive pole contact on the carrier.

The Layer growth is possible according to the invention on large substrates and allows either the production of large components or a cost-efficient Making a big one Number of smaller components. The described process control comes without the usual laser stripping when using sapphire substrates and is therefore easier and cheaper. Only for the production from backside contact and a structuring prior to the separation of the components Photolithography steps required.

The The above description shows that based on the growth method of the present invention for one Unstressed nitride semiconductor layer structure a particularly simple Processing in the further component manufacturing is possible. That way you can high-quality, but inexpensive components are manufactured.

In the process management different variants are possible. For example, the p-conductive cover layer 122 after at least 20 nm growth of p-GaN be provided with a SiN mask. The subsequent further growth of p-GaN occurs insular and does not lead to complete coalescence. This creates a rough surface and leads in the finished semiconductor device of 6f ) to a more homogeneous light emission upwards. The light is better decoupled, even if a less efficient antireflection coating is applied on top.

Claims (56)

A method of fabricating a layered structure of a nitride semiconductor device on a silicon surface, comprising the steps of: providing a substrate having a silicon surface; Depositing an aluminum nitride nitrile layer on the silicon surface of the substrate; Optionally: depositing an aluminum-containing nitride buffer layer on the nitride resin inlayer; Depositing a masking layer on the nitride shellimide layer or, if present, on the first nitride buffer layer; Separating a gallium-containing first nitride semiconductor layer on the masking layer, wherein the masking layer is deposited in such a way that separate crystallites grow together above a coalescence layer thickness in the deposition step of the first nitride semiconductor layer and have an average area of at least 0 in a layer plane of the coalesced nitride semiconductor layer perpendicular to the growth direction; Take 16 μm ² . The method of claim 1, wherein the masking layer is deposited with a layer thickness at the first in Form of growth islands growing first nitride semiconductor layer from a distance of at least 600 nm on average Masking layer to form at least 80% closed layer surface leaves. The method of claim 1 or 2, wherein the masking layer with a covering of the underlying Nitridankeimschicht or, if present, the first nitride buffer layer of at least 95% is deposited. Method according to one of claims 1 to 3, wherein the masking layer is deposited from silicon nitride. Method according to one of the preceding claims, in the duration of the deposition of the masking layer is chosen such that that in the deposition step of the first nitride semiconductor layer is a follower Measurement of the reflection intensity the growth surface with a wavelength of light of about 600 nm an oscillating intensity curve with increasing Oscillation amplitude shows that after at least 5 oscillation cycles reaches a then approximately constant maximum value. Method according to one of the preceding claims, in the deposition of the Nitridankeimschicht takes place on a (III) silicon surface. Method according to one of the preceding claims, in the first nitride semiconductor layer with a layer thickness of between 800 nm and 1600 nm is deposited. The method of claim 7, wherein on the first Nitride semiconductor layer an aluminum-containing nitride intermediate layer is deposited and in the latter layer a gallium-containing another, second nitride semiconductor layer is deposited. Method according to Claim 8, in which the sequence of steps the deposition of an aluminum-containing nitride intermediate layer and a gallium-containing further nitride semiconductor layer repeated carried out becomes. A method according to claim 8 or 9, wherein on the another nitride semiconductor layer a multi-quantum well structure is deposited from nitride semiconductor material. A method according to claim 10, characterized by depositing at least one further masking layer Silicon nitride immediately before depositing those of the others Nitride semiconductor layers on which the multi-quantum well structure is deposited. Method according to one of the preceding claims, in the one n-doping into the first and, if present, those further nitride semiconductor layers is deposited, which deposited in front of the multi-quantum well structure become. Method according to one of the preceding claims, with the steps: Producing a p-doped, gallium-containing Nitride semiconductor cap layer on the multi-quantum well structure. The method of any one of the preceding claims, wherein the step of providing a substrate includes providing a silicon substrate whose thickness is at least D _GaN x, where D _{GaN is} the layer thickness of the nitride semiconductor layer to be deposited on the substrate or if more than one nitride semiconductor layer is to be deposited , the sum of the layer thicknesses of the nitride semiconductor layers to be deposited on the substrate and the existing nitride intermediate layer, and wherein x in the case of using a doped silicon substrate 110 and in the case of using an undoped substrate 200 is. The method of claim 14, wherein at wherein the step of providing a substrate includes providing a silicon substrate, the thickness of which is additionally greater than or equal to

is, where

Method for producing a nitride semiconductor component, with the steps: - Production a layer structure of a nitride semiconductor device on a silicon surface according to any one of the preceding claims; - Bonding of the layer structure with a carrier such that the growth top of the layered structure faces the wearer is; - either complete or partially removing the substrate; - Production of a contact structure. A method according to claim 16, comprising a step of Depositing an electrically conductive contact layer on the Growth top of the layer structure. The method of claim 17, wherein for the contact layer a material is used which has a higher refractive index than the p-type nitride semiconductor cap layer. Method according to one of claims 16 to 18, with a vor the bonding performed Step of metallizing the growth top of the layered structure or, if present, the contact layer. A method according to any one of claims 16 to 19, wherein a carrier is used, the surface used for bonding electrically conductive or reflective or metallic. A method according to any one of claims 18 to 20, wherein the nitride semiconductor cap layer of the layered structure has a thickness of

is deposited, where m = 0, 1, 2, 3, ...; λ denotes a wavelength of a light emission of the multi-quantum well structure in the operation of the nitride semiconductor device, n _nitride, the refractive index of the nitride at the wavelength λ and d _MQW the thickness of the multi-quantum well structure. The method of claim 17, wherein for the contact layer a material is used that has a lower refractive index has as the p-type nitride semiconductor cap layer. The method of claim 22, wherein the nitride semiconductor cap layer of the layered structure has a thickness of

is deposited, where m = 1, 2, 3, 4, ...; λ denotes a wavelength of a light emission of the multi-quantum well structure in the operation of the nitride semiconductor device, n _nitride, the refractive index of the nitride at the wavelength λ and d _MQW the thickness of the multi-quantum well structure. A method according to any one of claims 16 to 23, wherein the Bonding takes place at a temperature in the range between 280 and 500 ° C. A method according to any one of claims 16 to 24, wherein the Step of removing the substrate by grinding or by combined grinding and etching he follows. A method according to any one of claims 16 to 24, wherein the Step of removing the substrate is carried out by etching alone. Method according to one of claims 26 to 25, wherein the growth back exposed by removing the substrate is structured to form an antireflective layer. A nitride semiconductor device comprising - a gallium-containing first nitride semiconductor layer having a structure of coalesced crystallites occupying an average area of at least 0.16 μm ² in a layer plane perpendicular to the growth direction, - an aluminum-containing nitride intermediate layer adjacent to the first nitride semiconductor layer, and, - adjacent to the latter layer, a gallium-containing further, second nitride semiconductor layer. A nitride semiconductor device according to claim 28, wherein the crystallites in a layer plane perpendicular to the growth direction have an average extension of at least 400 × 400 nm ² . A nitride semiconductor device according to claim 28, wherein the crystallites occupy an average area of at least 0.36 μm ² in a layer plane perpendicular to the growth direction. A nitride semiconductor device according to any one of claims 28 to 30, wherein the first nitride semiconductor layer has a layer thickness of between 800 nm and 1600 nm. A nitride semiconductor device according to any one of claims 28 to 31, the layer sequence of aluminum-containing nitride intermediate layer and gallium-containing further nitride semiconductor layer contains. A nitride semiconductor device according to any one of claims 31 or 32, in which on the further nitride semiconductor layer of a multi-quantum well structure Nitride semiconductor material is deposited. Nitride semiconductor component according to claim 33, characterized by at least one further masking layer of silicon nitride immediately adjacent to that of the further nitride semiconductor layers, on which the multi-quantum well structure is deposited, however on the side away from the multi-quantum well structure of this further Nitride semiconductor layer. A nitride semiconductor device according to any one of claims 28 to 34, in which the first and, if present, those other nitride semiconductor layers are n-doped, the are arranged on the side of the multi-quantum well structure, the facing the first nitride semiconductor layer. A nitride semiconductor device according to any one of claims 33 to 35, with a p-doped, gallium-containing nitride semiconductor cap layer, the side facing away from the first nitride semiconductor layer the multi-quantum well structure, is arranged. Nitride semiconductor component according to one of the claims 28 to 36 with a carrier, which is connected to the first nitride semiconductor layer. A nitride semiconductor device according to any one of claims 28 to 37, where the carrier and the first nitride semiconductor layer via a metal layer with each other are connected. A nitride semiconductor device according to claim 37 or 38, where the carrier essentially of copper or aluminum or silicon or aluminum nitride or Al / Si. A nitride semiconductor device according to any one of claims 28 to 39, in which between the carrier and the first nitride semiconductor layer is an electrically conductive contact layer is arranged. A nitride semiconductor device according to claim 36 and Claim 40, wherein the contact layer has a higher refractive index than the p-type nitride semiconductor cap layer. The nitride semiconductor device according to claim 36, wherein the nitride semiconductor cap layer of the layered structure has a thickness of

is deposited, where m = 0, 1, 2, 3, ...; λ denotes a wavelength of a light emission of the multi-quantum well structure in the operation of the nitride semiconductor device, n _nitride, the refractive index of the nitride at the wavelength λ and d _MQW the thickness of the multi-quantum well structure. A nitride semiconductor device according to claim 36 and Claim 40, wherein the contact layer has a lower refractive index has as the p-type nitride semiconductor cap layer. The nitride semiconductor device according to claim 43, wherein the nitride semiconductor cap layer of the layered structure has a thickness of

has, where m = 1, 2, 3, 4, ...; λ denotes a wavelength of a light emission of the multi-quantum well structure in the operation of the nitride semiconductor device, n _nitride, the refractive index of the nitride at the wavelength λ and d _MQW the thickness of the multi-quantum well structure. A nitride semiconductor device according to any one of claims 28 to 44, with an n-side and a p-side electrical contact element. carrier disc with a plurality of nitride semiconductor components according to one of claims 28 to 45. carrier disc The device of claim 46, wherein said plurality of nitride semiconductor devices on the carrier in its entirety a lateral extent of at least 24 cm has. A nitride semiconductor product comprising a substrate having a silicon surface, an aluminum-containing nitride core layer adjacent to the silicon surface, optionally an aluminum-containing nitride buffer layer adjacent to the nitride bank layer, a masking layer on the nitride bank layer or, if present, on the nitride buffer layer, and with one gallium-containing first nitride semiconductor layer disposed adjacent to the masking layer and having a structure of coalesced crystallites, wherein the crystallites occupy an average area of at least 0.16 μm ² above a coalescence layer thickness and in a layer plane perpendicular to the growth direction. A nitride semiconductor product according to claim 48, wherein the growth islands at a distance of at least 600 nm from the masking layer is at least 80% coalesced. A nitride semiconductor product according to any one of claims 48 or 49, wherein the Nitridankeimschicht an aluminum nitride layer or an aluminum gallium nitride layer having an aluminum content of at least 10%. A nitride semiconductor product according to claim 50, wherein the Nitridankeimschicht a layer thickness of between 10 and 100 nm has. A nitride semiconductor product according to any one of claims 48 to 51, wherein the nitride buffer layer has a maximum layer thickness 400 nm has. A nitride semiconductor product according to any one of claims 48 to 52, in which the substrate in a perpendicular to the rear substrate surface Direction either curvature free is or a radius of curvature of at least 10 m. A nitride semiconductor product according to any one of claims 48 to 53, with an aluminum-containing nitride intermediate layer attached to the adjacent first nitride semiconductor layer, and, - adjacent to the latter layer, a gallium-containing further, second nitride semiconductor layer. A nitride semiconductor product according to any one of claims 48 to 54, wherein the crystallites occupy an average area of at least 0.36 μm ² in a layer plane perpendicular to the growth direction. A nitride semiconductor product according to any one of claims 48 to 55, wherein the substrate has a lateral extent of at least 24 cm.