WO2012035135A1

WO2012035135A1 - Semiconductor chip and method for producing the same

Info

Publication number: WO2012035135A1
Application number: PCT/EP2011/066084
Authority: WO
Inventors: Armin Dadgar; Alois Krost; Peter Stauss
Original assignee: Osram Opto Semiconductors Gmbh
Priority date: 2010-09-19
Filing date: 2011-09-16
Publication date: 2012-03-22

Abstract

The invention relates to a semiconductor chip (10) comprising a stack (2) of semiconductor layers, the stack (2) of semiconductor layers being based on a material system of the group III nitrides and having an n-doped layer (2b). The n-dopant used is a dopant that is heavier than silicon of the fourth main group or a dopant of the sixth main group of chemical elements. The invention further relates to a method for producing a semiconductor chip (10) of the above type.

Description

description

The invention relates to a semiconductor chip comprising a semiconductor layer stack based on a group III nitride and a method for the production thereof.

Conventionally, often layers of a

Semiconductor layer stack based on a group III nitride material system grown on a heterosubstrate such as sapphire, Sic or silicon. To generate an n-type conductivity in the layers of the semiconductor layer stack, these are often doped, with silicon being used as the n-dopant, which has established itself as an easy-to-handle and efficient dopant. However, such a doping may be a tenile

Lead stress in the semiconductor layer stack, which may adversely affect the semiconductor chip performance and may even lead to damage to the semiconductor layers of the stack. For example, damage to the layers of the stack may occur as damage. Such damage due to Si dopants are for example in the

Publication "Effect of doping on strain, cracking and microstructure in GaN thin films grown by metalorganic chemical vapor deposition", Romano et al. , J. Appl. Phys. , Vol. 87, No. 11, June 1, 2000.

The growth on silicon requires, if component-relevant layer thicknesses of more than 2 μπι or 3 μπι to be achieved, except for a Ankeimschicht and a lowermost buffer layer to about 500 nm thickness, a compressive

Preloading the layer to be grown. For example, you can growing a GaN layer stack on one

Silicon growth substrate, especially when doing

Applied cooling process, tensile stresses occur in the layers. Conventionally, such tensile stresses by means of a compressive

Preloading the Group III Nitrides

Semiconductor layer stack compensated during growth. Such Vorverspannungen are for example in the

Publication "GaN-based epitaxy on Silicon: stress measurements", Krost et al. , phys. stat. sol. (a) 200, No. 1, 26-35 (2003). This wanted compressive

Preload, however, is disadvantageous at a high

Doping the layers with silicon degraded, so

Again, during the cooling process of the layers, a cracking of these layers can occur.

By contrast, when GaN layers are grown on a sapphire substrate, a compressive one is created during the cooling process

Tension due to the thermal mismatch of

Materials. However, a high Si doping and / or a high layer thickness of the n-doped layers of the

Layers stack already lead to a crack in the epitaxial layers due to the resulting tensile stress during deposition.

However, thick and heavily doped layers are a prerequisite for efficient light emitters, for example, which are to be produced on inexpensive silicon substrates which are available over a large area. In addition, thick and heavily doped layers are found for electronic components such as p-i-n or Schottky transistors for high voltage applications

Use . Although it is possible in principle to reduce the tensile stresses in such semiconductor chips, it requires a great deal of effort. The reason for this is the typically high dislocation density of greater or about 1 x 10 ^ cm ^-2

By adding Si of greater than or equal to about 1 × ΙΟ cm -1, an already built-in compressive stress is reduced by bending the dislocations, or even a

generates additional tensile stress. This effect is described inter alia in the publication "Si doping effect on strain reduction in compressively strained A10.49 Ga0.51N thin films", Cantu et al. , Appl. Phys. Lett., Vol. 83, No. 4, July 28, 2003.

Si is used as a dopant, in particular, since silane as the starting material for the silicon doping has a low price and the simple use of silane makes the use of elements other than dopant as unnecessarily complicated. Also with regard to a reduction of the bracing problem could be seen so far no advantages of other group IV dopants, since the chemistry of the substances is very similar and therefore the same problems can be expected.

However, a high doping is necessary inter alia for a good contact formation, with electron concentrations above 5 x ΙΟ ^ cm ^ are striven for.

The growth of GaN layers on a heterosubstrate generally results in an increased dislocation density within the GaN layers. To reduce these dislocation densities, inter alia SiN _x masking layers are found

Use. Such masking layers are among others also known by the term "in situ SiN". Masking layers "known and for example in the

Publication "Anti-Surfactant in III-Nitride Epitaxy - Quantum Dot Formation and Dislocation Termination", Tanaka et al., Jpn. J. Appl. Phys. , Vol. 39 (2000), PI. 2, No. 8B. Such a masking layer is in this case partially applied after it has grown at least a first group III nitride layer of the semiconductor layer stack. The masking layer is typically applied by a reaction of silicon with nitrogen (ammonia as a source). In a suitably thinly deposited layer, the person skilled in the art can achieve that a SiN layer which is only partially formed is formed. In a further GaN deposition step, a further GaN layer is produced starting from the non-SiN-covered regions. This first grows in a 3-dim island structure on the material of the nucleation-free areas of the first GaN layer and spreads with increasing

Growth time in the lateral direction over the SiN masking layer. In this area is the

Dislocation density significantly reduced.

If the second GaN layer is doped with Si for improved electrical conductivity, the parasitic reaction of silicon with nitrogen to form SiN can also occur, so that here too only a partial overgrowth takes place, and a desired fast

Coalescence of the growth islands to a closed

dislocation-reduced layer is hindered, or, depending on the process, the coalescence emanates unwanted germs newly forming on the SiN mask.

It is an object of the present application to provide an improved semiconductor chip, which has a high n-type doping and at the same time a reduced risk of tearing the

Has layers of the semiconductor chip. It is also an object of the present application, a production process

to grow a GaN layer on a growth substrate with a high degree of n-type doping, in which the

Danger of damage to the GaN layer is reduced and in addition a rapid coalescence of a GaN layer

following a possibly applied masking layer is not adversely prevented.

These tasks are among others by a

Semiconductor chip having the features of claim 1 and by a method for producing such a semiconductor chip having the features of claim 10. advantageous

Further developments of the semiconductor chip and the method for its production are the subject of the dependent claims.

In one embodiment, the semiconductor chip has a

Semiconductor layer stack based on the group III nitride material system and having at least one n-type doped layer. As n-dopant becomes a heavier

Dotand as silicon from the IV. Main group or a dopant from the VI. Main group of chemical elements used. The semiconductor chip is preferably used for

electronic application and preferably has highly conductive or highly doped n-layers in the GaN

Semiconductor layer stack on. In particular, the

Semiconductor layer stack on Al _n In _] __ _n _ _m Ga _m N with preferably 0 <n <0.2 and / or 0.35 <m <0.95 and / or 0 <1-nm <0.5 or consists thereof, wherein dopants of said molecular formula are not included and thus in

Semiconductor layer stack may be included in addition. In a middle layer with a thickness of up to 50 nm, it may be different from the above-mentioned values for n, m and instead that 0.75 <n <1.

In the context of the application, an n-doped layer based on the material system of the group III nitrides can also be understood to mean an n-doped substrate which is deposited on the substrate

Group III nitride material system based, so

for example on GaN. In this case, the

Semiconductor chip thus at least as semiconductor layer stack on the n-doped substrate on which further layers may be applied.

In a development, the semiconductor chip is a

optoelectronic semiconductor chip. In this case, the semiconductor chip has an active layer provided for the generation of radiation between the n-doped layer and a p-doped layer. An optoelectronic semiconductor chip is, in particular, a semiconductor chip which enables the conversion of electronically generated data or energies into light emission or vice versa. For example, the

Optoelectronic semiconductor chip, a radiation-emitting semiconductor chip.

When using a dopant for n-doping as claimed, advantageously the undesirable effects discussed above concerning the tensile strain and / or the parasitic reaction do not occur. In particular, by means of a dopant as claimed dopant tensile stress during the cooling process and / or the

occurring tensile stress due to the high n-type doping as well as only partial overgrowth due to reduced or prevented a high silicon content.

In addition, it is possible to use the n-doped layer or layers of the semiconductor layer stack with improved n-type doping.

Conductivity accordingly thin to separate. With the

claimed dopants can thus be a thin and

highly doped n-layer can be produced. The use of a dopant as claimed thus leads to a reduction in the cracking and damage of the n-layer of the semiconductor layer stack in contrast to

Use of silicon as dopants. In addition, a thick highly n-doped group III nitride layer can be realized on a sapphire, silicon carbide or silicon substrate. In this case, the dopant must be heavier or larger than silicon so that it does not act as an amphoteric dopant or as a p-dopant. Alternatively, group VI dopants are suitable. The active layer of the semiconductor layer stack preferably contains a pn junction, a double heterostructure, a single quantum well (SQW, single quantum well) or a

Multiple quantum well structure (MQW, multi quantum well) for generating radiation. The term quantum well structure unfolds no significance with respect to the

Dimensionality of quantization. It includes, among other things, quantum wells, quantum wires and quantum dots, and each one

Combination of these structures. Based on a material system of group III nitrides means here and below that the

Semiconductor layer sequence of the semiconductor layer stack epitaxially deposited on a growth substrate Layer sequence, which has at least one layer of a nitride II I compound semiconductor material,

preferably Al _n Ga _m _In] __ _ _n _m N, where 0 <n, m <1, n + m <. 1

This material does not necessarily have to have a mathematically exact composition according to the above formula. Rather, the material may comprise one or more dopants as well as additional constituents which the

characteristic physical properties of the

Al _n Ga _m _In] __ _ _n N _m change material does not substantially. For the sake of simplicity, however, the above formula contains only the essential constituents of the crystal lattice (Al, Ga, In, N), even if these may be partially replaced by small amounts of other substances. In a development, the n-dopant is Ge, Sn, Pb, O, S, Se or Te. In this case, therefore, as n-dopant a

heavier dopant from the IV. Main group of chemical elements as silicon, so Ge, Sn or Pb, find use. As Dotand from the VI. Main group finds

for example, 0, S, Se or Te use. These dopants do not show the undesirable effects of the prior art, since these dopants are not for turning or the

Contribute to migration of dislocations and thus promote a tensile strain.

In a further development, in addition to Ge, silicon is also used as n-dopant. The n-doped layer is therefore doped in this case with Ge and Si. Thus, the tensile strain and the doping can be influenced independently.

In a development, the dopant concentration of the n-dopant in the n-doped layer is greater than ₁₀ 19 l / CNW. So it becomes an n-doped layer on one

Growth substrate grown with a high dopant concentration. So can a thin and at the same time

highly doped n-doped layer can be realized.

In a development, the semiconductor chip is an InGaN LED. The semiconductor chip is preferably a thin-film chip. When

Thin film chip is considered in the context of the application, a semiconductor chip during its production, the growth substrate on which the semiconductor layer stack epitaxially

grew up, preferably completely detached. The semiconductor layer stack of the semiconductor chip can be applied, for example, on a carrier substrate. The carrier substrate used is preferably a silicon-containing material

Carrier substrate provided, in particular when already the growth substrate is a silicon-containing substrate.

In one development, the semiconductor chip and / or the semiconductor layer stack has a single-sided electrical

Contacting on. In other words, the semiconductor chip can then be a flip-chip. It is also possible that an electrical contact is constructed, as in the

Reference US 2010/0171135 AI or WO 2011/006719 AI specified, the disclosure of which by reference

is recorded. The n- and p-doped layers of the

Semiconductor layer stack are thus one-sided, ie

For example, only from a back of the

Semiconductor layer stack electrically contacted.

Alternatively, the electrical contact of a

Front of the semiconductor layer stack done. For electrical contact are on one side of the

Semiconductor layer stack arranged a first and second electrical connection layer, each for electrical Contacting the layer stack of a conductivity type are provided. The first and second electrical

Connection layer are electrically isolated from each other, for example by means of an electrically insulating separation layer.

The one-sided contacting technology of the chip allows a low-resistance contact. Because of the one-sided

Arrangement of the contacts can advantageously the full functionality of the epitaxial layers of

Semiconductor layer stack, in particular the active layer can be ensured.

In a development, the dopant concentration of the n-type dopant in the n-doped layer fulfills the following

Condition:

D x DIS _Edge x N> 5 x 10 ²³ cm ^-4, with D the thickness of the n-doped layer in cm, DIS ^^ g _g the average dislocation density-scale content in the n-doped layer in cm ^-2 and with a value above 1 × 10 -4 cm ^-2 , N of the dopant concentration in the n-doped layer in cm ^-3 .

In this case, D is in particular the layer thickness of the entire n-doped layer and optionally also subsequent thereto

Layers, but maximum up to one next

Stress compensating layer. In particular, N is a highest donor concentration in the n-doped layer.

It is also by a thin n-doped layer with a Thickness D of at least 100 nm produces strong tensile stress at high dislocation concentrations.

Since such a tensile stress even after reducing the

Dopant concentration is maintained, it is not crucial that the entire n-doped layer

is highly doped, but that at least partially relatively highly doped and / or a high stage ^¬ dislocation concentration is present. Such a high one

Doping is slightly less advantageous at the beginning of the n-doped layer than seen at the end in the growth direction, since the reduced stress in the growing layer has a stress-reducing effect on a thicker part of the layer than at the end.

This n-doped layer is preferably at least 0, 6 μπι thick and has approximately on the upper at least 400 nm

Electron concentration of at least 5xl0 ¹⁸ cm ^J on.

Especially due to the strong lattice mismatch

Growth process on silicon is the

Step dislocation density typically above 2x10 ⁹ cm ^. This results from the formula according to claim 1, a value of

6xl0 ²³ . According to at least one embodiment of the semiconductor chip, the thickness D is between 300 nm and 5 μπι, in particular between 0.4 μπι and 3 μπι or between 0.5 μπι and 2.0 μπι inclusive. DlS ^^ g _g lies to

Example between 5 x 10 ⁷ cm ^Δ and 109 cm ^ inclusive or between 9 x 10 ⁷ cm ^Δ and 5 x 10 ° cm ^Δ . The concentration N can be between 1 x 10 ¹⁸ cm ^J and 1 x 10 ^(J cm or ^J is between 7 x 10 ^IÖ cm 3 and 5 x 1θ19 cm ^_ lie. 3

According to at least one embodiment of the semiconductor chip, the lower limit for the expression D x DlSßdge ^x N is a

Value of at least 1 x 10 ^ 3 cm ^ or at least

5 x 10 ^ 3 cm ^" ^ or of at least 1 x 10 ^ 4 cm ^ or

Upper limit may alternatively or additionally at most

5 x 10 ^ 6 cm ^~ 4 or at most 1 x 10 ^ 6 cm ^.

The above condition can be used as a criterion for the meaningful

Use of an unusual and as claimed dopants in highly doped group III nitride layers compared to the normally used silicon can be seen. These layers can be heteroepitactic on sapphire, sic or silicon, but also homoepitaxial on group III nitride substrates, which have a correspondingly high

Dislocation density of, for example, greater than 5 x 10 ^ cm ^~ 2 grown.

According to at least one embodiment of the semiconductor chip, the latter comprises a highly n-conductive layer, in particular based on GaN, this layer preferably following an in situ or ex situ masking layer.

According to at least one embodiment of the semiconductor chip, the highly n-conductive layer, which is applied to the

Masking layer follows, an n-doping above lO-L ^ cm ^_ 3 or δχΐθ ^ cm ^_ 3 on. This n-doping takes place in particular over a layer thickness of 10 nm to 300 nm inclusive. By using the dopants according to the invention, a high n-type doping can be realized, without appreciably hindering or delaying subsequent coalescence, as would be the case with Si doping, since Si promotes three-dimensional growth and thus a two-dimensionally growing layer is difficult to achieve, usually only after the growth of very thick layers.

According to at least one embodiment of the semiconductor chip, the masking layer comprises or consists, for example, of SiN, SiO, SiON or BN or another material which does not or only inhibits wetting, which promotes three-dimensional growth, and / or growth conditions which are independent of such do a masking layer. One way to accomplish this is to add a heavy doping "10 ^ - ^ cm - ^ approximately Si, over one

Layer thickness of 10 nm to 300 nm provided.

According to at least one embodiment of the semiconductor chip, the masking layer has a thickness of at most 2 nm, in particular of at most 1 nm. For example, the thickness of the masking layer is on average one or two monolayers. Masking layers are described in the publication "Anti-Surfactant in III-Nitride Epitaxy - Quantum Dot

Formation and Dislocation Termination ", Tanaka et al., Jpn. J. Appl. Phys., Vol. 39 (2000), PI. 2, No. 8B, the disclosure of which is incorporated by reference.

According to at least one embodiment of the semiconductor chip, a coverage of the masking layer is between 20% and 80% inclusive, or between 55% and 70% inclusive of the underlying layer. In other words, the growth substrate and / or the growth layer, seen in plan view, to the said portion covered by a material of the masking layer.

According to at least one embodiment of the semiconductor chip, the latter has a coalescing layer which is the one of the coalescing layer

Masking layer in particular immediately follows and in which the coalescence takes place, starting from openings in the masking layer. This layer is in particular a GaN layer. A thickness of this

Coalescing layer is preferably between inclusive

300 nm and 3 μπι, in particular between 400 nm and 1.2 μπι. The coalescing layer may be undoped or substantially undoped. According to at least one embodiment of the semiconductor chip, the latter comprises a middle layer which is based in particular on AlGaN. An Al content of the middle layer is preferably between 75% and 100% inclusive. A thickness of

In particular, the middle layer is between 5 nm and 50 nm inclusive, for example between 10 nm and 10 nm inclusive

20 nm. The middle layer may be between the high n-type layer and the masking layer. In particular, the middle layer directly adjoins the highly n-conductive layer and the coalescing layer.

Detection of the dopant (s) in the semiconductor chip can be carried out, for example, by a secondary ion mass spectrometry analysis (SIMS for short). In this are

Masking layers detectable or existing at large islands of the masking layer usually on a micrometer scale doping fluctuations due to a

facet-dependent incorporation of the dopants and associated slight concentration fluctuations. Such inhomogeneities For example, cross-cathodoluminescence or cross-section transmission electron microscopy cathodoluminescence can also be determined by the different positions of donor-bound

Excitons or a line broadening of a luminescence can be detected, even if the masking layer is removed, for example by an etching process.

According to at least one embodiment of the semiconductor chip, a thickness of the semiconductor layer stack is at least 1 μπι or at least 2 μπι and / or at most 10 μπι or at most 5 μπι. This may be necessary to functional

Layers such as an active layer accommodate, and / or to realize a contact and current spreading and / or to ensure sufficient isolation to the growth substrate.

Due to the comparatively large layer thickness

For example, in the case of silicon for the growth substrate at such thicknesses a voltage compensation by

Biasing a majority of the grown up

Semiconductor layer stack preferred. This can be achieved for example by graded Al-containing

Interlayers having Al content decreasing in the direction away from the growth substrate, by AlN layers or by a superlattice of Al-rich and Al-poor layers. It can be the interlayer between one and eight

Partial layers comprise, in particular between two and five partial layers inclusive. A thickness of the intermediate layers as a whole is, for example, between 20 nm and 500 nm inclusive, in particular between 50 nm and 250 nm inclusive. According to at least one embodiment of the semiconductor chip, the seed layer, which is based in particular on AlN, and / or also a GaN layer grown directly thereon, is doped. A doping of the seed layer, which can also serve as a buffer layer, takes place in particular with silicon or with

Oxygen. A dopant concentration is

for example, between and including 5 x 10 ¹⁸ cm ^J and

5 x 1021 cm ^J or between including 2 x ₁₀ 19 cm ^J and

2 x ₁₀ 20 cm ^J. Likewise, the seed layer indium in a proportion of up to 20% or up to 10%. Silicon or sapphire is particularly preferably used as the growth substrate.

Due to the high dislocation density of> 5xl0 ⁹ cm ^ in particular at the beginning of heteroepitactic growth, without the

Generation of significant tension, usually no high carrier concentration can be achieved and thus no low contact resistance to the silicon substrate.

By using the dopants according to the invention as a substitute for Si, the stress is reduced to a lesser extent

reducible and there are semiconductor chips on silicon-containing

Substrates enabled.

In addition, a method for producing an optoelectronic semiconductor chip is specified. For example, by means of the method, a semiconductor chip can be produced, as described in connection with one or more of the abovementioned embodiments. Features for the method are therefore also disclosed for the semiconductor chip and vice versa.

A method for producing a semiconductor chip comprises the following method steps: Providing a growth substrate,

epitaxial growth of a semiconductor layer stack based on a material system of the group III nitrides and having at least one n-doped layer, wherein as n-dopant a heavier dopant than silicon from the IV. Main group or a dopant from the VI. Main group of chemical elements is used.

Such a method allows the growth of GaN layers on, for example, a silicon substrate with a high degree of n-doping, in which the strain in the

Essentially not influenced by the doping. In addition, it is possible to match the n-doped layer or layers of the semiconductor chip with improved n-type conductivity! to separate thinly. Thus, a thin and at the same time highly doped n-layer can be produced. In this case, a silicon-containing substrate can be used as the growth substrate, which is advantageously inexpensive. Furthermore, in such a method with additional

Use of a SiN masking layer for

Dislocation reduction the subsequent coalescence

advantageously not adversely affected.

It is possible with the described method, the complex and not always necessary by the component requirements

Reduction of stage dislocations or their

Dislocation migrations, which cause the tensile stress in doping significantly bypass and still highly doped

Create layers.

According to at least one embodiment of the method, a pressure-stressed GaN layer on the growth substrate, in particular a silicon substrate, is formed during the growth is grown with a high n-type doping at a relatively high dislocation density, wherein the compressive stress is not or not substantially affected by the doping, through the use of a heavier dopant such as Ge, Sn, Pb, O, S, Se or Te. It turns out that these elements do not show the undesirable stress-relieving effect, since they apparently do not contribute, or only slightly, to dislocation migration.

According to at least one embodiment, the method finds application for the generation of homoepitaxial

Device layers on group III nitride buffer layers.

In a further development, the growth substrate is an SOI substrate ("silicon on insulator" substrate). Alternatively, the growth substrate may be a sapphire or SiC substrate.

In a development, a germanium-hydrogen compound, an organic germanium compound, tert. butyl german, tert. butyl-tin, tert. -butyl-lead, an organometallic compound of the type F4_Me with R one

organic residue in gas phase epitaxy or a

Connection from the VI. Main group used with hydrogen or an organic radical.

The doping with germanium is to be preferred over the other elements, since the available precursors are easy to use and the vapor pressure of the dopant above the layer at the most prevalent in the group III nitride epitaxy process temperatures above 1000 ° C well controlled is. The other precursors are up

Oxygen in the process, however, not so easy to handle. Oxygen, in turn, may be involved in the epitaxy process be undesirable because it is considered the main contaminant and

at least in organometallic gas phase epitaxy also undesirable reactions with the organometallic

Can trigger connections and therefore a potential

Represents safety risk in hydrogen-rich processes.

The features mentioned in connection with the semiconductor chip also apply to the method and vice versa.

Further advantages and advantageous developments of

Invention will become apparent from the embodiments described below in conjunction with Figures 1 to 3. Show it :

FIGS. 1, 2A, 2B, 2D each show a schematic cross section of an exemplary embodiment of a semiconductor chip according to the invention,

Figure 2C is a diagram in which the tension against the

Production time is applied,

FIG. 3 is a flowchart relating to an inventive device

Manufacturing process, and

Figures 4 to 6 are schematic cross-sectional views of further embodiments of

inventive semiconductor chips.

In the figures, the same or the same effect

Each component be provided with the same reference numerals. The illustrated components and their

Size ratios among each other are basically not to be considered as true to scale. Rather, individual can Components, such as layers, structures,

Components and areas to be shown exaggerated thick or large dimensions for better presentation and / or for better understanding.

FIG. 1 shows an embodiment of a semiconductor chip 10 in cross section. The semiconductor chip 10 has a

Growth substrate 1 having, for example, sapphire, Sic or silicon. The growth substrate may also be a silicon on insulator (SOI) substrate or a group I I nitride substrate.

On the silicon-containing growth substrate 1 are the

individual layers 2a, 2b, 2c of the semiconductor layer stack 2 grown. The semiconductor layer stack 2 is based on a group III nitride material system. Preferably, the semiconductor layer stack 2 is based on the

Material system InGaN. The semiconductor layer stack 2 has an active layer 2 a. The active layer 2a is

suitable during operation of the semiconductor chip 10th

to generate electromagnetic radiation. Preferably, the semiconductor chip 10 is an LED ("light-emitting diode").

The active layer 2 a of the semiconductor layer stack 2 is arranged between an n-doped layer 2 b and a p-doped layer 2 c. The n-doped layer is in

Embodiment of Figure 1 directly on the

Growth substrate 1 applied. Alternatively, the n-doped layer may be covered by a masking layer and

Coalescing be applied to the growth substrate 1 (not shown). The n-doped layer 2b has a heavier dopant than silicon from the IV. Main group or a dopant from the VI. Main group of chemical elements. As n-dopant of the IV. Main group is thus Ge, Sn and Pb use. As Dotand the VI. Main group finds

for example, 0, S, Se or Te use.

The dopant concentration of the n-dopant in the n-doped layer 2b is preferably greater than 5 × ΙΟ 1 / cm 2. Advantageously, due to the choice of the dopant, the tensile strain of the semiconductor layer material which conventionally occurs during the cooling process or which occurs due to the dopant concentration can be avoided. Layers with such a high doping are particularly advantageous for a high transverse conductivity and optimized contact resistance. It is also possible, the n-doped layer 2b with improved n-conductivity

correspondingly thin to deposit or to make the n-contact surfaces with improved contact resistance correspondingly small.

The n-doped layer 2b and the p-doped layer 2c of the semiconductor layer stack 2 may be composed of a layer sequence. In this case, the

Semiconductor layer stack 2 a plurality of n-doped

Layers 2b, which are arranged between growth substrate 1 and active layer 2a. In this case, a plurality of p-doped layers can be arranged on the side of the active layer 2 a facing away from the growth substrate 1.

The dopant concentration of the n-dopant in the n-doped layer or the n-doped layers 2b preferably satisfies the following condition: D x DIS _Edge x N> 5 x 10 ^Ζό cm ^-4, where D is the layer thickness of the n-doped layer 2a or the sequence of layers of the n-doped layer, DIS ^^ g _g is the average dislocation density levels proportion in the range of n- doped layer 2b or the n-doped layers in cm-2 with a value above 1 x 10 ^ cm- ^ and N the

Dopant concentration in the n-doped layer 2b or the n-doped layers in cm- ^.

Due to the choice of the n-dopant, it is advantageous to avoid tensile stresses in the semiconductor chip, wherein at the same time a thick and highly doped group III nitride layer on silicon, sapphire or SiC can be realized. With such a heavy n-dopant can thus be the time-consuming and not always necessary reduction of the dislocations, the tensile stress at

Discharge to trigger, be circumvented, where

highly doped layers can be produced.

The semiconductor chip 10 advantageously has a

one-sided electrical contact on. This means that a first and second electrical connection surface on

the same side of the semiconductor chip 10 are arranged and from each other, for example by means of an insulating

Separating layer are electrically isolated from each other.

By using an n-dopant, which is heavier than silicon, can be a large-scale, cost-effective and

low-defect epitaxy and semiconductor chip processing on silicon substrates. In particular, you can thick n-doped layers are produced which have a reduced mechanical damage such as

Have cracking. Thus, an improved method and a semiconductor chip with improved properties can be achieved.

In Figure 2A, another embodiment of a

Semiconductor chips shown in cross section. Of the

Semiconductor chip 10 of FIG. 2A differs from the semiconductor chip of FIG. 1 by additional layers 3, 4 which are arranged between growth substrate and semiconductor layer stack 2. In particular, a buffer layer 3 is applied to the growth substrate 1. Such buffer layers 3 are in particular for growing on silicon-containing

Substrates 1 used. On the buffer layer 3, an aluminum-containing intermediate layer 4 is arranged, on which the layers of the semiconductor layer stack 2 are epitaxially grown. The aluminum-containing layer is

for example, an AIN seed layer. Such

Germ layer also grows up

used silicon-containing growth substrates.

Incidentally, the embodiment of FIG. 2A is identical to the embodiment of FIG.

In Figure 2B is another embodiment of a

Semiconductor chips shown in cross section. Of the

Semiconductor chip 10 of Figure 2B differs from the semiconductor chip of Figure 1 by additional layers 5, 6, 7, between the growth substrate and

Semiconductor layer stack 2 are arranged. In particular, a first group III nitride layer 5 is applied to the growth substrate 1. On this is a partial SiN masking layer 6 is arranged. Subsequently, the second group III nitride layer 7 is arranged, in such a way

in that it has a lower dislocation density than the first group III nitride layer 5.

Subsequently, the layers of the semiconductor layer stack 2 are epitaxially grown.

Incidentally, the embodiment of FIG. 2B is identical to the embodiment of FIG.

FIG. 2C shows a diagram in which

Manufacturing process the tension against the time of

Manufacturing process is applied. The dashed line shows the production of a semiconductor chip with an n-dopant silicon, the solid line shows a semiconductor chip with an n-dopant Ge.

The method relates, for example, to the production of a semiconductor chip according to the exemplary embodiment of FIG. 2A.

The graph of Figure 2C shows the curvature measurement during the growth of a silicon-doped GaN layer

(dashed line) and a Ge-doped GaN layer

(solid line) on a silicon substrate. After the growth of a buffer layer 101, compression is produced by an Al-containing intermediate layer in the subsequent GaN layer 102, which can be seen in particular from the change of the curvature to negative values. During doping 103, the curvature in Ge doping is virtually unchanged. The slight decrease shown in the diagram is common in the growth process. In the case of silicon doping, the curvature decreases, which indicates a tension-strained growth. The silicon-doped layer can therefore be after the Cooling be severely torn while the Ge-doped

Layer despite a high n-doping advantageously remains crack-free.

As shown in the diagram, the semiconductor layers with silicon in the later manufacturing process, in particular at about 60 minutes and more, have a lower stress than when doping with German and consequently a higher tensile stress after the cooling process (80 min). By means of a dopant such as German can thus be a mechanical damage to the layers, which can occur due to these occurring stresses are reduced.

The production method for the diagram of FIG. 2C can comprise the following method steps:

In time interval 101, in a growth chamber,

For example, a MOVPE reactor, a wet-chemical

placed cleaned and deoxidized silicon substrate and heated to about 730 ° C. This is followed by the supply of an aluminum precursor and ammonia. After the growth of about 25 nm AlN, the sample is heated to 1050 ° C under further flow of ammonia and by feeding a

Gallium precursors the growth of a GaN layer of the

Semiconductor layer stack started. As a result, a 0.7 μπι thick GaN layer is prepared, which has an electron concentration of 5 x 10 ¹⁸ cm ^J on the upper 500 nm. Due to the growth process is the

Step dislocation density typically above 2 x 10 ⁸ cm ^-2 . Using the condition D x DI SEDQJ XN> 5 X

10 ²³ cm 4 results in a value of 5 x 10 ²⁶ . This is

Germanium as a dopant diluted in hydrogen advantageous suitable. Through the use of this dopant can be a

Cracking in the GaN layer on the

Silicon growth substrate can be avoided. The dilution of German in hydrogen is usually lower than for silane in hydrogen, because the installation in comparison

is more inefficient and unlike Si doping is more vapor pressure driven. For example, a dilution of 1% to 1% GeH4 in H2 is possible.

An alternative manufacturing method to the diagram of Figure 2C can be performed as follows:

On a AIN seed layer is highly doped and grown directly on a GaN layer. By a high dislocation density of greater than 5 x 10 ^ cm ^~ 2 at the beginning of the heteroepitaxial growth can be without the production of a significant

Strain a high carrier concentration can be achieved and thus a low contact resistance to

Silicon substrate are made possible. In order _to realize in the doping electron concentration of 5 x ΙΟ ^ cm ^, is located on the first 100 nm with dislocation densities of greater than 5 x 10 ^ cm ^~ 2, the calculated according to the above condition

Value greater than 2.5 x 10 ^ 7 cm ^. Due to a dopant, which is heavier than silicon, the tension with

Advantage can be reduced to a lesser extent.

Another application is the growth of thick n-doped Group III nitride layers, mostly by means of HVPE, on a carrier substrate for the production of pseudo-substrates which, detached from the carrier substrate, serve as high-quality substrates for hetero and homoepitaxy: In this case, a strong inhomogeneous curvature usually occurs for conductive substrates heavily doped with Si, which curvature is shown by later abrasion of the substrate pointing to the growth substrate

Layer is reduced. Add to that the difficulty that comes from the doping and the associated strong

Tensile stress can occur during growth to cracking. Furthermore, a low dislocation density is usually achieved by forced 3D growth, either by the ELOG method, by means of in situ deposition

Mask layers, which are usually made of SiN, or achieved by a low seeding density, which leads to a 3D growth. The subsequent coalescence is influenced by the doping with Si by the parasitic SiN layer formation in an undesirable manner. If, instead of silicon doped with a dopant according to the invention, the resulting tensile stress at the beginning of the growth can be reduced and realized in three-dimensional island growth of this uninfluenced and thus simpler than n-doped layer. This subsequently avoids cracks during growth and provides for less

Substrate curvature of detached from the growth substrate

Pseudosubstrate after growth.

A further exemplary embodiment of the semiconductor chip 10 with a masking layer 6 is shown in FIG. 2D. On the substrate 1, for example of sapphire, Sic or silicon, the approximately 20 nm thick seed layer 5 is grown from A1N. In the case of silicon as a growth substrate, the thickness of the seed layer 5 is preferably between 100 nm and 250 nm, for example approximately 150 nm. This is followed by an n-type doped intermediate layer 4 made of GaN. After about 300 nm growth growth is interrupted and with simultaneous supply of ammonia and silane is the Masking layer 6 applied from SiN. This in turn is followed by the growth of the GaN layer 2b of the

Semiconductor layer stack 2.

This growth is initially three-dimensional, as evidenced by the onset of reflected intensity in in situ reflectometry measurements, for example. After several hundred nanometers of growth of the GaN layer 2b, this intensity increases until it reaches a maximum value again and the layer is thus closed in two dimensions.

If one now wants to dope this layer above the masking layer, silane is usually added during the GaN growth. However, silicon inhibits two-dimensional growth and promotes the three-dimensional, which delays the coalescence process and requires very high layer thicknesses and thus long growing time. Especially at

Silicon doping by 1 x ΙΟ ^ cm ^ or higher is the

Coalescence very difficult. With one of the dopants according to the invention, the growth of such a GaN layer is much easier. Although there may be little influence on the coalescence of the dopants, this is clearly less pronounced than when using silicon as the dopant. Thus, significantly higher dopant concentrations than when using silicon as dopants can be achieved.

For example, a thickness of the layers 2a, 2c together is between 200 nm and 300 nm inclusive, as is possible in all other embodiments. The

Growth substrate 1 and optionally also the masking layer can, as in all other embodiments, na the generation of the semiconductor layer stack 2 are removed from this.

If the growth substrate 1 is detached, it is not

immediately detectable. However, they are thicker

Semiconductor layers usually stack 2

Voltage compensating layers detectable. Furthermore, it can be concluded from strain gradients, as can be obtained for example by means of high-resolution Raman spectroscopy, and also from the dislocation density and the propagation of these on the substrate type. So are usually strain on the invention

Growth substrates stronger, dislocation densities higher and dislocation migration, but also the dislocation recombination, already more pronounced by the existing strain during growth than, for example, on sapphire substrates.

FIG. 3 shows a flow chart which

Method steps for producing a semiconductor chip according to the invention shows. In method step 301, a silicon substrate is provided. On the silicon substrate, a buffer layer is grown. Subsequently, in the

Step 302, an Al-containing intermediate layer is applied to the buffer layer. this happens

for example, by supplying an aluminum precursor and ammonia.

Subsequently, in method step 303, the layers of the semiconductor layer stack are applied to the aluminum-containing layer

Applied intermediate layer. By the aluminum-containing

Intermediate layer is generated in the subsequent layer of the semiconductor layer stack compression. In method step 304, a doping of the layer or layers of the semiconductor layer stack then takes place. After the doping process is the so

cooled semiconductor chip cooled.

Another embodiment of the semiconductor chip 10 is shown in FIG. On a 111 or 110 surface of a silicon substrate 1 is a buffer layer 3, which also acts as a seed layer 5, grown. The seed layer 5 has A1N and is undoped or mixed with Si, O or In. A thickness of the seed layer 5 is preferably between 100 nm and 300 nm inclusive.

The seed layer 5 is followed by the intermediate layer 4, which has four layers. These layers are not shown in FIG. The individual layers are made of AlGaN and each have a thickness of about 50 nm. In the direction away from the substrate 1, an Al content decreases and amounts to approximately 95%, 60%, 30% and 15% in the respective layers.

preferably with a tolerance of no more than 10 percentage points or no more than 5 percentage points.

The seed layer 5 is followed by a growth layer 8. The growth layer 8 is a GaN layer having a preferable thickness between 50 nm and 300 nm inclusive

Growth layer 8 may be doped or undoped. If the growth layer 8 is doped, then there is one

Dopant concentration preferably by at least a factor 2 or factor 4 under a dopant concentration of the n-doped layer 2b.

On the growth layer 8, the masking layer 6 of SiN is applied. A degree of coverage of the masking layer 6, based on the growth layer 8, is about 65%. In openings of the masking layer 6, the coalescence layer 7 is grown on the growth layer 8. Starting from these openings, the coalescing layer 7 grows above the

Masking layer 6 into a continuous layer. A thickness of the coalescing layer 8, which is preferably a GaN layer, is approximately 0.5 μm to 1.0 μm. The coalescing layer 7 can be doped in the same way as the growth layer 8. The coalescing layer 7 follows a middle layer 9. The middle layer 9 is an AlGaN layer having a thickness of about 15 nm. Other than drawn in the figures, it is also possible that a plurality of middle layers 9 are present. The n-doped layer 2b of the semiconductor layer stack 2 based on InGaN is then grown on the middle layer 9. It is the n-doped layer 2b doped with a concentration of between 5 x 10 ¹⁸ cm ^J to

1 x ₁₀ 20 cm ^J or between 1 x ₁₀ 19 cm ^J to 6 x ₁₀ 19 cm ^J , in particular 2 x ₁₀ 19 cm 3. D _e doping is preferably carried out with Ge or with one of the other dopants mentioned above.

A thickness D of the n-doped layer 2 b, measured from the middle layer 9 to the active layer 2 a, is preferably approximately 1.5 μm to 2.5 μm. In one of the middle class 9

The nearest area with a preferred thickness of at least 100 nm and / or at most 500 nm is the

Optional dopant concentration decreases and 1017 cm in this area is between 5 x ^J and

1 x ₁₀ 19 cm ^J or between including 8 x 1017 cm ^J and

2 x 10 ¹⁸ cm ^J , in particular 1 x 10 ¹⁸ cm ^J As in all other embodiments, it is possible that in addition to the heavier dopant than Si from the IV. Main group or the dopant from the VI. Main group, in particular Ge or Te, also in addition to Si as codotand

Is used, in particular in the n-doped layer 2b and / or in the coalescing 7 and / or in the

Growth layer 8. A ratio of

Dopant concentrations of Si and the dopant such as Ge or Te are then preferably between 0.2 and 0.6 inclusive or between 0.25 and 0.4 inclusive. For example, the n-doped layer 2b is doped with Si at approximately 5 x 10 ¹⁸ cm ^J and Ge or Te at approximately 1.5 x ₁₀ 19 cm ^J. In the semiconductor chip 10 according to the embodiment in FIG. 5, the semiconductor layer stack 2 is on one side

Carrier substrate 11 applied. The growth substrate 1 and the layers up to and including the masking layer 6 are removed from the semiconductor layer stack 2.

At the n-doped layer 2b, which faces away from the carrier substrate 11, a roughening 13 is produced to improve a light extraction efficiency. The roughening 13 extends through the coalescing layer 7 through to or into the n-doped layer 2b, so that in places the

Middle layer 9 is exposed from AlGaN. An average depth of the roughening is preferably between 300 nm and 2.5 μπι. For example, the roughening 13 is sufficient

at least 1% or at least 2% and / or at most 5% or at most 10% or at most 15% in the n-doped layer 2b, based on the thickness of the n-doped layer 2b. A radiation exit surface of the semiconductor layer stack 2 is thus in places by a Material of the coalescence layer 7 is formed. Optionally, a passivation made of a transparent material such as SiN or SiO 2 may be applied to the coalescing layer 7, not shown in the figures.

Optionally, two, for example metallic, electrical contact layers 12 are attached to the semiconductor layer stack 2. Which faces away from the carrier substrate 11

Contact layer 12 may also, in contrast to FIG. 5, be located closer to the carrier substrate 11 than the middle layer 9

Semiconductor chip 10, notwithstanding Figure 5, also act on a flip-chip. Another embodiment of the semiconductor chip 10 is shown in FIG. The semiconductor layer stack 2 is fastened to the carrier substrate 11 via a connection means 18, for example a solder. The carrier substrate 11 facing side of the semiconductor layer stack 2 is via the first electrical connection layer 14 and over the

Carrier substrate 11 contacted electrically.

The carrier substrate 11 facing away from the

Semiconductor layer stack 2 is contacted via the second electrical connection layer 16. The second connection layer 16 penetrates the active layer 2a from the carrier substrate 11 and is guided laterally next to the semiconductor layer stack 2 and can be contacted, for example, with a bond wire, not drawn.

The roughening 13 is not enough to the second

Connection layer 16 zoom. The connection layers 14, 16 through a separation layer 15, for example of silicon oxide or silicon nitride, isolated from each other. The middle layer and the coalescing layer are not in FIG. 7

shown. The invention is not by the description based on the

Embodiments limited to these. Rather, the invention has every new feature as well as any combination of

Characteristics on what every particular combination of

Contains features in the claims, even if this feature or combination itself is not explicitly stated in the claims or exemplary embodiments.

This patent application claims the priority of German patent applications 10 2010 045 957.7, 10 2010 045 958.5 and 10 2010 052 542.1, the disclosure of which is hereby incorporated by reference.

Claims

claims

A semiconductor chip (10) comprising a semiconductor layer stack (2) based on a group III nitride material system and having at least one n-doped layer (2b), wherein

as n-type dopant a heavier dopant than Si from the IV. Main group or a dopant from the VI. Main group of chemical elements is used.

2. Semiconductor chip according to claim 1,

wherein on a carrier substrate (11) facing away

Side of the n-doped layer (2b) at least one

Grown middle layer (9) of AlGaN with a thickness between 5 nm and 50 nm inclusive,

on a side facing away from the carrier substrate (11)

Middle layer (9) a coalescing layer (7)

doped or undoped GaN is formed with a thickness of between 300 nm and 1.2 μπι,

a roughening (13) from the coalescing layer (7) to the and / or into the n-doped layer (2b) extends, a radiation exit surface of the

Semiconductor layer stack (2) partially through the

Coalescence layer (7) is formed, and

the middle layer (9) is exposed in places.

3. Semiconductor chip according to one of the preceding claims, wherein the n-doped layer (2b) in addition to the n-dopant additionally comprises Si as a further dopant, wherein a ratio of the dopant concentrations of Si and the n-dopant between 0.25 and 0 inclusive , 4 lies.

4. The semiconductor chip according to one of the preceding claims, wherein the dopant concentration of the n-type dopant in the n-doped layer (2b) is greater than 1 x 10 ¹⁹ 1 / and the n-type dopant Ge, Sn, Pb, 0, S, Se or Te is.

5. Semiconductor chip according to the preceding claim,

wherein the n-type dopant is Pb or 0.

6. Semiconductor chip according to one of the preceding claims, wherein the semiconductor chip (10) is an optoelectronic chip having an intended for generating radiation active layer (2a) between the n-doped layer (2b) and a p-doped layer (2c).

7. Semiconductor chip according to one of the preceding claims, wherein the semiconductor chip (10) is an InGaN LED and the semiconductor layer stack (2) has a one-sided electrical contact.

8. Semiconductor chip according to one of the preceding claims, wherein the semiconductor chip (10) comprises a carrier substrate made of silicon.

9. Semiconductor chip according to one of the preceding claims, wherein the dopant concentration of the n-type dopant in the n-doped layer (2b) satisfies the following condition:

D x Dis _E dge x N> 5 x 10 ²³ cm ^-4 , where D is the layer thickness of the n-doped layer (2b),

Di ^s Edge of the average dislocation density with step proportion in the region of the n-doped layer (2b) in cm with a value above 1 × 10 ⁸ cm ^-2 and N the

Dopant concentration in the n-doped layer (2b) in cm-3.

Semiconductor chip according to the preceding claim,

wherein the thickness D is between 0.4 μπι and 3 μπι, DlS _j ^ g _g between and including 5 x 10 ⁷ cm ^Δ and

1 x 109 cm ^Δ , N between inclusive

7 x 10 ¹⁸ cm ^J and 5 x ₁₀ 19 cm ^J and the expression D x DlS _j g _g x N is at most 1 x 10 ²⁶ cm ^q .

Method for producing a semiconductor chip (10), comprising the following method steps:

Providing a growth substrate (1),

- Epitaxial growth of one

Semiconductor layer stack (2) lying on a

Group III nitride based material system and

at least one n-doped layer (2b), wherein as n-type dopant a heavier dopant than Si from the IV. Main group or a dopant from the VI. Main group of chemical elements is used.

Method according to the preceding claim,

wherein a light emitting diode is manufactured and on the

Growth substrate (1) the following layers are grown directly on each other and in the order given:

a seed layer (5) based on A1N,

an intermediate layer (4) based on AlGaN, wherein an Al content decreases away from the growth substrate (1), a growth layer (8) based on GaN,

a masking layer (6) based on SiN, wherein the masking layer (6) does not completely cover the growth layer (8),

a coalescence layer (7) based on GaN,

a middle layer (9) of AlGaN, and

the semiconductor layer stack (2a, 2b, 2c) based on InGaN. 13. Method according to the preceding claim,

wherein the seed layer (5) has a thickness between

including 100 nm and 300 nm and doped with Si or O and / or provided with In. 14. The method according to any one of claims 11 to 13,

while growing a germanium-hydrogen

Compound, an organic germanium compound, tert-butyl-german, tert-butyl-tin, tert-butyl-lead, an organometallic compound of the type F4-Me with R an organic radical, or a compound from the VI.

Main group is used with hydrogen or an organic radical.

15. The method according to any one of claims 11 to 14,

wherein the growth substrate (1) is a silicon substrate.