WO2012035135A1 - Semiconductor chip and method for producing the same - Google Patents

Semiconductor chip and method for producing the same Download PDF

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Publication number
WO2012035135A1
WO2012035135A1 PCT/EP2011/066084 EP2011066084W WO2012035135A1 WO 2012035135 A1 WO2012035135 A1 WO 2012035135A1 EP 2011066084 W EP2011066084 W EP 2011066084W WO 2012035135 A1 WO2012035135 A1 WO 2012035135A1
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layer
semiconductor chip
dopant
doped
cm
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PCT/EP2011/066084
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German (de)
French (fr)
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Armin Dadgar
Alois Krost
Peter Stauss
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Osram Opto Semiconductors Gmbh
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Priority to DE102010045957.7 priority
Priority to DE102010045958.5 priority
Priority to DE102010045958 priority
Priority to DE102010052542.1 priority
Priority to DE201010052542 priority patent/DE102010052542A1/en
Application filed by Osram Opto Semiconductors Gmbh filed Critical Osram Opto Semiconductors Gmbh
Publication of WO2012035135A1 publication Critical patent/WO2012035135A1/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
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    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/02365Forming inorganic semiconducting materials on a substrate
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    • H01L21/02521Materials
    • H01L21/02538Group 13/15 materials
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    • H01L21/02381Silicon, silicon germanium, germanium
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    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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    • H01L33/26Materials of the light emitting region
    • H01L33/30Materials of the light emitting region containing only elements of group III and group V of the periodic system
    • H01L33/32Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
    • H01L33/325Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen characterised by the doping materials
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Abstract

The invention relates to a semiconductor chip (10) comprising a stack (2) of semiconductor layers, the stack (2) of semiconductor layers being based on a material system of the group III nitrides and having an n-doped layer (2b). The n-dopant used is a dopant that is heavier than silicon of the fourth main group or a dopant of the sixth main group of chemical elements. The invention further relates to a method for producing a semiconductor chip (10) of the above type.

Description

description

Semiconductor chip and method for its production The invention relates to a semiconductor chip comprising a semiconductor layer stack based on a group III nitride, and a method for its production.

Traditionally, films are often a

Semiconductor layer stack, which is based on a material system of the group-III nitrides, grown on a hetero-substrate such as sapphire, SiC or silicon. To produce an n-type conductivity in the layers of the semiconductor layer stack those wherein silicon is used as n-type dopant is usually used, which has established itself as easy-to-handle and efficiently dopant are often doped. However, such a doping can tensile to a

cause tension in the semiconductor layer stack, which can adversely affect the semiconductor chip performance and even cause damage to the semiconductor layers of the stack. As damage to tearing of the layers of the stack can occur, for example. Such damage caused by Si doping, for example, in the

Publication "Effect of Si doping on strain, cracking, and microstructure in GaN thin films grown by metal organic chemical vapor deposition", Romano et al. , J. Appl. Phys. , Vol. 87, No. Described 11, June 1., 2000

The growth of silicon requires unless bauelement- relevant layer thicknesses of more than 2 or 3 are to be μπι μπι reached, except for a seeding layer and a bottom buffer layer to about 500 nm thickness, a compressive

To bias the growing layer. For example, when growing a GaN layer stack on a

Silicon growth substrate, especially when it

applied cooling process, tensile stresses occur in the layers. Conventionally, such a tensile tension by means of a compressive

Vorverspannung of the group III-nitrides

Semiconductor layer stack compensated during growth. Such Vorverspannungen for example, in the

Publication "GaN-based epitaxy on silicon: stress measurements", Krost et al. , Phys. stat. sol. (a) 200, No. described 35 (2003), - 1, 26th This intentional compressive

However Vorverspannung adversely at a high

Doping of the layers digested with silicon, so that

in turn, can occur rupture of these layers during the cooling of the layers.

In the growth of GaN layers on a sapphire substrate, however, a compressive created in the cooling process

Strain due to the thermal mismatch of the

Materials. However, a high Si doping, and / or a high layer thickness of the n-doped layers of the

due to the tensile stress generated thereby during the deposition of lead layer stack already in cracking in the epitaxial layers.

However, thick and highly doped layers are a prerequisite for example of efficient light emitters which are to be produced in inexpensive and large-area available silicon substrates. In addition, thick and highly doped layers for electronic components find such as pin or Schottky transistors for high voltage applications

Use . to reduce the tensile stress in such a semiconductor chip, is indeed possible in principle, but requires a lot of effort. The reason for this is the typically high dislocation density of greater than or about 1 x 10 ^ cm ~ 2

By an addition of Si to or greater than about 1 x ΙΟ ^ cm ^ an already built-in compressive stress is reduced by bending the dislocations, or a

additional tensile stress generated. This effect is, among others, in the publication "Si doping effect on strain reduction in compressively strained A10.49GaO.51N thin films," Cantu et al. Appl. Phys. Lett., Vol. 83, No. 4, July 28, 2003, described below.

Si is used as dopant, particularly because silane as a starting material for the silicon doping has a low price and allow easy use of silane seem complicated as unnecessary an insert of other elements as a dopant. Also with regard to a reduction of the stress problem not benefited from other Group IV dopants could be previously recognized because the chemistry of the materials is very similar and can therefore expect the same problems.

A high doping, however, is necessary for good contact formation, among other things, with electron concentrations above 5 x ΙΟ ^ cm ^ be sought for it.

The growth of GaN layers on a hetero substrate generally leads to an increased dislocation density in the GaN layers. To reduce this dislocation densities, see other SiN x -Maskierungsschichten

Use. Such masking layers are known to the expert, inter alia, the term "in situ SiN masking layers" and, for example in the

Publication "anti-surfactant in III-Nitride Epitaxy - quantum dot formation and dislocation Termination", Tanaka et al, Jpn.. J. Appl. Phys. , Vol. 39 (2000), PI. 2, No. 8B. Such a masking layer is then partially applied on this by growing at least a first group III nitride layer of the semiconductor layer stack. The application of the masking layer is typically carried out by a reaction of silicon with nitrogen (ammonia source). With a correspondingly thin deposited layer, the expert can achieve that only partially trained SiN layer. In another GaN deposition step a further GaN layer is formed starting from the not covered with SiN areas. This grows initially in a 3-dimensional island structure on the free material of the nucleation regions of the first GaN layer and spreads with increasing

Growing season from in the lateral direction over the SiN masking layer. In this area is the

Dislocation density significantly reduced.

If the second GaN layer for improved electrical conductivity with Si doped, the parasitic reaction of the silicon with nitrogen to SiN may also occur, so that here also disadvantageous takes place only partial overgrowth, and a desired rapid

Coalescence of the islands of growth to a closed

dislocation-reduced layer is hindered, or, depending on the process, coalescence of undesirable newly formed on the SiN mask germination starts.

It is an object of the present application to provide an improved semiconductor chip which has a high n-type doping at the same time a reduced risk of cracking of the

having layers of the semiconductor chips. It is another object of the present application, a production method

indicate to grow a GaN layer on a growth substrate with a high degree of n-doping, in which the

Risk of damage to the GaN layer is reduced and additional quick coalescence of a GaN layer

below a possibly applied masking layer is not prevented from adversely.

These objectives are, among others, by a

Semiconductor chip having the features of claim 1 and by a method for producing such a semiconductor chip having the features of claim 10. advantageous

Further developments of the semiconductor chip and the method for its production are the subject of the dependent claims.

In one disclosed embodiment, the semiconductor chip a

Semiconductor layer stack, based on the material system of the group-III nitrides and having at least one n-doped layer. As an n-dopant is a heavier

Dopant as silicon from the IV. Main group or a dopant from the VI. Main group of the chemical elements. The semiconductor chip is preferably employed for

electronic application and preferably has highly conductive or highly doped n-type layers in the GaN

Semiconductor layer stack. In particular, based the

Semiconductor layers stack on Al In n] __ n _ m N m Ga having preferably 0 <n is <0.2 and / or 0.35 <m <0.95 and / or 0 <1-nm <0.5 or therefrom, said dopants from said empirical formula are not included and thus the

Semiconductor layer stack may additionally be included. In a middle layer having a thickness of up to 50 nm that 0.75 <n <1 may be deviated from the above values ​​for n, m and are instead.

As n-doped layer based on the material system of the group III-nitrides which can be understood also an n-doped substrate as part of the registration, on the

Material system of the group III-nitride based, so

for example, GaN. In this case, the

Semiconductor chip may be applied at least as the semiconductor layer stack the n-doped substrate, on which further layers therefore.

In a development of the semiconductor chip is a

optoelectronic semiconductor chip. In this case, the semiconductor chip has an opening provided for generating radiation active layer between the n-doped layer and a p-doped layer. An optoelectronic semiconductor chip is in particular a semiconductor chip, which allows the conversion of electronically generated data or energies in light emission, or vice versa. For example, the

optoelectronic semiconductor chip is a radiation-emitting semiconductor chip.

When using a dopant as claimed for n-type doping step advantageously advance discussed adverse effects relating to the tensile stress and / or the parasitic reaction does not occur. In particular, by means of a dopant as claimed occurring tensile stress in the cooling process and / or the

tensile stress occurring due to the high n-doping as well as a purely partial overgrowth are reduced due to high silicon content or prevented.

It is also possible that n-doped layer or layers of the semiconductor layer stack with improved n-

deposit conductivity correspondingly thin. With the

claimed dopants can thus a thin and

highly doped n-layer are prepared. The use of a dopant as claimed thus leads to a reduction of cracking and damage to the n-layer of the semiconductor layer stack, as opposed to

Use of silicon as dopants. In addition, a thick highly n-doped Group III nitride layer on a sapphire, silicon carbide or silicon substrate can be realized. Here, the dopant heavier or larger than silicon must be so that it does not act as amphoteric dopant or a p-dopant. Alternatively, Group VI dopants offer. The active layer of the semiconductor layer stack preferably includes a pn-junction, a double heterostructure, a single quantum well (SQW, single quantum well) or a

Multiple quantum well structure (MQW multi quantum well) for generating radiation. The term quantum well structure does not exhibit any significance with regard to the

Dimensionality of the quantization. It includes, among other things, quantum wells, quantum wires and quantum dots and any

Combination of these structures. On a material system of the group III nitride based means here and below that the

The semiconductor layer sequence of the semiconductor layer stack is epitaxially deposited on a growth substrate layer sequence which has at least one layer of a nitride II I compound semiconductor material,

preferably Al n Ga m In] __ _ n m N, where 0 <n, m <1, n + m <. 1

This material does not necessarily have a mathematically exact composition according to the above formula. Rather, the material may comprise one or more dopants as well as additional ingredients, the

characteristic physical properties of

Al n Ga m In] __ _ n N m change material does not substantially. For simplicity, however, the above formula includes only the major components of the crystal lattice (Al, Ga, In, N), even though these may be partly replaced by small amounts of other substances. In a development of the n-type dopant Ge, Sn, Pb, 0, S, Se or Te. So Here, a as n-type dopant

Find heavier dopant from the IV. Main group of chemical elements as silicon, that is Ge, Sn or Pb use. As a dopant from the VI. Main group finds

for example, 0, S, Se, or Te use. These dopants do not show the adverse effects of the prior art, as these dopants not to bend or

contribute migration of dislocations, thereby favoring a tensile strain.

In one development, silicon is used as n-type dopant in addition to Ge additionally use. The n-doped layer is so doped in this case with Ge and Si. So that the tensile stress and the doping can be independently influenced by one another.

In one embodiment, the dopant concentration of the n-type dopant in the n-doped layer is greater than 10 19 l / CNW. It is thus an n-doped layer on a

Growth substrate grown with a high dopant concentration. Thus, a thin and at the same

highly doped n-doped layer can be realized.

In a development of the semiconductor chip is an InGaN LED. Preferably, the semiconductor chip is a thin film chip. As

Thin-film chip, a semiconductor chip is considered in the context of the application, during which production the growth substrate on which the semiconductor layer stack epitaxially

was grown, and preferably is completely detached. The semiconductor layer stack of the semiconductor chip can for example be applied to a carrier substrate. is preferred as the carrier substrate a silicon-containing

Carrier substrate is provided, particularly when the growth substrate is already a silicon-containing substrate.

In a further development, the semiconductor chip and / or the semiconductor layer stack a unilateral electric

Contacting on. In other words, the semiconductor chip may then be a flip-chip. It is also possible that an electrical contact is established, as in the

Document US 2010/0171135 Al or WO 2011/006719 AI indicated, the disclosure content by reference

is recorded. The n- and p-doped layers of the

Semiconductor layer stack are therefore one-sided, so

for example, only from a rear side of the

Semiconductor layer stack electrically contacted.

Alternatively the electrical contact may be of a

carried front of the semiconductor layer stack. For making electrical contact on one side of the

Semiconductor layer stack arranged a first and second electrical connection layer, which are provided for electrical contacting of the layer stack of one conductivity type. The first and second electrical

Connection layer are mutually electrically isolated, for example by means of an electrically insulating separation layer.

The one-sided contacting technique of the chip allows a low resistance contact. Due to the one-sided

Arrangement of the contacts can advantageously the full functionality of the epitaxial layers of the

Semiconductor layer stack, in particular of the active layer can be ensured.

In one embodiment, the dopant concentration of the n-type dopant satisfied in the n-doped layer following

condition:

D x DIS Edge x N> 5 x 10 23 cm -4, with D the thickness of the n-doped layer in cm, DIS ^^ g g the average dislocation density-scale content in the n-doped layer in cm -2 and with a value greater than 1 x 10 ^ cm -2, N of the dopant concentration in the n-doped layer in cm -3.

Here, D is in particular the layer thickness of the entire n-doped layer and, optionally, subsequent

Layers, but up to a maximum of a next

Stress-compensating stratum. N is in particular a high donor concentration in the n-doped layer.

In this case, a strong tensile stress is generated at high concentrations also offset by a thin n-doped layer having a thickness D of at least 100 nm.

Since such a tensile stress even after lowering the

Dopant concentration is maintained, it is not essential that the entire n-doped layer

is highly doped, but that is at least partially relatively highly doped and / or high levels ¬ dislocation concentration is present. Such a high

Doping is seen in the direction of growth at the beginning of the n-doped layer somewhat less advantageous than at the end, since the reduced voltage in the growing layer on a thicker portion of the layer stress-reducing effect than at the end.

This n-doped layer is preferably at least 0, 6 μπι thick and has approximately at the top at least 400 nm

Electron concentration of at least 18 cm 5xl0 J on.

In particular, due to the strong lattice-mismatched

Growth process silicon is the

Edge dislocation density ^ typically above 2xl0 9 cm. Thus, a value is obtained from the formula of claim 1 of

6xl0 23rd According to at least one disclosed embodiment of the semiconductor chip, the thickness D of between 300 nm and 5 μπι, in particular between 0.4 and 3 μπι μπι or μπι between 0.5 and 2.0 μπι. DIS ^^ g g is to

Example between 5 x 10 7 cm and 109 cm ^ Δ, or is between 9 x 10 7 cm Δ and 5 x 10 cm Δ °. The concentration N can be between 1 x 10 18 cm and 1 x 10 J (J cm or J is between 7 x 10 cm 3 and 5 x 1θ19 cm _. 3

According to at least one disclosed embodiment, the semiconductor chip is considered to be lower limit for the expression x D x N a DlSßdge

Value of at least 1 x 10 ^ 3 ^ cm or of at least

5 x 10 ^ 3 cm "^ or of at least 1 x 10 ^ 4 ^, or cm-. A

Upper limit may alternatively or additionally at most

5 x 10 ^ 6 cm ~ 4 or at most 1 x 10 ^ 6 cm ^, respectively.

Above condition can be used as a criterion for meaningful

Using a non-standard and as claimed dopants are seen in high-doped Group III nitride layers in comparison to the commonly used silicon. In this case, these layers may both heteroepitaxially on sapphire, SiC, or silicon, but also homoepitaxially on group III nitride substrates a correspondingly high

Having dislocation density of, for example, higher than 5 x 10 ^ cm ~ 2, are grown.

According to at least one disclosed embodiment of the semiconductor chip that includes a highly n-conductive layer, in particular based on GaN, which layer preferably follows an in situ or ex situ masking layer.

According to at least one disclosed embodiment of the semiconductor chip, the high n-type layer formed on the

Masking layer followed by a n-type doping higher than lO-L ^ _ cm 3 or δχΐθ ^ _ cm 3. This n-type doping takes place in particular across a layer thickness of 10 nm to 300 nm. By using the dopants according to the invention a high n-type doping can be realized without obstructing the subsequent coalescence significantly or strongly herauszuzögern, as would be the case with a Si doping as Si transported the three-dimensional growth and thus a two-dimensional growing layer it is difficult to reach, usually only after the growth of very thick layers.

According to at least one disclosed embodiment comprises shape of the semiconductor chip or is the masking layer for example of SiN, SiO, SiON, or BN or another, or only inhibited wetting material which promotes a three-dimensional growth, and / or growth conditions that regardless of such do a masking layer. One way to achieve this is to use a heavy doping »10 ^ - ^ cm - ^ about comprehensive Si, a

provide layer thickness of 10 nm to 300 nm.

According to at least one disclosed embodiment of the semiconductor chip, the masking layer has a thickness of at most 2 nm, in particular of at most 1 nm. For example, the thickness of the masking layer is one or two monolayers on average. Masking layers are described in "anti-surfactant in III-Nitride Epitaxy - Quantum Dot

described formation and displacement Termination ", Tanaka et al., Jpn. J. Appl. Phys., Vol. 39 (2000), PI. 2, No. 8B, the disclosure of which is incorporated by reference.

According to at least one disclosed embodiment, the semiconductor chip is a degree of coverage of the masking layer between 20% and 80% or between 55% and 70%, including the underlying layer. In other words, the growth substrate and / or the Anwachsschicht, seen in plan view, covers to said share of a material of the masking layer.

According to at least one disclosed embodiment, the semiconductor chip has a coalescing layer on this, that of the

in particular, immediately following the masking layer and in which the coalescence takes place, proceeding from openings in the masking layer. This layer, in particular, a GaN layer. A thickness of this

Coalescence is preferably between

300 nm and 3 μπι, in particular between 400 nm and 1.2 μπι. The coalescing layer may be undoped or substantially undoped. According to at least one disclosed embodiment of the semiconductor chip that includes a central layer, based in particular AlGaN. An Al content of the middle layer is preferably between 75% and 100%. A thickness of the

Middle layer is in particular between 5 nm and 50 nm, for example between 10 nm and

20 nm. The middle layer may be between the highly n-conductive layer and the masking layer. In particular, the middle layer is directly adjacent to the highly n-conductive layer and to the coalescing layer.

Detection of the or of the dopants in the semiconductor chip may be, for example, by a secondary ion mass spectrometry-analysis, short-SIMS, be effected. are in this

Masking layers detectable or most existing on a micrometer scale at large islands of the masking layer doping fluctuations, due to a

multifaceted dependent incorporation of dopants and slight variations in concentration involved. Such inhomogeneities may for example also by cathodoluminescence cross-sectional or cross-sectional transmission electron microscopy cathodoluminescence based on the different positions of donatorgebundenen

Excitons or a line broadening of luminescence are detected, even if the masking layer is removed, for example by an etching process.

According to at least one disclosed embodiment of the semiconductor chip, a thickness of the semiconductor layer stack is at least 1 or at least 2 μπι μπι and / or at most 10 or at most 5 μπι μπι. This may be necessary to functional

Layers accommodate as an active layer, and / or to realize a contact and current spreading and / or to provide sufficient insulation to ensure the growth substrate.

is due to the comparatively large layer thickness

For example, in the case of silicon for the growth substrate at such thicknesses a voltage compensation by

Biasing a large part of the grown

Semiconductor layer stack preferred. This can be achieved, for example, stepped Al-containing

Between layers in the direction away from the growth substrate decreasing the Al content, Al-rich by AIN layers or a superlattice and Al-poor layers. It may be the intermediate layer is between one and eight

include sub-layers, in particular between two and five sub-layers. A total thickness of the intermediate layers is, for example, between 20 nm and 500 nm, in particular between 50 nm and 250 nm. According to at least one disclosed embodiment, the semiconductor chip is the seed layer, which is based in particular A1N, and / or a directly thereon grown GaN layer doped. A doping of the seed layer, which can also serve as a buffer layer, is carried out in particular with silicon or with

Oxygen. A dopant concentration is

for example, between 5 x 10 18 cm and J

5 x 1021 cm J or between 2 x 10 19 cm and J

2 x 10 20 cm J. Similarly, the seed layer may comprise indium in a proportion of up to 20% or up to 10%. As a growth substrate in this case is particularly preferably silicon or sapphire.

The high dislocation density of particular> 5xl0 9 cm ^ at the beginning of heteroepitaxial growth, may without the

Generating significant tensions, a high carrier concentration are generally achieved and therefore no low contact resistance to the silicon substrate.

Through the use of the dopants according to the invention as a replacement for Si, the stress are to a lesser degree

reduced and there are semiconductor chips on silicon-containing

allows substrates.

Disclosed is a method for producing an optoelectronic semiconductor chip beyond. For example, a semiconductor chip can be manufactured by the method as described guide forms in conjunction with one or more elements selected from the above. Features for the process are therefore also discloses to the semiconductor chip and vice versa.

A method of manufacturing a semiconductor chip comprises the following steps: - providing a growth substrate,

- epitaxial growth of a semiconductor layer stack, which is based on a material system of the group-III nitrides and having at least one n-doped layer, as the n-dopant a heavier dopant as silicon from the IV main group or of a dopant from the VI.. Main group of the chemical elements is used.

Such a method enables the growth of GaN layers on, for example, a silicon substrate with a high degree of n-doping, in which the tension in

Is not substantially influenced by the doping. It is also possible, corresponding to n-doped layer or layers of the semiconductor chips with improved n-conductivity! thin deposit. Thus, a thin and at the same highly doped n-layer can be produced. In this case, a silicon-containing substrate can be used as a growth substrate, which is advantageously cost-effective. Further, in such a process with additional

Use of a SiN masking layer

Displacement reducing the subsequent coalescence

advantageously not adversely affected.

One can use the method described the complicated and not always necessary component of the requirements

Reduction of dislocations or their

Displacement hiking that trigger the tensile stress at doping decisively to deal yet highly doped

Making layers.

According to at least one disclosed embodiment of the method a pressure-strained GaN layer on the growth substrate, which is in particular a silicon substrate during the growth, grown with a high n-type impurity at a relatively high dislocation density, wherein the compressive strain is not or substantially not the doping is influenced by the use of a heavier dopants such as Ge, Sn, Pb, 0, S, Se, or Te. It turns out that these elements do not show the undesirable compressive stress relieving effect as it apparently has little or no help to offset hiking.

According to at least one disclosed embodiment, the method finds application for the production of homoepitaxial

Component layers on Group III-nitride buffer layers.

The growth substrate is in a further development, a SOI substrate ( "Silicon on insulator" substrate). Alternatively, the growth substrate may be a sapphire or SiC substrate.

In a further development during growth is a hydrogen germanium compound, an organic germanium compound, tert. -butyl-German, tert. butyl-tin, tert. -butyl-lead, an organometallic compound of the type R F4_Me with a

organic radical in the vapor phase epitaxy or

Compound from the VI. Main group with hydrogen or an organic radical used.

The doping with germanium is preferable before the other elements because the available precursors are easy to use and the vapor pressure of Dotands over the layer with the often prevailing in the Group III nitride epitaxial process temperatures above 1000 ° C readily manageable is. The other precursors are up to

Oxygen in the process, however not so easy to handle. However, oxygen in turn can be undesirable in the epitaxial process, since it is considered Hauptkontaminent and

at least in the organometallic vapor phase epitaxy unwanted reactions with the organometallic

can trigger compounds and, therefore, a potential

represents security risk in hydrogen-rich processes.

The features referred to in connection with the semiconductor chip also apply to the method and vice versa.

Further advantages and advantageous developments of the

Invention will become apparent from the following described in connection with Figures 1 to 3 embodiments. Show it :

Figures 1, 2A, 2B, 2D are each a schematic cross section of an embodiment of a semiconductor chip according to the invention,

Figure 2C is a diagram in which the bracing against the

Production time is plotted,

Figure 3 is a flow diagram relating to an inventive

Manufacturing process, and

Figures 4 to 6 are schematic cross-sectional views of further embodiments of

Semiconductor chips according to the invention.

In the figures, the same or equivalent to

Components each be provided with the same reference numerals. The ingredients and their illustrated

Size relationships among one another should not be regarded as true to scale. Instead, individual components, such as, for example, layers, structures,

Components or areas to be shown for better illustration and / or better comprehension exaggeratedly thick or large dimensions.

1 shows an embodiment of a semiconductor chip 10 in cross section. The semiconductor chip 10 has a

On the growth substrate 1 having, for example, sapphire, SiC or silicon. The growth substrate may be a SOI substrate ( "silicon on insulator" substrate), or a group II I-nitride substrate.

In the silicon-containing growth substrate 1, the

individual layers 2a, 2b, 2c of the grown semiconductor layer stack. 2 The semiconductor layer stack 2 is based on a material system of the group-III nitrides. Preferably, the semiconductor layer stack 2 is based on the

InGaN material system. The semiconductor layer stack 2 has an active layer 2a. The active layer 2a

suitable, in operation of the semiconductor chip 10

for generating electromagnetic radiation. Preferably, the semiconductor chip 10 is an LED ( "light emitting diode").

The active layer 2a of the semiconductor layer stack 2 is disposed between an n-type layer 2b and a p-doped layer 2c. The n-doped layer is

Embodiment of Figure 1 directly on the

Growth substrate 1 is applied. Alternatively, the n-doped layer by means of a masking layer can, and

Coalescing layer on the growth substrate 1 is applied (not shown). The n-doped layer 2b has a heavier dopant as silicon from the IV. Main group or a dopant from the VI. Main group of chemical elements. As n-dopant of the IV. Main group so Ge, Sn and Pb is used. As a dopant of VI. Main group finds

for example, 0, S, Se, or Te use.

The dopant concentration of the n-type dopant in the n-doped layer 2b is preferably greater than 5 x ΙΟ ^ l / cm ^. Advantageously, due to the choice of the dopant conventionally occurring or in the cooling process occurring due to the tensile stress dopant concentration of the semiconductor layer material can be avoided. Layers with such a high doping are particularly advantageous for high lateral conductivity and optimized contact resistances. It is also possible that n-doped layer 2b with improved n-type conductivity

thin deposit accordingly or to make the n-contact surfaces for improved contact resistance correspondingly small.

The n-doped layer 2b and the p-doped layer 2c of the semiconductor layer stack 2 may be composed of a layer sequence. In this case, the

Semiconductor layer stack 2, a plurality of n-doped

Layers 2b which are interposed between the growth substrate 1 and the active layer 2a. On the side remote from the growth substrate 1 side of the active layer 2a may be arranged a plurality of p-doped layers in this case.

The dopant concentration of the n-type dopant in the n-doped layer or the n-doped layers 2b preferably satisfies the following condition: D x DIS Edge x N> 5 x 10 -4 cm Ζό, where D is the layer thickness of the n-doped layer 2a or the layer sequence of the n-doped layer, DIS ^^ g g is the average dislocation density levels proportion in the range of n- doped layer 2b or the n-doped layers in cm-2 with a value above 1 x 10 ^ cm ^ and N is the

Dopant concentration in the n-doped layer 2b or the n-doped layers in cm- ^.

Due to the choice of n-dopants tensile stresses in the semiconductor chip can be advantageously avoided, at the same time can be realized a thick and highly doped Group III nitride layer on silicon, sapphire or SiC. Thus, with such a heavy n-dopants the complicated and not always necessary from the requirements of reducing dislocations tensile stress that can at

trigger doping largely be bypassed, wherein

highly doped layers may be fabricated.

The semiconductor chip 10 has advantageously a

unilateral electrical contact on. This means that a first and second electrical connection pad on

the same side of the semiconductor chip 10 are arranged and spaced for example by means of an insulating

Separating layer are electrically insulated from each other.

By using an n-type dopant, which is heavier than silicon, a large-area, inexpensive, and

defective reduced epitaxy and Halbleiterchipprozessierung be made possible on silicon substrates. In particular, thick n-doped layers can be produced, the reduced mechanical damage, such as

exhibit cracking. Thus an improved method and a semiconductor chip with improved properties can be achieved.

In Figure 2A, another embodiment is a

The semiconductor chip shown in cross section. Of the

Semiconductor chip 10 of Figure 2A differs from the semiconductor chip of Figure 1 with additional layers 3, 4 which are disposed between the growth substrate and the semiconductor layer stack. 2 Specifically, a buffer layer 3 is applied on the growth substrate. 1 Such buffer layers 3 are in particular for growth on silicon-containing

Substrates 1 is used. On the buffer layer 3, an aluminum-containing intermediate layer 4 is arranged, on which the layers of the semiconductor layer stack are grown epitaxially. 2 The aluminum-containing layer is

for example, an AlN seed layer. such a

is also seed layer to grow on

siliceous Aufwachssubstraten used.

Incidentally, the embodiment of Figure 2A with the embodiment of Figure 1 is consistent.

In Figure 2B a further embodiment is a

The semiconductor chip shown in cross section. Of the

Semiconductor chip 10 of Figure 2B differs from the semiconductor chip of Figure 1 with additional layers 5, 6, 7, between the growth substrate and

Semiconductor layer stack 2 are arranged. Specifically, a first group III nitride layer 5 is applied on the growth substrate. 1 On this a partial SiN masking layer 6 is arranged. Subsequently, the second group III nitride layer 7 is arranged in such a way

in that it has a lower dislocation density than the first group III-nitride. 5

Subsequently, the layers of the semiconductor layer stack 2 are epitaxially grown.

Incidentally, the embodiment of Figure 2B with the embodiment of Figure 1 is consistent.

In Figure 2C, a diagram is shown, wherein, in

Manufacturing process, the stress against the time of the

manufacturing process is applied. The dashed line shows the manufacturing of a semiconductor chip with an n-type dopant is silicon, the solid line shows a semiconductor chip with an n-type dopant Ge.

The method for example relates to the production of a semiconductor chip according to the embodiment of Figure 2A.

The diagram of Figure 2C shows the curvature measurement during the growth of a silicon-doped GaN layer

(Dashed line) and a Ge-doped GaN layer

(Solid line) on a silicon substrate. After the growth of a buffer layer 101, a compression is generated by an Al-containing intermediate layer in the subsequent GaN layer 102, which is especially seen at the change of the curvature to negative values. During the doping 103, the curvature is virtually unchanged at the Ge doping. The illustrated in the diagram slight decrease is common in the growth process. In the case of silicon doping the curvature decreases, indicating a zugverspanntes growth. The silicon-doped layer can therefore be strongly torn after cooling, while the Ge-doped

Layer will not crack in spite of a high n-type doping with advantage.

As shown in the diagram, the semiconductor layers comprise silicon in the later manufacturing process, in particular at about 60 minutes or more, a smaller strain than in the case of doping with German and consequently a higher tensile stress after the cooling process (80 min). By means of a dopant such as German thus mechanical damage to the layers that can occur because of this occurring tensions are reduced.

The manufacturing process for the diagram of Figure 2C can include the following steps:

In the time interval 101 is in a growth chamber,

for example, an MOVPE reactor, a wet-chemical

inserted purified and deoxidized silicon substrate and heated to about 730 ° C. Subsequently, the supply of a Aluminiumprecursors and of ammonia follows. After the growth of about 25 nm A1N the sample is heated to 1050 ° C, with further ammonia flow and by supplying a

Galliumprecursors the growth of a GaN layer of the

Semiconductor layer stack started. As a result, a 0.7 μπι thick GaN layer is produced, having on the top 500 nm an electron concentration of 5 x 10 18 cm J. Because of the growth process is the

Dislocation density typically in excess of 2 x 10 8 cm -2. Using the condition D x DI SEDQJ XN> 5 X

10 23 cm 4 results in a value of 5 x 10 26th is for this purpose

Germanium as dopant diluted advantageously suitable in hydrogen. By using this dopant can be a

Cracking of the GaN layer on the

Siliziumaufwachssubstrat be avoided. The dilution of German in hydrogen usually falls lower than for silane in hydrogen, since the installation compared

is inefficient and vapor pressure driven more unlike the Si doping. For example, a dilution of 1% o to 1% GeH4 in H2 is possible.

An alternative manufacturing method to the diagram of Figure 2C can be carried out as follows:

A AlN seed layer is highly doped and directly growing a GaN layer. By a high dislocation density of greater than 5 x 10 ^ cm ~ 2 at the beginning of the heteroepitaxial growth can without generating any appreciable

Tensioning a high carrier concentration can be obtained and thus a low contact resistance for

Silicon substrate are made possible. In order to realize in the doping electron concentration of 5 x ΙΟ ^ cm ^, is located on the first 100 nm with dislocation densities of greater than 5 x 10 ^ cm ~ 2, the calculated according to the above condition

Value at greater than 2.5 x 10 ^ 7 cm ^. Due to a dopant that is heavier than silicon, the strain can with

Advantage be reduced to a lower level.

Another application is the growth of thick n-doped Group III nitride layers, usually by means of HVPE on a carrier substrate for the production of pseudo-substrates, detached from the support substrate to serve as a high-quality substrates for the hetero- and homoepitaxy: Here becomes effective for Si highly doped, conductive substrates usually a strong inhomogeneous curvature that displayed by subsequent grinding of the growth substrate

Layer is reduced. Then there is the problem that by the doping and the associated strong

Tensile stress can cause cracking during growth. Further, a low dislocation density usually by a forced 3D growth, either by the ELOG method by deposited in situ

Or, achieved mask layers, which usually consist of SiN by a low nucleation density leading to a 3D-growth. The subsequent coalescence is influenced by the doping with Si by the parasitic SiN layer formation undesirably. Is now in place with silicon doped with a dopant according to the invention, the resulting tensile stress can be reduced at the beginning of growth and are prospective and therefore more easily implemented as an n-doped layer in three-dimensional island growth this. This avoids subsequently cracks during growth and provides for less

Substrate curvature of detached from the growth substrate

Pseudo substrate after growth.

A further embodiment of the semiconductor chip 10 with a masking layer 6 is shown in Figure 2D. On the substrate 1, for example made of sapphire, SiC, or silicon, the approximately 20 nm thick seed layer is grown from 5 A1N. In the case of silicon as the growth substrate, the thickness of the seed layer 5 in this case is preferably between 100 nm and 250 nm, for example about 150 nm. In this an n-type follows doped intermediate layer 4 made of GaN. After about 300 nm growth, the growth is interrupted and at the same time supplying ammonia and silane, the masking layer is applied from SiN. 6 Then again follows the growth of the GaN layer 2b of the

Semiconductor layer stack. 2

This growth is initially in three dimensions, which is reflected for example in situ reflectometry on intrusion of a reflected intensity. After several hundred nanometers growth of the GaN layer 2b that intensity increases until it reaches a maximum value is two-dimensional again and the layer thus closed.

If one wants to dope this layer above the masking layer, one usually leads to silane during the GaN growth. However, silicon inhibits the growth of two-dimensional and transported the three-dimensional, which is why the coalescence process is delaying and very high layer thicknesses and thus requires a long growing season. especially in

Silicon doping by 1 x ΙΟ ^ cm ^ or higher the

Coalescence very difficult. With one of the dopants according to the invention the growth of such a GaN layer is much easier to do. Although there exists in the dopant under certain circumstances a smaller impact on the coalescence but it is much weaker than with the use of silicon as a dopant. Thus, significantly higher dopant concentrations than with the use of silicon can be achieved as dopants.

A thickness of the layers 2a, 2c together is, for example, between 200 nm and 300 nm, as is also possible in all other embodiments. The

Growth substrate 1 and optionally also the masking layer can, as in all other embodiments, well the generation of the semiconductor layer stack 2 are removed therefrom.

If the growth substrate 1 replaced, so it is not

immediately detectable. However, with thicker

Semiconductor layer stacks 2 usually

Stress-layers detectable. Furthermore, from Verspannungsgradienten how they can be obtained, for example, by high resolution Raman spectroscopy, and these are closed on the type of substrate and from the dislocation density and spread. So are usually Verspannungsgradienten to the invention

Aufwachssubstraten stronger dislocation densities higher and the displacement of hiking, but also the Versetzungsrekombination, already by the existing tension during growth more pronounced than, say, on sapphire substrates.

In Figure 3, a flowchart is shown which

shows process steps for manufacturing a semiconductor chip according to the invention. In process step 301, a silicon substrate is provided. On the silicon substrate, a buffer layer is grown. Then, in

Method step 302, an Al-containing intermediate layer is applied onto the buffer layer. this happens

for example, by supplying a Aluminiumprecursors and ammonia.

Subsequently, in process step 303, the layers of the semiconductor layer stack to be on the aluminum-containing

Intermediate layer applied. By aluminous

Intermediate layer is formed a compression in the subsequent layer of the semiconductor layer stack. In process step 304, then instead of a doping of the layer or layers of the semiconductor layer stack place. Following the doping process is the so

Semiconductor chip made cooled.

A further embodiment of the semiconductor chip 10 is shown in FIG. 4 On a 111- or 110-surface of a silicon substrate 1, a buffer layer 3, which also acts as a seed layer 5 grown. The seed layer 5 has A1N and is offset with undoped or Si, 0, or In. A thickness of the seed layer 5 is preferably between 100 nm and 300 nm.

the intermediate layer 4, which has four layers follows the seed layer. 5 These layers are not shown in FIG. 4 The individual layers are made of AlGaN and have a thickness of about 50 nm in each case. In the direction away from the substrate 1, an Al content decreases and is in the respective layers about 95%, 60%, 30% and 15%,

preferably with a tolerance of not more than 10 percentage points or more than 5 percentage points.

The seed layer 5 is followed by a Anwachsschicht. 8 The Anwachsschicht 8 is a GaN layer having a preferred thickness of between 50 nm and 300 nm.

Anwachsschicht 8 may be doped or undoped. If the Anwachsschicht endowed 8, there is a

Dopant concentration preferably by at least a factor of 2 or factor of 4 with a dopant concentration of the n-doped layer 2b.

the masking layer is applied from SiN 6 to the Anwachsschicht. 8 A coverage of the masking layer 6, based on the Anwachsschicht 8, is approximately 65%. In openings of the masking layer 6, the coalescing layer is grown on the Anwachsschicht 7. 8 From these openings, the coalescing layer 7 grows above

Masking layer 6 to form a coherent layer. A thickness of the coalescing layer 8, which is preferably a GaN layer is, about 0.5 to 1.0 μπι μπι. The coalescing layer 7 may be doped in the same manner as the Anwachsschicht 8. The coalescing layer 7 is followed by a middle layer. 9 The middle layer 9 is an AlGaN layer having a thickness of 15 nm. In contrast to drawn in the figures, it is also possible that several middle layers 9 are available. The n-doped layer 2b of the semiconductor layer stack 2, which is based on InGaN is then grown on the middle layer. 9 It is the n-doped layer 2b doped with a concentration between 5 x 10 18 cm to J

1 x 10 20 cm or J between 1 x 10 19 cm J to 6 x 10 19 cm J, in particular 2 x 10 19 cm 3 D e doping is preferably carried out with Ge or with one of the other above-mentioned dopants.

A thickness D of the n-doped layer 2b, measured from the middle layer 9 to the active layer 2a, is preferably about 1.5 to 2.5 μπι μπι. In one of the middle layer 9

nearest area with a preferred thickness of at least 100 nm and / or at most 500 nm is the

Optional dopant concentration decreases and 1017 cm in this area is between 5 x J and

1 x 10 19 cm or J of between 8 x 1017 cm and J

2 x 10 18 cm J, in particular 1 x 10 18 cm J. As in all other embodiments, it is possible that, besides the heavier than Si dopants from the IV. Main group or of the dopants from the VI. Main group, in particular Ge, or Te, and Si as additional Kodotand

Finds use, particularly in the n-doped layer 2b and / or in the coalescing layer 7 and / or in the

Anwachsschicht 8. A ratio of

Dopant concentrations of Si and the dopant such as Ge or Te is then preferably between 0.2 and 0.6 or between and including 0.25 and 0.4. For example, the n-doped layer 2b doped with Si to about 5 x 10 18 cm and J with Ge or Te with about 1.5 x 10 19 cm J. In the semiconductor chip 10 according to the embodiment in Figure 5 of the semiconductor layer stack 2 is on a

Carrier substrate 11 is applied. The growth substrate 1 and the layers up to and including the masking layer 6 are removed from the semiconductor layer stack. 2

On the n-doped layer 2b, which is remote from the carrier substrate 11, a roughening 13 for improving a light outcoupling is generated. The roughening 13 extends through the coalescing layer 7 through up to the or into the n-doped layer 2b, so that locally the

Middle layer 9 is exposed from AlGaN. An average depth of the roughening is preferably between 300 nm and 2.5 μπι. For example extends the roughening 13 to

at least 1% or at least 2% and / or not more than 5% or not more than 10% or more than 15% in the n-doped layer 2b into, based on the thickness of the n-doped layer 2b. A radiation exit surface of the semiconductor layer stack 2 is thus formed in places by a material of the coalescing layer. 7 On the coalescing layer 7 passivation of a transparent material such as SiN or SiO may optionally be applied, in the figures not drawn.

Optionally two, for example, metallic electrical contact layers 12 are attached to the semiconductor layer stack. 2 The carrier substrate 11 facing away

Contact layer 12 may also be other than drawn in Figure 5, are located closer to the carrier substrate 11, as the middle layer 9. Furthermore, it may be in the

Semiconductor chip 10, deviating from Figure 5, also be a flip-chip. A further embodiment of the semiconductor chip 10 is shown in FIG. 6 The semiconductor layer stack 2 is connected via a connecting means 18, for example a solder attached to the carrier substrate. 11 The carrier substrate 11 facing side of the semiconductor layer stack 2 is via the first electrical connecting layer 14 and on

Carrier substrate 11 are electrically contacted.

The carrier substrate 11 opposite side of the

Semiconductor layer stack 2 is contacted by the second electrical connection layer sixteenth The second connection layer 16 penetrating the active layer 2a from the carrier substrate 11 and fro is guided laterally adjacent to the semiconductor layer stack 2 and can be contacted for example with a bonding wire, not shown.

The roughening 13 does not extend up to the second

Connection layer 16 approach. The connecting layers 14, 16 is isolated by a separating layer 15, for example of silicon oxide or silicon nitride from one another. The middle class and the coalescence are not in Figure 7

shown. The invention is not limited by the description referring to the

Embodiments limited to these. Rather, the invention includes any novel feature and any combination of

Features on what particular any combination of

includes features in the patent claims, even if this feature or this combination itself is not explicitly specified in the patent claims or exemplary embodiments.

This patent application claims the priority of German patent applications 10 2010 045 957.7, 10 2010 045 958.5 and 10 2010 052 the disclosure of which is hereby incorporated by reference 542.1.

Claims

claims
1. semiconductor chip (10) having a semiconductor layer stack (2) which is based on a material system of the group-III nitrides and at least one n-doped layer (2b), wherein
as an n-dopant than a heavier dopant Si of the IV. main group or a dopant from the VI. Main group of the chemical elements is used.
2. The semiconductor chip of claim 1,
wherein facing away from a carrier of a substrate (11)
Side of the n-doped layer (2b) at least one
Middle layer (9) made of AlGaN is grown with a thickness of between 5 nm and 50 nm,
Side facing away from a carrier substrate (11) of the
Middle layer (9) has a coalescing layer (7) from
doped or undoped GaN with a thickness of between 300 nm and formed μπι 1.2,
a roughening (13) of the coalescing layer (7) up to the forth and / or into the n-doped layer (2b) extends, a radiation exit surface of the
Semiconductor layer stack (2) in part by the
Coalescing layer (7) is formed, and
the middle layer (9) is exposed in places.
3. The semiconductor chip according to any one of the preceding claims, wherein the n-doped layer (2b) further comprises in addition to the n-type dopant Si as further dopant, wherein a ratio of the dopant concentrations of Si and the n-type dopant is between 0.25 and 0 , 4.
4. The semiconductor chip according to any one of the preceding claims, wherein the dopant concentration of the n-type dopant in the n-doped layer (2b) is greater than 1 x 10 19 1 / and the n-type dopant Ge, Sn, Pb, 0, S, Se or Te.
5. The semiconductor chip of the preceding claim,
wherein the n-type dopant Pb or 0.
6. The semiconductor chip according to any one of the preceding claims, wherein the semiconductor chip (10) is an opto-electronic chip that an intended for generating radiation active layer (2a) between the n-doped layer (2b) and a p-doped layer (2c).
7. The semiconductor chip according to any one of the preceding claims, wherein the semiconductor chip (10) is a InGaN LED and the semiconductor layer stack (2) has a one-sided electrical contact.
8. The semiconductor chip according to any one of the preceding claims, wherein the semiconductor chip (10) comprises a carrier substrate of silicon.
9. The semiconductor chip according to any one of the preceding claims, wherein the dopant concentration of the n-type dopant in the n-doped layer (2b) satisfies the following condition:
D x E dge Dis x N> 5 x 10 23 cm -4, with the layer thickness D of the n-doped layer (2b),
Di s Edge of the average dislocation density-scale content in the n-doped layer (2b) in cm with a value above 1 x 10 8 cm -2 and the N
Dopant concentration in the n-doped layer (2b) in cm. 3
The semiconductor chip of the preceding claim,
wherein the thickness D of between 0.4 and 3 μπι μπι is, DIS j ^ g g between 5 x 10 7 cm and Δ
1 x 109 cm is Δ, N is between
7 x 10 18 cm J and 5 x 10 19 cm and the term J is D x DIS j ^ g g x N at most 1 x 10 26 cm q is.
A method of manufacturing a semiconductor chip (10), comprising the steps of:
- providing a growth substrate (1),
- Epitaxial growth of a
Semiconductor layer stack (2) on a
Material system of the group-III-nitride-based, and
having at least one n-doped layer (2b), wherein an n-type dopant as a heavier dopant Si of the IV. main group or a dopant from the VI. Main group of the chemical elements is used.
Method according to the preceding claim,
wherein a light-emitting diode is manufactured and on the
the following layers are grown directly on one another and in the order given growth substrate (1):
- a seed layer (5) based on A1N,
- an intermediate layer (4) based on AlGaN, with an Al content in the direction away from the growth substrate (1) decreases, - a Anwachsschicht (8) based on GaN,
- a masking layer (6), based on SiN, wherein the masking layer (6) Anwachsschicht (8) is not completely covered,
- a coalescing (7) based on GaN,
- a middle layer (9) made of AlGaN, and
- the semiconductor layer stack (2a, 2b, 2c), based on InGaN. 13. Method according to the preceding claim,
wherein said seed layer (5) has a thickness between
comprises including 100 nm and 300 nm and is doped with Si or 0, and / or provided with In. 14. A method according to any one of claims 11 to 13,
wherein when growing a germanium-hydrogen
Compound, an organic germanium compound, tert-butyl-German, tert-butyl-tin, lead-tert-butyl, an organometallic compound of the type F4-Me with R an organic group, or a compound of the VI.
Main group is used with hydrogen or an organic radical.
15. The method according to any one of claims 11 to 14,
wherein the growth substrate (1) is a silicon substrate.
PCT/EP2011/066084 2010-09-19 2011-09-16 Semiconductor chip and method for producing the same WO2012035135A1 (en)

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