WO2012035135A1 - Microplaquette semi-conductrice et procédé de production - Google Patents

Microplaquette semi-conductrice et procédé de production Download PDF

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Publication number
WO2012035135A1
WO2012035135A1 PCT/EP2011/066084 EP2011066084W WO2012035135A1 WO 2012035135 A1 WO2012035135 A1 WO 2012035135A1 EP 2011066084 W EP2011066084 W EP 2011066084W WO 2012035135 A1 WO2012035135 A1 WO 2012035135A1
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Prior art keywords
layer
semiconductor chip
dopant
doped
growth
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PCT/EP2011/066084
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German (de)
English (en)
Inventor
Armin Dadgar
Alois Krost
Peter Stauss
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Osram Opto Semiconductors Gmbh
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Priority claimed from DE102010052542.1A external-priority patent/DE102010052542B4/de
Application filed by Osram Opto Semiconductors Gmbh filed Critical Osram Opto Semiconductors Gmbh
Publication of WO2012035135A1 publication Critical patent/WO2012035135A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02576—N-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02647—Lateral overgrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
    • H01L33/325—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen characterised by the doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the invention relates to a semiconductor chip comprising a semiconductor layer stack based on a group III nitride and a method for the production thereof.
  • Lead stress in the semiconductor layer stack which may adversely affect the semiconductor chip performance and may even lead to damage to the semiconductor layers of the stack.
  • damage to the layers of the stack may occur as damage.
  • Such damage due to Si dopants are for example in the
  • Preloading the layer to be grown For example, you can growing a GaN layer stack on one
  • Silicon growth substrate especially when doing
  • thick and heavily doped layers are a prerequisite for efficient light emitters, for example, which are to be produced on inexpensive silicon substrates which are available over a large area.
  • thick and heavily doped layers are found for electronic components such as p-i-n or Schottky transistors for high voltage applications
  • Si is used as a dopant, in particular, since silane as the starting material for the silicon doping has a low price and the simple use of silane makes the use of elements other than dopant as unnecessarily complicated. Also with regard to a reduction of the bracing problem could be seen so far no advantages of other group IV dopants, since the chemistry of the substances is very similar and therefore the same problems can be expected.
  • GaN layers on a heterosubstrate generally results in an increased dislocation density within the GaN layers.
  • SiN x masking layers are found
  • Such masking layers are among others also known by the term “in situ SiN". Masking layers "known and for example in the
  • Such a masking layer is in this case partially applied after it has grown at least a first group III nitride layer of the semiconductor layer stack.
  • the masking layer is typically applied by a reaction of silicon with nitrogen (ammonia as a source).
  • ammonia as a source
  • the person skilled in the art can achieve that a SiN layer which is only partially formed is formed.
  • a further GaN layer is produced starting from the non-SiN-covered regions. This first grows in a 3-dim island structure on the material of the nucleation-free areas of the first GaN layer and spreads with increasing
  • the parasitic reaction of silicon with nitrogen to form SiN can also occur, so that here too only a partial overgrowth takes place, and a desired fast
  • dislocation-reduced layer is hindered, or, depending on the process, the coalescence emanates unwanted germs newly forming on the SiN mask.
  • the semiconductor chip has a
  • the semiconductor chip is preferably used for
  • Semiconductor layer stack may be included in addition.
  • a middle layer with a thickness of up to 50 nm it may be different from the above-mentioned values for n, m and instead that 0.75 ⁇ n ⁇ 1.
  • an n-doped layer based on the material system of the group III nitrides can also be understood to mean an n-doped substrate which is deposited on the substrate
  • Semiconductor chip thus at least as semiconductor layer stack on the n-doped substrate on which further layers may be applied.
  • the semiconductor chip is a
  • the semiconductor chip has an active layer provided for the generation of radiation between the n-doped layer and a p-doped layer.
  • An optoelectronic semiconductor chip is, in particular, a semiconductor chip which enables the conversion of electronically generated data or energies into light emission or vice versa.
  • the semiconductor chip has an active layer provided for the generation of radiation between the n-doped layer and a p-doped layer.
  • An optoelectronic semiconductor chip is, in particular, a semiconductor chip which enables the conversion of electronically generated data or energies into light emission or vice versa.
  • the semiconductor chip has an active layer provided for the generation of radiation between the n-doped layer and a p-doped layer.
  • An optoelectronic semiconductor chip is, in particular, a semiconductor chip which enables the conversion of electronically generated data or energies into light emission or vice versa.
  • the semiconductor chip has an active layer provided for the generation of radiation between the n-doped layer and a p-d
  • Optoelectronic semiconductor chip a radiation-emitting semiconductor chip.
  • n-doped layer or layers of the semiconductor layer stack with improved n-type doping.
  • claimed dopants can thus be a thin and
  • a thick highly n-doped group III nitride layer can be realized on a sapphire, silicon carbide or silicon substrate.
  • the dopant must be heavier or larger than silicon so that it does not act as an amphoteric dopant or as a p-dopant.
  • group VI dopants are suitable.
  • the active layer of the semiconductor layer stack preferably contains a pn junction, a double heterostructure, a single quantum well (SQW, single quantum well) or a
  • MQW Multiple quantum well structure
  • Dimensionality of quantization includes, among other things, quantum wells, quantum wires and quantum dots, and each one
  • This material does not necessarily have to have a mathematically exact composition according to the above formula. Rather, the material may comprise one or more dopants as well as additional constituents which the
  • n-dopant is Ge, Sn, Pb, O, S, Se or Te. In this case, therefore, as n-dopant a
  • n-dopant silicon is also used as n-dopant.
  • the n-doped layer is therefore doped in this case with Ge and Si.
  • the tensile strain and the doping can be influenced independently.
  • the dopant concentration of the n-dopant in the n-doped layer is greater than 10 19 l / CNW. So it becomes an n-doped layer on one
  • the semiconductor chip is an InGaN LED.
  • the semiconductor chip is preferably a thin-film chip.
  • Thin film chip is considered in the context of the application, a semiconductor chip during its production, the growth substrate on which the semiconductor layer stack epitaxially
  • the semiconductor layer stack of the semiconductor chip can be applied, for example, on a carrier substrate.
  • the carrier substrate used is preferably a silicon-containing material
  • Carrier substrate provided, in particular when already the growth substrate is a silicon-containing substrate.
  • the semiconductor chip and / or the semiconductor layer stack has a single-sided electrical
  • the semiconductor chip can then be a flip-chip. It is also possible that an electrical contact is constructed, as in the
  • Front of the semiconductor layer stack done. For electrical contact are on one side of the
  • the semiconductor layer stack arranged a first and second electrical connection layer, each for electrical Contacting the layer stack of a conductivity type are provided.
  • the first and second electrical connection layer arranged a first and second electrical connection layer, each for electrical Contacting the layer stack of a conductivity type are provided.
  • Connection layer are electrically isolated from each other, for example by means of an electrically insulating separation layer.
  • the one-sided contacting technology of the chip allows a low-resistance contact. Because of the one-sided
  • Semiconductor layer stack in particular the active layer can be ensured.
  • the dopant concentration of the n-type dopant in the n-doped layer fulfills the following
  • D is in particular the layer thickness of the entire n-doped layer and optionally also subsequent thereto
  • N is a highest donor concentration in the n-doped layer.
  • n-doped layer with a Thickness D of at least 100 nm produces strong tensile stress at high dislocation concentrations.
  • Doping is slightly less advantageous at the beginning of the n-doped layer than seen at the end in the growth direction, since the reduced stress in the growing layer has a stress-reducing effect on a thicker part of the layer than at the end.
  • This n-doped layer is preferably at least 0, 6 ⁇ thick and has approximately on the upper at least 400 nm
  • Step dislocation density typically above 2x10 9 cm ⁇ This results from the formula according to claim 1, a value of
  • the thickness D is between 300 nm and 5 ⁇ , in particular between 0.4 ⁇ and 3 ⁇ or between 0.5 ⁇ and 2.0 ⁇ inclusive.
  • DlS ⁇ g g lies to
  • the concentration N can be between 1 x 10 18 cm J and 1 x 10 (J cm or J is between 7 x 10 I ⁇ cm 3 and 5 x 1 ⁇ 19 cm _ lie. 3
  • the lower limit for the expression D x DlSßdge x N is a
  • Upper limit may alternatively or additionally at most
  • Dislocation density of, for example, greater than 5 x 10 ⁇ cm ⁇ 2 grown.
  • the latter comprises a highly n-conductive layer, in particular based on GaN, this layer preferably following an in situ or ex situ masking layer.
  • the highly n-conductive layer which is applied to the semiconductor chip
  • Masking layer follows, an n-doping above lO-L ⁇ cm _ 3 or ⁇ ⁇ cm _ 3 on. This n-doping takes place in particular over a layer thickness of 10 nm to 300 nm inclusive.
  • a high n-type doping can be realized, without appreciably hindering or delaying subsequent coalescence, as would be the case with Si doping, since Si promotes three-dimensional growth and thus a two-dimensionally growing layer is difficult to achieve, usually only after the growth of very thick layers.
  • the masking layer comprises or consists, for example, of SiN, SiO, SiON or BN or another material which does not or only inhibits wetting, which promotes three-dimensional growth, and / or growth conditions which are independent of such do a masking layer.
  • One way to accomplish this is to add a heavy doping "10 ⁇ - ⁇ cm - ⁇ approximately Si, over one
  • the masking layer has a thickness of at most 2 nm, in particular of at most 1 nm.
  • the thickness of the masking layer is on average one or two monolayers.
  • a coverage of the masking layer is between 20% and 80% inclusive, or between 55% and 70% inclusive of the underlying layer.
  • the growth substrate and / or the growth layer, seen in plan view, to the said portion covered by a material of the masking layer is between 20% and 80% inclusive, or between 55% and 70% inclusive of the underlying layer.
  • the latter has a coalescing layer which is the one of the coalescing layer
  • Masking layer in particular immediately follows and in which the coalescence takes place, starting from openings in the masking layer.
  • This layer is in particular a GaN layer. A thickness of this
  • Coalescing layer is preferably between inclusive
  • the coalescing layer may be undoped or substantially undoped.
  • the semiconductor chip comprises a middle layer which is based in particular on AlGaN.
  • An Al content of the middle layer is preferably between 75% and 100% inclusive.
  • the middle layer is between 5 nm and 50 nm inclusive, for example between 10 nm and 10 nm inclusive
  • the middle layer may be between the high n-type layer and the masking layer. In particular, the middle layer directly adjoins the highly n-conductive layer and the coalescing layer.
  • Detection of the dopant (s) in the semiconductor chip can be carried out, for example, by a secondary ion mass spectrometry analysis (SIMS for short).
  • SIMS secondary ion mass spectrometry analysis
  • Masking layers detectable or existing at large islands of the masking layer usually on a micrometer scale doping fluctuations due to a
  • cross-cathodoluminescence or cross-section transmission electron microscopy cathodoluminescence can also be determined by the different positions of donor-bound
  • Excitons or a line broadening of a luminescence can be detected, even if the masking layer is removed, for example by an etching process.
  • a thickness of the semiconductor layer stack is at least 1 ⁇ or at least 2 ⁇ and / or at most 10 ⁇ or at most 5 ⁇ . This may be necessary to functional
  • Layers such as an active layer accommodate, and / or to realize a contact and current spreading and / or to ensure sufficient isolation to the growth substrate.
  • Semiconductor layer stack preferred. This can be achieved for example by graded Al-containing
  • Partial layers comprise, in particular between two and five partial layers inclusive.
  • a thickness of the intermediate layers as a whole is, for example, between 20 nm and 500 nm inclusive, in particular between 50 nm and 250 nm inclusive.
  • the seed layer which is based in particular on AlN, and / or also a GaN layer grown directly thereon, is doped.
  • a doping of the seed layer, which can also serve as a buffer layer, takes place in particular with silicon or with
  • the seed layer indium in a proportion of up to 20% or up to 10%. Silicon or sapphire is particularly preferably used as the growth substrate.
  • the stress is reduced to a lesser extent
  • a method for producing an optoelectronic semiconductor chip is specified.
  • a semiconductor chip can be produced, as described in connection with one or more of the abovementioned embodiments.
  • Features for the method are therefore also disclosed for the semiconductor chip and vice versa.
  • a method for producing a semiconductor chip comprises the following method steps: Providing a growth substrate,
  • n-dopant a heavier dopant than silicon from the IV.
  • Main group of chemical elements is used.
  • Such a method allows the growth of GaN layers on, for example, a silicon substrate with a high degree of n-doping, in which the strain in the
  • the method finds application for the generation of homoepitaxial
  • the growth substrate is an SOI substrate ("silicon on insulator" substrate).
  • the growth substrate may be a sapphire or SiC substrate.
  • a germanium-hydrogen compound an organic germanium compound, tert. butyl german, tert. butyl-tin, tert. -butyl-lead, an organometallic compound of the type F4_Me with R one
  • the doping with germanium is to be preferred over the other elements, since the available precursors are easy to use and the vapor pressure of the dopant above the layer at the most prevalent in the group III nitride epitaxy process temperatures above 1000 ° C well controlled is.
  • the other precursors are up
  • Oxygen in the process may be involved in the epitaxy process be undesirable because it is considered the main contaminant and
  • organometallic gas phase epitaxy at least in organometallic gas phase epitaxy also undesirable reactions with the organometallic
  • FIGS. 1, 2A, 2B, 2D each show a schematic cross section of an exemplary embodiment of a semiconductor chip according to the invention
  • FIG. 2C is a diagram in which the tension against the
  • FIG. 3 is a flowchart relating to an inventive device
  • Figures 4 to 6 are schematic cross-sectional views of further embodiments of
  • Size ratios among each other are basically not to be considered as true to scale. Rather, individual can Components, such as layers, structures,
  • FIG. 1 shows an embodiment of a semiconductor chip 10 in cross section.
  • the semiconductor chip 10 has a
  • Growth substrate 1 having, for example, sapphire, Sic or silicon.
  • the growth substrate may also be a silicon on insulator (SOI) substrate or a group I I nitride substrate.
  • SOI silicon on insulator
  • the semiconductor layer stack 2 is based on a group III nitride material system.
  • the semiconductor layer stack 2 is based on the
  • the semiconductor layer stack 2 has an active layer 2 a.
  • the active layer 2a is
  • the semiconductor chip 10 is an LED ("light-emitting diode").
  • the active layer 2 a of the semiconductor layer stack 2 is arranged between an n-doped layer 2 b and a p-doped layer 2 c.
  • the n-doped layer is in
  • the n-doped layer may be covered by a masking layer and
  • the n-doped layer 2b has a heavier dopant than silicon from the IV.
  • Main group or a dopant from the VI. Main group of chemical elements.
  • As n-dopant of the IV. Main group is thus Ge, Sn and Pb use.
  • Dotand the VI. Main group finds
  • the dopant concentration of the n-dopant in the n-doped layer 2b is preferably greater than 5 ⁇ ⁇ 1 / cm 2.
  • the tensile strain of the semiconductor layer material which conventionally occurs during the cooling process or which occurs due to the dopant concentration can be avoided.
  • Layers with such a high doping are particularly advantageous for a high transverse conductivity and optimized contact resistance. It is also possible, the n-doped layer 2b with improved n-conductivity
  • the n-doped layer 2b and the p-doped layer 2c of the semiconductor layer stack 2 may be composed of a layer sequence.
  • the n-doped layer 2b and the p-doped layer 2c of the semiconductor layer stack 2 may be composed of a layer sequence.
  • Semiconductor layer stack 2 a plurality of n-doped
  • Layers 2b which are arranged between growth substrate 1 and active layer 2a.
  • a plurality of p-doped layers can be arranged on the side of the active layer 2 a facing away from the growth substrate 1.
  • the dopant concentration of the n-dopant in the n-doped layer or the n-doped layers 2b preferably satisfies the following condition: D x DIS Edge x N> 5 x 10 ⁇ cm -4, where D is the layer thickness of the n-doped layer 2a or the sequence of layers of the n-doped layer, DIS ⁇ g g is the average dislocation density levels proportion in the range of n- doped layer 2b or the n-doped layers in cm-2 with a value above 1 x 10 ⁇ cm- ⁇ and N the
  • n-dopant Due to the choice of the n-dopant, it is advantageous to avoid tensile stresses in the semiconductor chip, wherein at the same time a thick and highly doped group III nitride layer on silicon, sapphire or SiC can be realized. With such a heavy n-dopant can thus be the time-consuming and not always necessary reduction of the dislocations, the tensile stress at
  • the semiconductor chip 10 advantageously has a
  • the same side of the semiconductor chip 10 are arranged and from each other, for example by means of an insulating
  • Separating layer are electrically isolated from each other.
  • n-dopant which is heavier than silicon, can be a large-scale, cost-effective and
  • Semiconductor chip 10 of FIG. 2A differs from the semiconductor chip of FIG. 1 by additional layers 3, 4 which are arranged between growth substrate and semiconductor layer stack 2.
  • additional layers 3, 4 which are arranged between growth substrate and semiconductor layer stack 2.
  • a buffer layer 3 is applied to the growth substrate 1.
  • Such buffer layers 3 are in particular for growing on silicon-containing
  • an aluminum-containing intermediate layer 4 is arranged, on which the layers of the semiconductor layer stack 2 are epitaxially grown.
  • the aluminum-containing layer is
  • an AIN seed layer for example, an AIN seed layer.
  • FIG. 2A is identical to the embodiment of FIG.
  • Semiconductor chip 10 of Figure 2B differs from the semiconductor chip of Figure 1 by additional layers 5, 6, 7, between the growth substrate and
  • Semiconductor layer stack 2 are arranged.
  • a first group III nitride layer 5 is applied to the growth substrate 1.
  • a partial SiN masking layer 6 is arranged.
  • the second group III nitride layer 7 is arranged, in such a way
  • the layers of the semiconductor layer stack 2 are epitaxially grown.
  • FIG. 2B is identical to the embodiment of FIG.
  • FIG. 2C shows a diagram in which
  • the dashed line shows the production of a semiconductor chip with an n-dopant silicon
  • the solid line shows a semiconductor chip with an n-dopant Ge.
  • the method relates, for example, to the production of a semiconductor chip according to the exemplary embodiment of FIG. 2A.
  • the graph of Figure 2C shows the curvature measurement during the growth of a silicon-doped GaN layer
  • the semiconductor layers with silicon in the later manufacturing process in particular at about 60 minutes and more, have a lower stress than when doping with German and consequently a higher tensile stress after the cooling process (80 min).
  • a dopant such as German can thus be a mechanical damage to the layers, which can occur due to these occurring stresses are reduced.
  • the production method for the diagram of FIG. 2C can comprise the following method steps:
  • Gallium precursors the growth of a GaN layer of the
  • Germanium as a dopant diluted in hydrogen advantageous suitable.
  • this dopant can be a
  • Silicon growth substrate can be avoided.
  • the dilution of German in hydrogen is usually lower than for silane in hydrogen, because the installation in comparison
  • AIN seed layer is highly doped and grown directly on a GaN layer.
  • a high dislocation density of greater than 5 x 10 ⁇ cm ⁇ 2 at the beginning of the heteroepitaxial growth can be without the production of a significant
  • Silicon substrate are made possible.
  • Another application is the growth of thick n-doped Group III nitride layers, mostly by means of HVPE, on a carrier substrate for the production of pseudo-substrates which, detached from the carrier substrate, serve as high-quality substrates for hetero and homoepitaxy:
  • a strong inhomogeneous curvature usually occurs for conductive substrates heavily doped with Si, which curvature is shown by later abrasion of the substrate pointing to the growth substrate
  • Tensile stress can occur during growth to cracking. Furthermore, a low dislocation density is usually achieved by forced 3D growth, either by the ELOG method, by means of in situ deposition
  • Mask layers which are usually made of SiN, or achieved by a low seeding density, which leads to a 3D growth.
  • the subsequent coalescence is influenced by the doping with Si by the parasitic SiN layer formation in an undesirable manner. If, instead of silicon doped with a dopant according to the invention, the resulting tensile stress at the beginning of the growth can be reduced and realized in three-dimensional island growth of this uninfluenced and thus simpler than n-doped layer. This subsequently avoids cracks during growth and provides for less
  • FIG. 2D A further exemplary embodiment of the semiconductor chip 10 with a masking layer 6 is shown in FIG. 2D.
  • the approximately 20 nm thick seed layer 5 is grown from A1N.
  • the thickness of the seed layer 5 is preferably between 100 nm and 250 nm, for example approximately 150 nm.
  • an n-type doped intermediate layer 4 made of GaN.
  • the Masking layer 6 applied from SiN. This in turn is followed by the growth of the GaN layer 2b of the
  • This growth is initially three-dimensional, as evidenced by the onset of reflected intensity in in situ reflectometry measurements, for example. After several hundred nanometers of growth of the GaN layer 2b, this intensity increases until it reaches a maximum value again and the layer is thus closed in two dimensions.
  • silane is usually added during the GaN growth.
  • silicon inhibits two-dimensional growth and promotes the three-dimensional, which delays the coalescence process and requires very high layer thicknesses and thus long growing time.
  • Silicon doping by 1 x ⁇ ⁇ cm ⁇ or higher is the
  • a thickness of the layers 2a, 2c together is between 200 nm and 300 nm inclusive, as is possible in all other embodiments.
  • Growth substrate 1 and optionally also the masking layer can, as in all other embodiments, na the generation of the semiconductor layer stack 2 are removed from this.
  • Voltage compensating layers detectable. Furthermore, it can be concluded from strain gradients, as can be obtained for example by means of high-resolution Raman spectroscopy, and also from the dislocation density and the propagation of these on the substrate type. So are usually strain on the invention
  • FIG. 3 shows a flow chart
  • Method steps for producing a semiconductor chip according to the invention shows.
  • a silicon substrate is provided.
  • a buffer layer is grown. Subsequently, in the
  • Step 302 an Al-containing intermediate layer is applied to the buffer layer. This happens
  • Step 304 a doping of the layer or layers of the semiconductor layer stack then takes place. After the doping process is the so
  • FIG. 10 Another embodiment of the semiconductor chip 10 is shown in FIG. On a 111 or 110 surface of a silicon substrate 1 is a buffer layer 3, which also acts as a seed layer 5, grown.
  • the seed layer 5 has A1N and is undoped or mixed with Si, O or In.
  • a thickness of the seed layer 5 is preferably between 100 nm and 300 nm inclusive.
  • the seed layer 5 is followed by the intermediate layer 4, which has four layers. These layers are not shown in FIG.
  • the individual layers are made of AlGaN and each have a thickness of about 50 nm. In the direction away from the substrate 1, an Al content decreases and amounts to approximately 95%, 60%, 30% and 15% in the respective layers.
  • the seed layer 5 is followed by a growth layer 8.
  • the growth layer 8 is a GaN layer having a preferable thickness between 50 nm and 300 nm inclusive
  • Growth layer 8 may be doped or undoped. If the growth layer 8 is doped, then there is one
  • Dopant concentration preferably by at least a factor 2 or factor 4 under a dopant concentration of the n-doped layer 2b.
  • the masking layer 6 of SiN is applied on the growth layer 8.
  • a degree of coverage of the masking layer 6, based on the growth layer 8, is about 65%.
  • the coalescence layer 7 is grown on the growth layer 8. Starting from these openings, the coalescing layer 7 grows above the
  • the coalescing layer 7 can be doped in the same way as the growth layer 8.
  • the coalescing layer 7 follows a middle layer 9.
  • the middle layer 9 is an AlGaN layer having a thickness of about 15 nm. Other than drawn in the figures, it is also possible that a plurality of middle layers 9 are present.
  • the n-doped layer 2b of the semiconductor layer stack 2 based on InGaN is then grown on the middle layer 9. It is the n-doped layer 2b doped with a concentration of between 5 x 10 18 cm J to
  • D e doping is preferably carried out with Ge or with one of the other dopants mentioned above.
  • a thickness D of the n-doped layer 2 b, measured from the middle layer 9 to the active layer 2 a, is preferably approximately 1.5 ⁇ m to 2.5 ⁇ m. In one of the middle class 9
  • the nearest area with a preferred thickness of at least 100 nm and / or at most 500 nm is the
  • Optional dopant concentration decreases and 1017 cm in this area is between 5 x J and
  • Dopant concentrations of Si and the dopant such as Ge or Te are then preferably between 0.2 and 0.6 inclusive or between 0.25 and 0.4 inclusive.
  • the n-doped layer 2b is doped with Si at approximately 5 x 10 18 cm J and Ge or Te at approximately 1.5 x 10 19 cm J.
  • the semiconductor layer stack 2 is on one side
  • Carrier substrate 11 applied.
  • the growth substrate 1 and the layers up to and including the masking layer 6 are removed from the semiconductor layer stack 2.
  • a roughening 13 is produced to improve a light extraction efficiency.
  • the roughening 13 extends through the coalescing layer 7 through to or into the n-doped layer 2b, so that in places the
  • Middle layer 9 is exposed from AlGaN.
  • An average depth of the roughening is preferably between 300 nm and 2.5 ⁇ .
  • the roughening 13 is sufficient
  • a radiation exit surface of the semiconductor layer stack 2 is thus in places by a Material of the coalescence layer 7 is formed.
  • a passivation made of a transparent material such as SiN or SiO 2 may be applied to the coalescing layer 7, not shown in the figures.
  • two, for example metallic, electrical contact layers 12 are attached to the semiconductor layer stack 2. Which faces away from the carrier substrate 11
  • Contact layer 12 may also, in contrast to FIG. 5, be located closer to the carrier substrate 11 than the middle layer 9
  • semiconductor chip 10 also act on a flip-chip.
  • FIG. 1 Another embodiment of the semiconductor chip 10 is shown in FIG.
  • the semiconductor layer stack 2 is fastened to the carrier substrate 11 via a connection means 18, for example a solder.
  • the carrier substrate 11 facing side of the semiconductor layer stack 2 is via the first electrical connection layer 14 and over the
  • Carrier substrate 11 contacted electrically.
  • the carrier substrate 11 facing away from the
  • Semiconductor layer stack 2 is contacted via the second electrical connection layer 16.
  • the second connection layer 16 penetrates the active layer 2a from the carrier substrate 11 and is guided laterally next to the semiconductor layer stack 2 and can be contacted, for example, with a bond wire, not drawn.
  • the roughening 13 is not enough to the second
  • Connection layer 16 zoom.
  • the middle layer and the coalescing layer are not in FIG. 7

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Abstract

L'invention concerne une microplaquette semi-conductrice (10) comprenant un empilement (2) de couches semi-conductrices, ledit empilement (2) de couches semi-conductrices étant à base d'un système de matériaux de nitrure du groupe III et présentant au moins une couche (2b) dopée n. Un dopant plus lourd que le silicium du groupe principal IV ou un dopant du groupe principal VI du tableau périodique des éléments trouve une application comme impureté de dopage n. L'invention concerne également un procédé de production d'une telle microplaquette semi-conductrice (10).
PCT/EP2011/066084 2010-09-19 2011-09-16 Microplaquette semi-conductrice et procédé de production WO2012035135A1 (fr)

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DE102010052542.1A DE102010052542B4 (de) 2010-11-25 2010-11-25 Halbleiterchip und Verfahren zu dessen Herstellung
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CN111653625A (zh) * 2019-03-04 2020-09-11 3-5电力电子有限责任公司 堆叠状的高截止的iii-v族功率半导体二极管
CN113013024A (zh) * 2019-12-20 2021-06-22 阿聚尔斯佩西太阳能有限责任公司 气相外延方法

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Cited By (10)

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Publication number Priority date Publication date Assignee Title
DE102012204553A1 (de) * 2012-03-21 2013-09-26 Freiberger Compound Materials Gmbh Verfahren zur Herstellung von III-N-Templaten und deren Weiterverarbeitung, und III-N-Template
WO2013139888A1 (fr) 2012-03-21 2013-09-26 Freiberger Compound Materials Gmbh Procédé de production de matrices de iii-n et leur traitement ultérieur et matrices de iii-n
US9896779B2 (en) 2012-03-21 2018-02-20 Freiberger Compound Materials Gmbh Method for producing III-N single crystals, and III-N single crystal
US10309037B2 (en) 2012-03-21 2019-06-04 Freiberger Compound Materials Gmbh Method for producing III-N templates and the reprocessing thereof and III-N template
US10584427B2 (en) 2012-03-21 2020-03-10 Freiberger Compound Materials Gmbh Processes for producing III-N single crystals, and III-N single crystal
US10883191B2 (en) 2012-03-21 2021-01-05 Freiberger Compound Materials Gmbh Method for producing III-N templates and the reprocessing thereof and III-N template
DE102012204553B4 (de) 2012-03-21 2021-12-30 Freiberger Compound Materials Gmbh Verfahren zur Herstellung eines Templats, so hergestelltes Templat, dessen Verwendung, Verfahren zur Herstellung von III-N-Einkristallen, Verfahren zur Herstellung von III-N-Kristallwafern, deren Verwendung und Verwendung von Maskenmaterialien
CN111653625A (zh) * 2019-03-04 2020-09-11 3-5电力电子有限责任公司 堆叠状的高截止的iii-v族功率半导体二极管
CN113013024A (zh) * 2019-12-20 2021-06-22 阿聚尔斯佩西太阳能有限责任公司 气相外延方法
CN113013024B (zh) * 2019-12-20 2024-03-15 阿聚尔斯佩西太阳能有限责任公司 气相外延方法

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