DE102010052542B4 - Semiconductor chip and method for its manufacture - Google Patents

Abstract

Semiconductor chip (10) with a semiconductor layer stack (2) which is based on a group III nitride material system and has at least one n-doped layer (2b), Sn or Pb being used as the n-dopant, and the dopant concentration of the n-dopant in the n-doped layer (2b), the following condition is met: D×DisEdge×N≥5×1023 cm−4, with D being the layer thickness of the n-doped layer (2b), DiSEdge the average dislocation density with a step component in the area of the n-doped layer (2b) in cm-2 having a value above 1x108cm-2 and N the dopant concentration in the n-doped layer (2b) in cm-3.

Description

The invention relates to a semiconductor chip having a semiconductor layer stack based on a group III nitride and a method for its production.

Conventionally, layers of a semiconductor layer stack based on a group III nitride material system are often grown on a hetero-substrate such as sapphire, SiC or silicon. In order to generate an n-type conductivity in the layers of the semiconductor layer stack, these are often doped, silicon being used as the n-type dopant in most cases, which has established itself as an easy-to-handle and efficient dopant. However, such a doping can lead to a tensile stress in the semiconductor layer stack, which can negatively affect the semiconductor chip performance and even lead to damage to the semiconductor layers of the stack. Cracking of the layers of the stack, for example, can occur as damage. Such damage due to Si doping is described, for example, in the publication "Effect of Si doping on strain, cracking, and microstructure in GaN thin films grown by metal-organic chemical vapor deposition", Romano et al., J. Appl. Phys., Vol. 87, No. 11, June 1, 2000.

For example, when a GaN layer stack is grown on a silicon growth substrate, in particular during the cooling process used, tensile stresses can occur in the layers. Conventionally, such tensile strains are compensated by means of a compressive pre-strain of the group III nitride semiconductor layer stack during the growth. Such prestresses are, for example, in the publication "GaN-based epitaxy on silicon: stress measurements", Krost et al., phys. stat. sol. (a) 200, no. 1, 26-35 (2003). However, this desired compressive prestressing is disadvantageously reduced when the layers are highly doped with silicon, so that in turn the layers can crack during the cooling process of the layers.

When growing GaN layers on a sapphire substrate, on the other hand, compressive stress occurs during the cooling process due to the thermal mismatch of the materials. However, a high Si doping and/or a high layer thickness of the n-doped layers of the layer stack can already lead to cracking in the epitaxial layers during the deposition due to the tensile strain generated thereby.

However, thick and highly doped layers are a prerequisite for efficient light emitters, for example, which are to be produced on cheap silicon substrates that are available over a large area. In addition, thick and highly doped layers are used for electronic components such as p-i-n or Schottky transistors for high-voltage applications.

Although it is possible in principle to reduce the tensile stresses in such semiconductor chips, it requires a great deal of effort. The reason for this is the typically high dislocation density of greater than or about 1 × 10 ⁹ cm ^-2 By adding Si of greater than or about 1 × 10 ¹⁸ cm ^-3 , an already built-in compressive strain is reduced by bending the dislocations, or even one additional tensile stress generated. This effect is, inter alia, in the publication "Si doping effect on strain reduction in compressively strained Al0.49Ga0.51N thin films", Cantu et al., Appl. physics Lett., Vol. 83, No. 4, July 28, 2003.

However, high doping is necessary, among other things, for good contact formation, with electron concentrations above 5×10 ¹⁸ cm ^-3 being aimed at for this.

The growth of GaN layers on a hetero-substrate generally leads to an increased density of dislocations within the GaN layers. In order to reduce these dislocation densities, SiN _x masking layers are used, among other things. Such masking layers are known to those skilled in the art, inter alia, under the term “insitu SiN masking layers” and are described, for example, in the publication “Anti-Surfactant in III-Nitride Epitaxy—Quantum Dot Formation and Dislocation Termination”, Tanaka et al., Jpn. J. Appl. Phys., Vol. 39 (2000), Pl. 8B. Such a masking layer is partially applied to at least a first group III nitride layer of the semiconductor layer stack after it has been grown. The masking layer is typically applied by reacting silicon with nitrogen (ammonia as the source). With a correspondingly thinly deposited layer, the person skilled in the art can achieve that an only partially formed SiN layer is formed. In a further GaN deposition step, starting from the areas not covered with SiN, another GaN layer is produced.

This initially grows in a 3-dimensional island structure on the areas of the first GaN layer that are free of material from the nucleation layer and spreads out in the lateral direction over the SiN masking layer as the growth time increases. In In this area, the dislocation density is significantly reduced.

If the second GaN layer is doped with Si for improved electrical conductivity, the parasitic reaction of the silicon with nitrogen to form SiN can also occur, with the disadvantage that only partial overgrowth takes place here, and a desired rapid coalescence of the growth islands to form a closed dislocation-reduced layer is hindered or, depending on how the process is carried out, the coalescence is caused by undesired new nuclei forming on the SiN mask.

The pamphlet U.S. 2010/0 230 714 A1 describes a gallium nitride compound semiconductor light emitting device.

The pamphlet U.S. 6,686,608 B1 describes a light emitting nitride semiconductor device.

The pamphlet U.S. 5,825,052 A describes a light-emitting semiconductor device.

Visconti, P. et al. describe in Appl. physics Lett., 2000, vol. 77, no. 22, pp. 3532-3534 the dislocation density in GaN determined by photoelectrochemical etching and wet etching.

It is the object of the present application to specify an improved semiconductor chip which has high n-doping and at the same time a reduced risk of the layers of the semiconductor chip tearing. It is also the object of the present application to specify a manufacturing method for growing a GaN layer on a growth substrate with a high degree of n-doping, in which the risk of damage to the GaN layer is reduced and, in addition, rapid coalescence of a GaN layer subsequent to a possibly applied masking layer is not disadvantageously prevented.

These objects are achieved, inter alia, by a semiconductor chip having the features of claim 1 and by a method for producing such a semiconductor chip having the features of claim 8 . Advantageous developments of the semiconductor chip and the method for its production are the subject matter of the dependent claims.

The semiconductor chip has a semiconductor layer stack which is based on the group III nitride material system and has at least one n-doped layer. A heavier dopant than silicon from the IV. main group or a dopant from the VI. Main group of chemical elements used.

The semiconductor chip is preferably used for electronic applications and preferably has highly conductive or highly doped n-layers in the GaN semiconductor layer stack.

Within the scope of the application, an n-doped substrate based on the group III-nitride material system, ie for example GaN, can also be understood as an n-doped layer based on the group III-nitride material system. In this case, the semiconductor chip thus has the n-doped substrate, at least as a semiconductor layer stack, on which further layers can be applied.

In one development, the semiconductor chip is an optoelectronic semiconductor chip. In this case, the semiconductor chip has an active layer provided for generating radiation between the n-doped layer and a p-doped layer. An optoelectronic semiconductor chip is in particular a semiconductor chip that enables the conversion of electronically generated data or energy into light emission or vice versa. For example, the optoelectronic semiconductor chip is a radiation-emitting semiconductor chip.

When using a dopant as claimed for the n-doping, the undesired effects discussed above relating to the tensile strain and/or the parasitic reaction advantageously do not occur. In particular, the tensile strain that occurs during the cooling process and/or the tensile strain that occurs due to the high n-doping and only partial overgrowth due to a high silicon content can be reduced or prevented by means of a dopant as claimed.

In addition, it is possible to deposit the n-doped layer or layers of the semiconductor layer stack in a correspondingly thin manner with improved n-conductivity. A thin and highly doped n-layer can thus be produced with the claimed dopant.

The use of a dopant as claimed thus leads to a reduction in the formation of cracks and damage to the n-layer of the semiconductor layer stack, in contrast to the use of silicon as a dopant. In addition, a thick, highly n-doped Group III nitride layer can be realized on a sapphire, silicon carbide or silicon substrate. The dopant must be heavier or larger than silicon so that it does not act as an amphoteric dopant or as a p-dopant. Alternatively, group VI dopants can be used.

The active layer of the semiconductor layer stack preferably contains a pn junction, a double heterostructure, a single quantum well (SQW, single quantum well) or a multiple quantum well structure (MQW, multi quantum well) for generating radiation. The term quantum well structure has no meaning with regard to the dimensionality of the quantization. It includes, but is not limited to, quantum wells, quantum wires, and quantum dots, and any combination of these structures.

Based on a material system of group III nitrides means here and in the following that the semiconductor layer sequence of the semiconductor layer stack is a layer sequence deposited epitaxially on a growth substrate, which has at least one layer of a nitride/III/compound semiconductor material, preferably Al _n Ga _m In _{1 -mn} N, where 0≦n, m≦1, n+m≦1. This material does not necessarily have to have a mathematically exact composition according to the above formula. Rather, the material may include one or more dopants as well as additional components that do not substantially change the characteristic physical properties of the Al _n Ga _m In _1-mn N material. For the sake of simplicity, however, the above formula only contains the essential components of the crystal lattice (Al, Ga, In, N), even if these can be partially replaced by small amounts of other substances.

In a development, the n-dopant is Ge, Sn, Pb, O, S, Se or Te. A heavier dopant from main group IV of the chemical elements than silicon, ie Ge, Sn or Pb, can be used as the n-dopant. As a student from the VI. Main group is used, for example, O, S, Se or Te. These dopants do not show the undesired effects from the prior art, since these dopants do not contribute to the bending or migration of dislocations and thus promote tensile stress.

In a further development, silicon is used as an n-dopant in addition to Ge. In this case, the n-doped layer is therefore doped with Ge and Si. The tensile strain and the doping can thus be influenced independently of one another.

In a development, the dopant concentration of the n-dopant in the n-doped layer is greater than 10 ¹⁹ 1/cm ³ . An n-doped layer is therefore grown on a growth substrate with a high dopant concentration. A thin and at the same time highly doped n-doped layer can be realized in this way.

In one development, the semiconductor chip is an InGaN LED. The semiconductor chip is preferably a thin-film chip. Within the scope of the application, a thin-film chip is a semiconductor chip during the production of which the growth substrate on which the semiconductor layer stack was epitaxially grown is preferably completely detached. The semiconductor layer stack of the semiconductor chip can be applied to a carrier substrate, for example. A silicon-containing carrier substrate is preferably provided as the carrier substrate, in particular when the growth substrate is already a silicon-containing substrate.

In one development, the semiconductor chip has electrical contacting on one side. The n- and p-doped layers of the semiconductor layer stack can thus be electrically contacted on one side, that is to say for example only from a rear side of the semiconductor layer stack. Alternatively, the electrical contact can be made from a front side of the semiconductor layer stack. For electrical contacting, a first and second electrical connection layer are arranged on one side of the semiconductor layer stack, which are each provided for electrical contacting of the layer stack of one conductivity type. In this case, the first and second electrical connection layers are electrically insulated from one another, for example by means of an electrically insulating separating layer.

The one-sided contacting technology of the chip enables a low-impedance contact. Due to the one-sided arrangement of the contacts, the full functionality of the epitaxial layers of the semiconductor layer stack, in particular the active layer, can advantageously be ensured.

mit D der Schichtdicke der n-dotierten Schicht, DIS_Edge der mittleren Versetzungsdichte mit Stufenanteil im Bereich der n-dotierten Schicht in cm^-2 und mit einem Wert oberhalb von 1 x 10⁸ cm^-2, N der Dotierstoffkonzentration in der n-dotierten Schicht in cm^-3.The dopant concentration of the n-dopant in the n-doped layer satisfies the following condition: $$D\times DI{S}_{E\mathrm{i.e}Ge}\times N\ge 5\times {10}^{23}c{m}^{-4},$$

with D the layer thickness of the n-doped layer, DIS _Edge the mean dislocation density with step content in the area of the n-doped layer in cm ^-2 and with a value above 1 x 10 ⁸ cm ^-2 , N the dopant concentration in the n-doped layer layer in cm ^-3 .

The above condition can be seen as a criterion for the sensible use of an unusual and claimed dopant in highly doped group III nitride layers in comparison to the silicon normally used. These layers can be heteroepitaxial on sapphire, SiC or silicon, but also homoepitaxial on group III nitride substrates that ent have a correspondingly high dislocation density of, for example, higher than 5×10 ⁶ cm ^-2 .

• - Bereitstellen eines Aufwachssubstrats,
• - epitaktisches Aufwachsen eines Halbleiterschichtenstapels, der auf einem Materialsystem der Gruppe-III-Nitride basiert und zumindest eine n-dotierte Schicht aufweist, wobei als n-Dotierstoff ein schwererer Dotand als Silizium aus der IV. Hauptgruppe oder ein Dotand aus der VI. Hauptgruppe der chemischen Elemente verwendet wird.

A method for manufacturing a semiconductor chip includes the following method steps:

• - providing a growth substrate,
• - Epitaxial growth of a semiconductor layer stack, which is based on a material system of group III nitrides and has at least one n-doped layer, the n-dopant being a heavier dopant than silicon from group IV. Main group or a dopant from group VI. Main group of chemical elements is used.

Such a method enables GaN layers to be grown on, for example, a silicon substrate with a high degree of n-doping, in which the strain is essentially unaffected by the doping. In addition, it is possible to deposit the n-doped layer or layers of the semiconductor chip in a correspondingly thin manner with improved n-conductivity. In this way, a thin and at the same time highly doped n-layer can be produced. In this case, a silicon-containing substrate can be used as the growth substrate, which is advantageously inexpensive. Furthermore, with a method of this type, with the additional use of a SiN masking layer for dislocation reduction, the subsequent coalescence is advantageously not adversely affected.

In one development, the growth substrate is an SOI substrate (“silicon on insulator” substrate). Alternatively, the growth substrate can be a sapphire or SiC substrate.

In a further development, a germanium-hydrogen compound, an organic germanium compound, tert-butyl german, tert-butyl tin, tert-butyl lead, an organometallic compound of the R ₄ -Me type with R being an organic radical in the gas phase epitaxy or a compound from the VI. Main group used with hydrogen or an organic radical.

Doping with germanium is preferable to the other elements, since the available precursors are easy to use and the vapor pressure of the dopant above the layer can be easily controlled at the process temperatures above 1000 °C that often prevail in group III nitride epitaxy is. With the exception of oxygen, the other precursors are not so easy to handle in the process. However, oxygen in turn can be undesirable in the epitaxy process, since it is considered the main contaminant and, at least in metal-organic vapor phase epitaxy, can also trigger undesirable reactions with the metal-organic compounds and therefore represents a potential safety risk in hydrogen-rich processes.

The features mentioned in connection with the semiconductor chip also apply to the method and vice versa.

• 1, 2A, 2B jeweils einen schematischen Querschnitt eines Ausführungsbeispiels eines erfindungsgemäßen Halbleiterchips,
• 2C ein Diagramm, bei dem die Verspannung gegen die Herstellungszeit aufgetragen ist, und
• 3 ein Flussdiagramm betreffend ein erfindungsgemäßes Herstellungsverfahren.

Further advantages and advantageous developments of the invention result from the following in conjunction with 1 until 3 described embodiments. Show it:

• 1 , 2A , 2 B each a schematic cross section of an embodiment of a semiconductor chip according to the invention,
• 2C a graph of stress versus manufacturing time, and
• 3 a flowchart relating to a manufacturing method according to the invention.

In the figures, components that are the same or have the same effect can each be provided with the same reference symbols. The components shown and their proportions to one another are not to be regarded as true to scale. Rather, individual parts, such as for example layers, structures, components and areas, can be shown in an exaggerated thickness or with large dimensions for better representation and/or for better understanding.

1 shows an embodiment of a semiconductor chip 10 in cross section. The semiconductor chip 10 has a growth substrate 1, the z. B. sapphire, SiC or silicon. The growth substrate can also be an SOI substrate (“silicon on insulator” substrate) or a group III nitride substrate.

The individual layers 2a, 2b, 2c of the semiconductor layer stack 2 are grown on the silicon-containing growth substrate 1. FIG. The semiconductor layer stack 2 is based on a group III nitride material system. The semiconductor layer stack 2 is preferably based on the InGaN material system. The semiconductor layer stack 2 has an active layer 2a. The active layer 2a is suitable for generating electromagnetic radiation when the semiconductor chip 10 is in operation. The semiconductor chip 10 is preferably an LED (“Light Emitting Diode”).

The active layer 2a of the semiconductor layer stack 2 is arranged between an n-doped layer 2b and a p-doped layer 2c. The n-doped layer is in the embodiment 1 applied directly to the growth substrate 1. Alternatively, the n-doped layer by means a masking layer and coalescing layer may be applied to the growth substrate 1 (not shown).

The n-doped layer 2b has a heavier dopant than silicon from the IV. Main group or a dopant from the VI. main group of chemical elements. Ge, Sn and Pb are therefore used as n-dopants of main group IV. As a student of the VI. Main group is used, for example, O, S, Se or Te.

The dopant concentration of the n-dopant in the n-doped layer 2b is preferably greater than 5×10 ¹⁸ 1/cm ³ . Due to the selection of the dopant, the tensile strain of the semiconductor layer material that conventionally occurs during the cooling process or that occurs as a result of the dopant concentration can advantageously be avoided. Layers with such a high level of doping are particularly advantageous for high transverse conductivity and optimized contact resistances. It is also possible to deposit the n-doped layer 2b correspondingly thin with improved n-conductivity or to make the n-contact areas correspondingly small with improved contact resistances.

The n-doped layer 2b and the p-doped layer 2c of the semiconductor layer stack 2 can be composed of a layer sequence. In this case, the semiconductor layer stack 2 has a plurality of n-doped layers 2b, which are arranged between the growth substrate 1 and the active layer 2a. In this case, a plurality of p-doped layers can be arranged on that side of the active layer 2a which is remote from the growth substrate 1 .

wobei D die Schichtdicke der n-dotierten Schicht 2a oder der Schichtenfolge der n-dotierten Schicht ist, DIS_Edge die mittlere Versetzungsdichte mit Stufenanteil im Bereich der n-dotierten Schicht 2b oder der n-dotierten Schichten in cm^-2 mit einem Wert oberhalb von 1 x 10⁸ cm^-2, und N die Dotierstoffkonzentration in der n-dotierten Schicht 2b oder den n-dotierten Schichten in cm^-3 ist.The dopant concentration of the n-dopant in the n-doped layer or the n-doped layers 2b preferably satisfies the following condition: $$D\times DI{S}_{E\mathrm{i.e}Ge}\times N\ge 5\times {10}^{23}{\text{cm}}^{-4},$$

where D is the layer thickness of the n-doped layer 2a or the layer sequence of the n-doped layer, DIS _Edge is the average dislocation density with step content in the area of the n-doped layer 2b or the n-doped layers in cm ^-2 with a value above 1 x 10 ⁸ cm ^-2 , and N is the dopant concentration in the n-doped layer 2b or the n-doped layers in cm ^-3 .

Due to the selection of the n-dopant, tensile strains in the semiconductor chip can advantageously be avoided, while at the same time a thick and highly doped group III nitride layer can be realized on silicon, sapphire or SiC. With such a heavy n-dopant, the complex reduction of the dislocations, which is not always necessary due to the requirements and which decisively trigger the tensile stress during doping, can thus be avoided, with highly doped layers being able to be produced.

The semiconductor chip 10 advantageously has electrical contacting on one side. This means that a first and second electrical connection pad are arranged on the same side of the semiconductor chip 10 and are electrically isolated from one another, for example by means of an insulating separating layer.

By using an n-dopant that is heavier than silicon, a large-area, cost-effective and defect-reduced epitaxy and semiconductor chip processing on silicon substrates can be made possible. In particular, thick n-doped layers can be produced which have reduced mechanical damage such as cracking. An improved method and a semiconductor chip with improved properties can thus be achieved.

In 2A another exemplary embodiment of a semiconductor chip is shown in cross section. The semiconductor chip 10 of 2A differs from the semiconductor chip 1 by additional layers 3, 4, which are arranged between the growth substrate and the semiconductor layer stack 2. In particular, a buffer layer 3 is applied to the growth substrate 1 . Such buffer layers 3 are used in particular for growing onto substrates 1 containing silicon. An aluminum-containing intermediate layer 4 is arranged on the buffer layer 3, on which the layers of the semiconductor layer stack 2 have grown epitaxially. The aluminum-containing layer is, for example, an AlN seed layer. Such a seed layer is also used for growth on silicon-containing growth substrates.

Otherwise, the embodiment of the 2A with the embodiment of 1 match.

In 2 B another exemplary embodiment of a semiconductor chip is shown in cross section. The semiconductor chip 10 of 2 B differs from the semiconductor chip 1 by additional layers 5, 6, 7, which are arranged between the growth substrate and the semiconductor layer stack 2. In particular, a first group III nitride layer 5 is applied to the growth substrate 1 . A partial SiN masking layer 6 is arranged on this. Subsequently, the second Group-III nitride layer 7 is arranged, characterized as having a lower dislocation density than the first group III nitride layer 5. The layers of the semiconductor layer stack 2 are then grown epitaxially.

Otherwise, the embodiment of the 2 B with the embodiment of 1 match.

In 2C a diagram is shown in which the stress in the manufacturing process is plotted against the time of the manufacturing process. The dashed line shows the production of a semiconductor chip with an n-dopant silicon, the solid line shows a semiconductor chip with an n-dopant Ge.

The method relates, for example, to the production of a semiconductor chip in accordance with the exemplary embodiment of FIG 2A .

The diagram of 2C shows the curvature measurement during the growth of a silicon-doped GaN layer (dashed line) and a Ge-doped GaN layer (solid line) on a silicon substrate. After the growth of a buffer layer 101, compression is generated by an Al-containing intermediate layer in the subsequent GaN layer 102, which can be seen in particular from the change in curvature to negative values. During the doping 103, the curvature of the Ge doping is practically unchanged. The slight decrease shown in the chart is common in the growth process. In the case of silicon doping, the curvature decreases, indicating a strained growth. The silicon-doped layer can therefore be severely cracked after cooling, while the Ge-doped layer advantageously remains crack-free despite high n-doping.
As shown in the diagram, the semiconductor layers with silicon in the later manufacturing process, in particular at around 60 minutes and more, exhibit less stress than with doping with German and consequently higher tensile stress after the cooling process (80 min). A dopant such as German can thus be used to reduce mechanical damage to the layers, which can occur as a result of the stresses that occur.

• Im Zeitintervall 101 wird in einer Wachstumskammer, beispielsweise einem MOVPE-Reaktor, ein nasschemisch gereinigtes und deoxidiertes Siliziumsubstrat eingelegt und auf zirka 730 °C erhitzt. Anschließend folgt die Zuführung eines Aluminiumprecursors und von Ammoniak. Nach dem Wachstum von zirka 25 nm AlN wird die Probe auf 1050 °C unter weiterem Ammoniakfluss erhitzt und durch Zuführen eines Galliumprecursors das Wachstum einer GaN-Schicht des Halbleiterschichtenstapels gestartet. Als Resultat wird eine 0,7 µm dicke GaN-Schicht hergestellt, die auf den oberen 500 nm eine Elektronenkonzentration von 5 × 10¹⁸ cm^-3 aufweist. Aufgrund des Wachstumsprozesses liegt die Stufenversetzungsdichte typischerweise oberhalb von 2 × 10⁸ cm^-2. Unter Verwendung der Bedingung D × DIS_EDGE × N ≥ 5 × 10²³ cm^-4 ergibt sich ein Wert von 5 × 10²⁶. Hierzu ist Germanium als Dotierstoff verdünnt in Wasserstoff vorteilhaft geeignet. Durch den Einsatz dieses Dotanden kann eine Rissbildung in der GaN-Schicht auf dem Siliziumaufwachssubstrat vermieden werden. Die Verdünnung von German in Wasserstoff fällt in der Regel geringer aus als für Silan in Wasserstoff, da der Einbau im Vergleich ineffizienter ist und im Gegensatz zur Si-Dotierung mehr dampfdruckgetrieben ist. Beispielsweise ist eine Verdünnung von 1 %o bis 1 % GeH₄ in H₂ möglich.

The manufacturing process to the diagram of 2C may include the following process steps:

• In time interval 101, a wet-chemically cleaned and deoxidized silicon substrate is placed in a growth chamber, for example a MOVPE reactor, and heated to approximately 730°C. This is followed by the addition of an aluminum precursor and ammonia. After the growth of about 25 nm AlN, the sample is heated to 1050 °C with a further flow of ammonia and the growth of a GaN layer of the semiconductor layer stack is started by adding a gallium precursor. As a result, a 0.7 µm thick GaN layer is produced, which has an electron concentration of 5 × 10 ¹⁸ cm ^-3 on the top 500 nm. Due to the growth process, the step dislocation density is typically above 2 × 10 ⁸ cm ^-2 . Using the condition D × DIS _EDGE × N ≥ 5 × 10 ²³ cm ^-4 gives a value of 5 × 10 ²⁶ . For this purpose, germanium is advantageously suitable as a dopant diluted in hydrogen. By using this dopant, crack formation in the GaN layer on the silicon growth substrate can be avoided. The dilution of German in hydrogen is generally lower than for silane in hydrogen, since the incorporation is comparatively less efficient and, in contrast to Si doping, is more driven by vapor pressure. For example, a dilution of 1% to 1% GeH ₄ in H ₂ is possible.

• Auf eine AIN-Keimschicht wird hochdotiert und direkt eine GaN-Schicht aufgewachsen. Durch eine hohe Versetzungsdichte von größer als 5 × 10⁹ cm^-2 am Anfang des heteroepitaktischen Wachstums kann ohne die Erzeugung einer nennenswerten Verspannung eine hohe Ladungsträgerkonzentration erzielt werden und somit ein niedriger Übergangswiderstand zum Siliziumsubstrat ermöglicht werden. Um bei der Dotierung Elektronenkonzentration von 5 x 10¹⁸ cm^-3 zu realisieren, liegt auf den ersten 100 nm mit Stufenversetzungsdichten von größer als 5 × 10⁹ cm^-2 der nach obiger Bedingung errechnete Wert bei größer als 2,5 × 10²⁷ cm^-4. Aufgrund eines Dotanden, der schwerer ist als Silizium, kann die Verspannung mit Vorteil auf ein geringeres Maß reduziert werden.

An alternative manufacturing method to the diagram of 2C can be done as follows:

• An AlN seed layer is highly doped and a GaN layer is grown directly. A high dislocation density of greater than 5×10 ⁹ cm ^-2 at the beginning of the heteroepitaxial growth can achieve a high charge carrier concentration without generating any appreciable strain, and thus a low contact resistance to the silicon substrate can be made possible. In order to achieve an electron concentration of 5×10 ¹⁸ cm ^-3 during doping, the value calculated according to the above condition is greater than 2.5×10 ²⁷ cm on the first 100 nm with step dislocation densities of greater than 5×10 ⁹ cm ^{-2 -4} . Due to a dopant that is heavier than silicon, the strain can advantageously be reduced to a lower level.

• Hier tritt für mit Si hochdotierten, leitfähigen Substraten meist eine starke inhomogene Krümmung auf, welche durch späteres Abschleifen der zum Aufwachssubstrat zeigenden Schicht reduziert wird. Dazu kommt die Schwierigkeit, dass durch die Dotierung und die damit verbundene starke Zugverspannung es während des Wachstums zur Rissbildung kommen kann. Weiterhin wird eine niedrige Versetzungsdichte meist durch ein forciertes 3d Wachstum, entweder nach dem ELOG Verfahren, mittels in-situ abgeschiedener Maskenschichten, wobei diese meist aus SiN bestehen, oder durch eine geringe Bekeimungsdichte, die zu einem 3d-Wachstum führt, erzielt. Die anschließende Koaleszenz wird dabei durch die Dotierung mit Si durch die parasitäre SiN Schichtbildung in unerwünschter Weise beeinflusst. Wird nun anstatt mit Silizium mit einem erfindungsgemäßen Dotanden dotiert, kann die entstehende Zugverspannung am Anfang des Wachstums reduziert werden und bei 3-dimensinonalem Inselwachstum dieses unbeeinflusster und damit einfacher als n-dotierte Schicht realisiert werden. Dies vermeidet in der Folge Risse während des Wachstums und sorgt für eine geringere Substratkrümmung des vom Wachstumssubstrat abgelösten Pseudosubstrats nach dem Wachstum.

Another application is the growth of thick n-doped group III nitride layers, usually using HVPE, on a carrier substrate for the production of pseudo-substrates, which, detached from the carrier substrate, serve as high-quality substrates for hetero- and homoepitaxy:

• Here, for conductive substrates highly doped with Si, there is usually a strong inhomogeneous curvature, which is reduced by later grinding down the layer pointing to the growth substrate. In addition, there is the difficulty that the doping and the associated strong tensile stress lead to crack formation during growth can come. Furthermore, a low dislocation density is usually achieved through forced 3D growth, either using the ELOG process, using in-situ deposited mask layers, which usually consist of SiN, or through a low seeding density, which leads to 3D growth. The subsequent coalescence is influenced in an undesired manner by the doping with Si through the parasitic SiN layer formation. If a dopant according to the invention is now doped instead of silicon, the resulting tensile stress at the beginning of the growth can be reduced and, in the case of 3-dimensional island growth, this can be realized in a more unaffected and thus simpler way than an n-doped layer. This subsequently avoids cracks during growth and ensures less substrate curvature of the pseudo-substrate detached from the growth substrate after growth.

In 3 a flowchart is shown which shows method steps for producing a semiconductor chip according to the invention. In method step 301, a silicon substrate is provided. A buffer layer is grown on the silicon substrate. Subsequently, in method step 302, an Al-containing intermediate layer is applied to the buffer layer. This is done, for example, by supplying an aluminum precursor and ammonia.

Subsequently, in method step 303, the layers of the semiconductor layer stack are applied to the aluminum-containing intermediate layer. Compression is generated in the subsequent layer of the semiconductor layer stack by the aluminum-containing intermediate layer.

In method step 304, the layer or layers of the semiconductor layer stack are then doped. Subsequent to the doping process, the semiconductor chip produced in this way is cooled.

Claims (9)

Semiconductor chip (10) with a semiconductor layer stack (2) which is based on a group III nitride material system and has at least one n-doped layer (2b), Sn or Pb being used as the n-dopant, and the dopant concentration of the n-dopant in the n-doped layer (2b) satisfies the following condition: $$D\times Di{s}_{E\mathrm{i.e}Ge}\times N\ge 5\times {10}^{23}{\text{cm}}^{-4},$$

with D the layer thickness of the n-doped layer (2b), DiS _Edge the average dislocation density with step content in the region of the n-doped layer (2b) in cm ^-2 with a value above 1 × 10 ⁸ cm ^-2 and N the dopant concentration in the n-doped layer (2b) in cm ^-3 . semiconductor chip claim 1 , where the n-dopant is Pb. Semiconductor chip according to one of the preceding claims, wherein the dopant concentration of the n-dopant in the n-doped layer (2b) is greater than 10 ¹⁹ 1/cm ³ . Semiconductor chip according to one of the preceding claims, wherein the semiconductor chip (10) is an optoelectronic chip which has an active layer (2a) provided for generating radiation between the n-doped layer (2b) and a p-doped layer (2c). Semiconductor chip according to one of the preceding claims, wherein the semiconductor chip (10) is an InGaN LED. Semiconductor chip according to one of the preceding claims, wherein the semiconductor chip (10) comprises a silicon-containing carrier substrate. Semiconductor chip according to one of the preceding claims, wherein the semiconductor chip (10) has electrical contacting on one side. Method for producing a semiconductor chip (10) according to one of the preceding claims, having the following method steps: - Providing a silicon-containing growth substrate (1), - Epitaxial growth of the semiconductor layer stack (2), which is based on the material system of group III nitrides and has at least the n-doped layer (2b), Sn or Pb being used as the n-dopant. procedure after claim 8 , where tert-butyl tin or tert-butyl lead is used in the growth.

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