DE10061770B4 - Zugriffsregelung für Steuerchipsätzen bei Bustransaktion - Google Patents

Zugriffsregelung für Steuerchipsätzen bei Bustransaktion Download PDF

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Publication number
DE10061770B4
DE10061770B4 DE10061770A DE10061770A DE10061770B4 DE 10061770 B4 DE10061770 B4 DE 10061770B4 DE 10061770 A DE10061770 A DE 10061770A DE 10061770 A DE10061770 A DE 10061770A DE 10061770 B4 DE10061770 B4 DE 10061770B4
Authority
DE
Germany
Prior art keywords
bus
control chip
data
clock
signal line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE10061770A
Other languages
German (de)
English (en)
Other versions
DE10061770A1 (de
Inventor
Jiin Lai
Chau-Chad Tsai
Sheng-Chang Peng
Chi-Che Tsai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Via Technologies Inc
Original Assignee
Via Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Via Technologies Inc filed Critical Via Technologies Inc
Publication of DE10061770A1 publication Critical patent/DE10061770A1/de
Application granted granted Critical
Publication of DE10061770B4 publication Critical patent/DE10061770B4/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)
DE10061770A 1999-12-15 2000-12-12 Zugriffsregelung für Steuerchipsätzen bei Bustransaktion Expired - Lifetime DE10061770B4 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW088121973 1999-12-15
TW088121973A TW468112B (en) 1999-12-15 1999-12-15 Arbitrating method of bus between control chipsets

Publications (2)

Publication Number Publication Date
DE10061770A1 DE10061770A1 (de) 2001-08-09
DE10061770B4 true DE10061770B4 (de) 2007-11-08

Family

ID=21643386

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10061770A Expired - Lifetime DE10061770B4 (de) 1999-12-15 2000-12-12 Zugriffsregelung für Steuerchipsätzen bei Bustransaktion

Country Status (4)

Country Link
US (1) US6721833B2 (enExample)
JP (1) JP4583590B2 (enExample)
DE (1) DE10061770B4 (enExample)
TW (1) TW468112B (enExample)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6959372B1 (en) * 2002-02-19 2005-10-25 Cogent Chipware Inc. Processor cluster architecture and associated parallel processing methods
US7085866B1 (en) * 2002-02-19 2006-08-01 Hobson Richard F Hierarchical bus structure and memory access protocol for multiprocessor systems
JP2005250671A (ja) * 2004-03-02 2005-09-15 Sony Corp 通信システム、通信装置、通信方法およびプログラム
CN100336045C (zh) * 2004-11-19 2007-09-05 威盛电子股份有限公司 多功能芯片组及相关方法
US7174403B2 (en) * 2005-02-24 2007-02-06 Qualcomm Incorporated Plural bus arbitrations per cycle via higher-frequency arbiter
US20060277444A1 (en) * 2005-06-03 2006-12-07 Nicholas Holian Recordation of error information
US7467245B2 (en) * 2005-07-22 2008-12-16 Cisco Technology, Inc. PCI arbiter
US7757031B2 (en) * 2005-10-24 2010-07-13 Via Technologies, Inc. Data transmission coordinating method and system
US7945719B2 (en) 2006-09-20 2011-05-17 Intel Corporation Controller link for manageability engine
CN104978302B (zh) * 2015-06-24 2018-02-23 山东超越数控电子股份有限公司 一种基于tcm芯片的智能安全usb接口控制方法
TWI637269B (zh) * 2017-12-26 2018-10-01 奇景光電股份有限公司 電子裝置及其操作方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998036360A1 (en) * 1997-02-18 1998-08-20 Advanced Micro Devices, Inc. System for partitioning pc chipset functions into logic and port integrated circuits
US5983302A (en) * 1995-05-08 1999-11-09 Apple Comptuer, Inc. Method and apparatus for arbitration and access to a shared bus

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05324544A (ja) * 1992-05-15 1993-12-07 Hitachi Ltd バス制御方法
TW242183B (en) * 1993-11-26 1995-03-01 United Microelectronics Corp Chip set architecture for personal computer
TW400483B (en) * 1994-03-01 2000-08-01 Intel Corp High performance symmetric arbitration protocol with support for I/O requirements
US6073199A (en) * 1997-10-06 2000-06-06 Cisco Technology, Inc. History-based bus arbitration with hidden re-arbitration during wait cycles
US6195722B1 (en) * 1998-01-26 2001-02-27 Intel Corporation Method and apparatus for deferring transactions on a host bus having a third party agent
US6202112B1 (en) * 1998-12-03 2001-03-13 Intel Corporation Arbitration methods to avoid deadlock and livelock when performing transactions across a bridge
US6223244B1 (en) * 1998-12-10 2001-04-24 International Business Machines Corporation Method for assuring device access to a bus having a fixed priority arbitration scheme
US6253270B1 (en) * 1998-12-30 2001-06-26 Intel Corporation Method and apparatus for arbitrating ownership of an interface between hub agents
US6347351B1 (en) * 1999-11-03 2002-02-12 Intel Corporation Method and apparatus for supporting multi-clock propagation in a computer system having a point to point half duplex interconnect

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5983302A (en) * 1995-05-08 1999-11-09 Apple Comptuer, Inc. Method and apparatus for arbitration and access to a shared bus
WO1998036360A1 (en) * 1997-02-18 1998-08-20 Advanced Micro Devices, Inc. System for partitioning pc chipset functions into logic and port integrated circuits

Also Published As

Publication number Publication date
US6721833B2 (en) 2004-04-13
DE10061770A1 (de) 2001-08-09
US20010004749A1 (en) 2001-06-21
JP4583590B2 (ja) 2010-11-17
TW468112B (en) 2001-12-11
JP2001216254A (ja) 2001-08-10

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8110 Request for examination paragraph 44
8364 No opposition during term of opposition
R071 Expiry of right