DE10056272A1 - Halbleitervorrichtung und Verfahren zu deren Herstellung - Google Patents

Halbleitervorrichtung und Verfahren zu deren Herstellung

Info

Publication number
DE10056272A1
DE10056272A1 DE10056272A DE10056272A DE10056272A1 DE 10056272 A1 DE10056272 A1 DE 10056272A1 DE 10056272 A DE10056272 A DE 10056272A DE 10056272 A DE10056272 A DE 10056272A DE 10056272 A1 DE10056272 A1 DE 10056272A1
Authority
DE
Germany
Prior art keywords
insulating film
side wall
gate
film
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE10056272A
Other languages
English (en)
Inventor
Yoshinori Okumara
Tomohiro Yamashita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of DE10056272A1 publication Critical patent/DE10056272A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Semiconductor Memories (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Das Eindringen eines Gate-Isolierfilms und das Steigen des Flächenwiderstands in einer Gate-Elektrode in CMOS-Logikvorrichtungen und DRAMs wird verhindert, wobei die steigende Fläche eines Logikgatter-Anordnungsteils in den CMOS-Logikvorrichtungen ebenfalls verhindert wird. Auf einem durch die oberen Hauptoberflächen von hochschmelzenden Metallsilicidfilmen (23b, 23c) und durch die obere Stirnseite eines Seitenwand-Nitridfilms (171) ausgebildeten ebenen Gebiet sind die Nitridsperrfilme (25b, 25c) vorgesehen. Wenn die elektrische Verbindung zwischen einer oberen Verdrahtung und den Source/Drain-Gebieten (18, 20) durch Durchgangskontaktlöcher hergestellt wird, wird somit selbst dann, wenn die Kontaktloch-Bildungsstelle verschoben ist, vermieden, daß die Polycid-Gates (8b, 8c) mit den Kontaktlöchern in direkten Eingriff gelangen. Somit kann der Ausrichtungsgrenzwert zwischen den Kontaktlöchern und der Gate-Elektrode gegenüber der Ausrichtungsgenauigkeit verringert werden, was somit ein Verringern der Fläche des Gate-Anordnungsteils ermöglicht.
DE10056272A 2000-03-30 2000-11-14 Halbleitervorrichtung und Verfahren zu deren Herstellung Withdrawn DE10056272A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000093260A JP2001284467A (ja) 2000-03-30 2000-03-30 半導体装置およびその製造方法

Publications (1)

Publication Number Publication Date
DE10056272A1 true DE10056272A1 (de) 2001-10-11

Family

ID=18608471

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10056272A Withdrawn DE10056272A1 (de) 2000-03-30 2000-11-14 Halbleitervorrichtung und Verfahren zu deren Herstellung

Country Status (4)

Country Link
JP (1) JP2001284467A (de)
KR (1) KR100385763B1 (de)
DE (1) DE10056272A1 (de)
TW (1) TW469565B (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3096357A1 (de) * 2009-12-30 2016-11-23 Intel Corporation Selbstausrichtende kontakte

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100437011B1 (ko) * 2002-08-27 2004-06-23 삼성전자주식회사 금속실리사이드막을 갖는 반도체 소자의 형성방법
JP4602138B2 (ja) * 2005-03-30 2010-12-22 富士通セミコンダクター株式会社 半導体装置の製造方法
JP2007157744A (ja) * 2005-11-30 2007-06-21 Toshiba Corp 半導体装置および半導体装置の製造方法
JP4322897B2 (ja) 2006-07-07 2009-09-02 エルピーダメモリ株式会社 半導体装置の製造方法
DE102007041207B4 (de) * 2007-08-31 2015-05-21 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg CMOS-Bauelement mit Gateisolationsschichten mit unterschiedlicher Art und Dicke und Verfahren zur Herstellung
JP5374947B2 (ja) * 2008-07-24 2013-12-25 ソニー株式会社 半導体装置およびその製造方法
KR101615654B1 (ko) * 2010-05-14 2016-05-12 삼성전자주식회사 반도체 소자의 형성방법
CN109417022B (zh) * 2016-06-28 2023-08-11 应用材料公司 用于3d nand存储器器件的基于cvd的氧化物-金属多结构

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3096357A1 (de) * 2009-12-30 2016-11-23 Intel Corporation Selbstausrichtende kontakte
US10629483B2 (en) 2009-12-30 2020-04-21 Intel Corporation Self-aligned contacts
US10930557B2 (en) 2009-12-30 2021-02-23 Intel Corporation Self-aligned contacts
US11600524B2 (en) 2009-12-30 2023-03-07 Intel Corporation Self-aligned contacts
US11887891B2 (en) 2009-12-30 2024-01-30 Intel Corporation Self-aligned contacts

Also Published As

Publication number Publication date
KR20010096509A (ko) 2001-11-07
TW469565B (en) 2001-12-21
JP2001284467A (ja) 2001-10-12
KR100385763B1 (ko) 2003-05-28

Similar Documents

Publication Publication Date Title
WO2004038808A3 (en) Double and triple gate mosfet devices and methods for making same
EP0964448A3 (de) DRAM-Zelle mit vertikalem Transistor und Verfahren zur Herstellung derselben
WO2003083947A3 (en) Folded bit line dram with vertical ultra thin body transistors
WO2002048668A3 (en) Integrated cmos capacitive pressure sensor
WO2003041185A3 (en) Organic thin film transistor with polymeric interface
WO2001050535A3 (en) Field effect transistor structure with partially isolated source/drain junctions and methods of making same
EP1017095A3 (de) DRAM-Zelle mit Grabenkondensator
WO2002061806A3 (en) Dram cell having a capacitor structure fabricated partially in a cavity and method for operating same
SG111054A1 (en) Self-aligned silicide process for silicon sidewall source and drain contacts and structure formed thereby
EP0389762A3 (de) Halbleiterspeicheranordnung mit einem ferroelektrischen Material
EP1039533A3 (de) Hochleistungs-DRAM und dessen Herstellungsverfahren
WO2002080227A3 (en) Memory address and decode circuits with ultra thin body transistors
EP0514547A4 (de) Halbleiterbauteil, dasselbe verwendender halbleiterspeicher, integrierte cmos-halbleiterschaltung und verfahren zur herstellung des halbleiterbauteils.
WO2003103032A3 (en) A method for making a semiconductor device having a high-k gate dielectric
CA2006745A1 (en) Cross-point lightly-doped drain-source trench transistor and fabrication process therefor
WO2004097898A3 (en) Fuse and method for forming
WO2003041127A3 (en) Process for forming metallized contacts to periphery transistors
EP1207552A3 (de) Nichtflüchtige Halbleiterspeicherbauelement und dessen Herstellungsverfahren
EP1211729A3 (de) Komplementäre Transistoren mit jeweiligen Gattern aus Metall und entsprechendem Metallsilizid
EP1227513A3 (de) Verfahren zur Herstellung von einem Gatter-Dielektrikum mit veränderlicher Dielektrizitätskonstante
DE10056272A1 (de) Halbleitervorrichtung und Verfahren zu deren Herstellung
EP1246258A4 (de) Halbleiteranordnung, ihre herstellungsmethode und informationsverarbeitungsanordnung
WO2003019643A1 (fr) Dispositif semi-conducteur comportant un film isolant presentant une permittivite elevee et son procede de production
AU2002243538A1 (en) Reduced aspect ratio digit line contact process flow used during the formation of a semiconductor dram device
EP1152470A3 (de) Halbleiterbauelement mit LDD-Struktur und dessen Herstellungsverfahren

Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8139 Disposal/non-payment of the annual fee