DD290789A7 - METHOD AND CIRCUIT ARRANGEMENT FOR THE APPROACHED CORRELATION AND SIGNAL PROCESSING BY RISC PROCESSOR - Google Patents

Abstract

The invention relates to a method and a circuit arrangement for clocked correlation and signal processing by means of a RISC processor and can be used for synchronizing - receivers in digital frame networks, mobile networks and equivalent devices which operate in time division multiplexing. The aim of the invention is to improve the quality of reception of modulated data signals in said devices and to propose a circuit arrangement which is characterized by a good Integrationsfaehigkeit. The essence of the inventive solution is that first the binary cross-correlation of the received signal with one or more known synchronization bit patterns is calculated in authenticity. The correlation function is then filtered and the bit and word clocks are derived. The serial data is formed into a matrix which is output via a DMA channel. For monitoring the radio channel, the phase of the correlation pulse and its length is monitored. To implement the method is a circuit arrangement. Fig. 1 {RISC processor; Correlation processing; Signal processing; Synchronization; Receiver; Frame network; Digital network; Mobile network; Time division multiplexing; bit pattern; Clock processing; DMA Prozesz; Real Time}

Description

For this 3 pages drawings

Field of application of the invention

The invention relates to a method and a circuit arrangement for clocked correlation and signal processing by means of a RISC processor and can be used for synchronizing receivers in digital frame networks, mobile radio networks and equivalent devices which work in the time-division multiplex method.

Characteristic of the known state of the art

It is generally known to apply clocked correlation and signal processing methods or to use circuit arrangements to realize synchronization in a digital or analog manner. In digital correlation methods, the received signal is compared with a digital pattern and, if coincident, a correlation signal is formed. The correlation signal can be used for certain types of modulation, eg. PSK or QAM, be complex. If the magnitude of the correlation signal is greater than a threshold, a digital signal whose temporal length is evaluated is derived in real time. The time center of this pulse indicates the optimum position of the bit sample with the accuracy of a system-specific constant and is used to synchronize a bit clock generator.

The known technical solutions differ essentially by the connection for digitizing the analog input information as well as the manner of deriving the bit clock. In general, a parallel comparison of delayed samples with a sync word is made.

Furthermore, it is known from DE-OS 3032296 to give the analog input signal to a runtime arrangement with taps having a time offset corresponding to the Bittokt. From the taps the respective output voltages are multiplied by constants and finally added and compared with a threshold analog. The correlation signal thus obtained is delayed by exactly one bit clock. The instantaneous correlation signal starts a up / down counter in the backward counting mode from a defined output state and interrupts the counting process after the end of the correlation signal. The delayed correlation pulse ticks the same counter in the count-ahead mode, but with the double-ended clock frequency. When the defined initial state is reached, the bit clock generator can be synchronized. The device is controlled by a microcomputer and allows the control of the bit clock and an accumulation of the phase information.

According to DE-OS 3507029, the calculation of the correlation is performed digitally. For this purpose, each bit or dibit of the input signal is divided into a number of intervals and sampled and stored in one or more shift registers. Suitable taps of these shift registers are compared in parallel with a stored synchronizing word, and if they match, a "1" is shifted into a "synchronous shift register". The mean sampling time is obtained by a method equivalent to DE-OS 3032296. Due to the limited length of the shift registers, a receive frame is formed which a priori indicates the approximate location of the synchronization word.

All these methods have the disadvantages described below:

When synchronizing to long Synchronworto that are advantageous because of their higher interference, complicates the cost of analog delay elements or large FIFO memory integration into cost-effective custom circuits.

The use of apriori information on the position of the synchronizing word presupposes an upstream analysis of the input signal, which significantly increases the transient response, in particular in the case of dispersive in operating networks, and negatively influences the synchronization statistics.

Arrangements for formatting serial data streams in connection with synchronization devices are not described.

Object of the invention

The aim of the invention is to improve the reception quality of modulated data signals within clocked Korrolations- and signal processing units and to propose a circuit arrangement which is characterized by a good integration ability.

Explanation of the essence of the invention

Dor invention has for its object to provide a solution for correlation and signal processing, which calculates the cross-correlation of the received signal with one or more known, the synchronization serving bit pattern in real time and derives therefrom the bit and word clock.

According to the invention, this object is achieved by an ancestor sound and a circuit arrangement by means of a RISC processor, which performs the following steps in an ordered order in the system clock SCLK:

a) Taking over the state of the bit counter as a base address in the address computer with the signal COPY, assumption dos Korrolationsergebnisses of the correlator in the transversal filter and subsequent initialization of the correlator by the signal INIT. ₁

b) writing the current sample to the RAM at the address determined by the phase counter and bit counter,

c) reading the KAM on the address corresponding to the differential bit-space of the first significant bit to the base address in the bit counter and then outputting the first bit of the roforone (bit pattern) from the command decoder and enabling the correlator with the signal SCTRL,

d) repeating the previous step with the next bitwise bit spacing and the next bit of the reference pattern, wherein the address corresponding to the difforential bit spacing has been obtained in the address calculator by addition to the base address.

To implement these method steps is a circuit arrangement in which a command counter with a first division factor a command decoder and a phase counter with a zweiton division factor as a binary counter switched bit counter are followed by a third division factor, which together form a first time unit that the instruction counter on the input side System clock (SCLK) and the instruction counter, the phase counter and the bit counter are assigned a synchronization input (SYNC_1) for resetting the first time base that the command decoder on the output thürr 'a control signal (COPY) with a second time base and via an address calculator with an address control, via an initiator output (INIT) having a correlator and a transversal filter and a control output (WE) having a data controller, an output for bit patterns with the correlator, and a control line (DMA) having a DMA controller and the second timebase is connected, that the phase counter is connected via a D 'enbus (PHASE) with the data control and the bit counter and the bit counter with the address calculator that the correlator oingangssoitig the data control and the output side of the transversal filter and the transversal filter on the output side a data bus (STATUS) Data control and a synchronization control line (SYNCB) is assigned to the second time base that the data control is connected on the output side via a bidirectional data bus with a RAM and another data bus to the DMA controller and the input receives the samples via another data bus, and that the DMA - Control is assigned to the output side of a DMA bus, and that the output of the second Zoitbasis is connected via the address control with the RAM.

The transversal filter consists of a pre and a main filter. The pre-filter is a two-stage shift register with decoder that provides oin signal at the output when the correlator provides a signal at two out of three consecutive sampling instants. The main filter is a k-stage shift register with decoder (K = 50 ... 100% of the counting range of the phase counter).

The first time base is clocked with the system clock (SCLK) resulting from dom quotients of the product of the first and second division factors and the period of the bit clock of the transmitter. The command decoder outputs the instructions for the DMA traffic, the reading / writing of samples, the control signals for the correlation and for the address calculator and the data control to the corresponding control lines. The address calculator consists of an arithmetic-logic unit with accumulator or a loadable counter arrangement with UmschaltDarem decoder network. Starting at the address of the bit counter, addresses are available at the output of the address processor, which addresses are changed by a constant dependent on the synchronization pattern with each system clock.

coordinated count. The count is programmable by the MODE register of the transversal filter.

The correlator consists of an input hetero-multiplexer, a comparator and a digital integrator. The data controller consists of one or more shift registers clocked with the write signal of the samples, a bitwise addressable register for information data, a DMA register and a multiplexer.

For the detection of random transmissions with different but previously known correlation sequences, the amount of bit sequences is tested in parallel at the same time. The correlation for multiple bit patterns is achieved by arranging several two-part RISC processors whose number η equals the number of bit patterns used, the first part of each RISC processor consisting of instruction counter, phase counter, bit counter, instruction decoder, address calculator, correlator and transversal filters each m channels with η bit patterns are assigned (m <n), and the second parts of the time base on an arrangement consisting of a logic that sets the bit pattern corresponding to the detected bit pattern in a MODE register in two successive correlations, and a decoder downstream of the MODE register, which performs the necessary mode switches (eg count amount) in the time base.

Selected addresses of the command counter, the phase counter and the bit counter, an externally programmable decoder for generating time slots for a DMA traffic in the context of a system of a plurality of RISC processors is arranged.

The instruction counter, the phase counter and the bit counter are assigned a reset input (SYNCL1) for the synchronization of several RISC processors operating in such a system.

For operation in multiple synchronization MODES, the transversal filter is equipped with multiple inputs for correlation pulses, followed by a parallel input register and a decoder with MODE register. The decoder sets after the arrival of two consecutive correlation pulses on one of the inputs of the. Transversalfilters a corresponding bit of the downstream MODE register whose outputs switch the channel recognized as active via a multiplexer to the inputs of the prefilter of the transversal filter and the contents of the MODE register as part of the status information on the corresponding bus for data control and the count of the set second time base.

Further steps are carried out by the RISC processor in system clock SCLK:

The control signal COPY of the address computer first copies the contents of the bit counter into the address computer, initializes the digital integrator and blocks the correlator via a control signal. Thereafter, with a write signal WRKORR, the contents of the shift registers are written into the RAM with the input signals digitized in the interval clock (length of a bit clock divided by the count amount of the phase counter), the sampling waveforms. In the next and subsequent clocks, the address calculator respectively determines the bit spacings corresponding to the significant bits of the bit pattern, and samples are read on the thus determined addresses of the RAM and applied to the input multiplexer of the corresponding correlator. The BI FMUSTER output of the command decoder supplies the reference pattern at the same time, which can also be supplied by an external source. Thus, at the input of the correlator there are two corresponding values in each clock, the value stored in the calculated bit distance from the current sample from the RAM and the corresponding bit of the reference pattern. The digital comparator checks the equality of both values, and if unequal, the digital integrator is reset if the comparison has been validated by a control signal SCTRL. At the end of the integration, the integrator receives the value "High" with complete identity of the sequences, otherwise the value "Low". This signal, referred to as the correlation pulse, is taken over into the following transversal filter with the clock of the initialization. The execution of the method steps are within one revolution of the command counter, i.e., an interval (length of a bit clock divided by the count amount of the phase counter). The clock frequency of the instruction counter is selected to be greater than the baud rate of the transmitter by the factor of the count of the instruction counter and the phase counter. For a large bandwidth undisturbed transmitted rectangular bit sequence has the code match the correlation signal in all intervals of a bit high level when transmit and Empfangssbittakte in phase and frequency match. Real signals are band-limited, distorted by noise, and sampled at a clock having frequency and phase differences from the transmit clock, so that in practice the correlation signal is shorter than one bit-width. Furthermore, disturbances in the correlation also occur in the case of disturbed signals, so that the correlation pulse can be missing at individual intervals. However, the correlation signal has the property that the temporal center of moment coincides to a good approximation with the optimum sampling clock. The derivation of the optimum sampling clock is realized in the transversal filter. To establish the time reference between the transmitter and the receiver, the second time base counter arrangement, clocked with the interval clock and synchronized with a synchronization signal on the transmitter, is arranged in the receiver. When using different types of synchronization and thus different synchronization words, after detecting the synchronization word, the operating mode Dos RISC processor and thus the count of the second time base can be switched. This second time base is set taking into account the constant transit times of the signals in the transversal filter with the sync pulse SYNCB. The bit clock is available at the output of the zwsite phase counter. The inventive solution further supports the construction of a data matrix.

The key advantage of the invention is that even at far lower signal-to-noise ratios than in the prior art, the useful signal is found and recognized. Another advantage of the invention is that a measure of the quality of the received useful signal of the receiver is determined and sent to the transmitter, which decides in conjunction with other relay stations, for example in a honeycomb, which station takes over the transmission of the useful signal. Namely, that relay station takes over the transmission of the useful signal, which determines the best quality of the useful signal at the receiver. This transfer of data transmission from one transmitter within a honeycomb to another is advantageously done at a time before the transmission of the wanted signal from the "worst" transmitter to the receiver has broken down.

The circuit arrangement is characterized by a good integration capability, it can be implemented in a cost-effective custom circuit. This in turn leads to the saving of a variety of components and thus the realization of small device dimensions, the reduction of manufacturing and testing costs, as well as the increase of the use value of the product by high reliability, low power consumption and small size.

embodiment

The invention will be explained in more detail in the following embodiment. The accompanying drawings show:

Fig. 1: Block diagram of the RISC processor

Fig. 2: Structure of the bit pattern and the necessary control signals

Fig. 3: Signal flow when storing the samples

Fig.4: Delay of the SYNCB pulse

Fig. 5: Signal flow in the correlation of the stored samples.

1 illustrates the structure of the RISC processor. The RISC processor has a first time base consisting of the series connection of a counter arrangement with a program counter 1 with the division factor FBEF, a phase counter 2 with the division factor FPH and a bit counter 3 designed as a binary counter with the division factor FBIT and an instruction decoder 4 connected to the instruction counter 1. The first time base can be reset via a synchronization input SYNCI and is clocked with the system clock SCLK.

FBEF x FPH SCLK =

toman represents the period of the bit clock of the unsigned transmitter. To the outputs of the instruction counter 1, an instruction decoder 4 is connected, which in the context of a method gives the following instructions to the corresponding control lines:

DMA - DMA traffic

WRKORR ₁ RDKORr - read / write correlation data

/ INIT, BITMUSTER, SCTRL - Control signals for correlation

COPY, SUBCI, SUBC2 ... - control signals of the address computer

WRDAT, RDDAT

WRPHASE.WRSTATUS - Data control control signals.

The outputs of the Bitzahlers 3 are connected to an address calculator 5. The address calculator 5 consists of an arithmetic logic unit with accumulator ocjr a loadable counter arrangement with switchable decoder network. The address calculator 5 does not perform a transfer treatment. At the output of the address calculator 5 are, starting with the address of the Bitzählors 3, addresses available to each system clock SCLK to a dependent of the synchronization pattern constant, z. Eg 0, C1, C2 ... l: ann. The word width WBITZ of the bit counter 3 and the address calculator 5 corresponds

WBITZ = log ₂ (length of the correlation pattern in bars) - log ₂ N,

where N indicates the number of samples combined in one word of RAM.

Further components of the RISC processor are one or more correlators 6, the outputs of which synchronize a second time base 8 via a transversal filter 7, and a DMA 9, data 10 and address controller 11. The correlators 6 each consist of an input multiplexer, a comparator and a digital integrator. The input multiplexer is addressed with the low part of the phase counter 2 so that at its output appear the samples previously written using the shift registers of the data controller 10 under the same address of the phase counter 2. The inputs of the digital comparator are connected to the output of the input multiplexer and to the BITMUSTER output of the instruction decoder 4.

The output signal of the comparator, tapped by the control signal SCTRL of the command decoder 4, passes to the digital integrator, which can be set by the control signal / INIT.

The data controller 10 consists of one or more shift registers clocked with the control signal WRKORR, a bitwise addressable register for the information data, a DMA register and a multiplexer. The multiplexer is controlled as follows:

Control signal data bus

WRKORR shift register

WRPHASE phase counter 2, low part of the bit counter 3

WRSTATUS transversal filter 7, MODE detection

WRDAT byte-by-byte readout of the bitwise addressable register

Tab. 1 Control signals and associated data in the multiplexer of the data controller 10 when writing data The following read operations are also controlled:

Control signal operation

DMA reading the DMA register

RDDAT byte-by-byte reading of the bitwise addressable register

Tab. 2 Control signals and processes in the data controller 10 when reading data The address controller typically represents a multiplexer, which is controlled as follows:

Control signal address bus

WRKORR address calculator 5, high part of the phase counter 2

RDDAT, WRDAT AX 8, time base 8, xx

DMA / AX 8, phase counter 2 + low part of bit counter 3, xx

Tab.3 control signals and provided by the address controller 11 addresses

where xx ... bit combinations for the physical separation of samples and information data (by the

Limiting the Zählumfanges of the phase counter 2 at typically 10 ... 12 states at 4 bit word width, the states by 11B in the high part not used by the counter Za ¹ in).

AX 8 ... MSB of the bit counter of the time base 2, separates memory areas for the construction or the output of

Telegrams via a DMA channel.

The function of the mentioned subcircuits as cross-correlator with a word width of 1 bit is realized as follows:

With the signal COPY, first the content of the bit counter 3 is copied to the address computer 5, the integrator is set via / INIT and the correlation is blocked via SCTRL. Then WRKORR writes the contents of the shift registers with the current samples into the RAM.

In the next and the following clocks, the address calculator 5 determines the respective bit spacings corresponding to the significant bits of the bit pattern, the output BITMUSTER of the command decoder 4 at the same time supplies the reference pattern,

which can also be supplied by an oxtornon source. Thus, at the input of the correlator 6 there are two corresponding values in each clock, the previously stored and the corresponding bit of the reference pattern read out in RAM at the calculated bit interval from the current sample The digital comparator checks the equality of both words (if unequal, the digital comparator is reset) At the end of the integration, the integrator contains the value "High" with complete identity of the sequences, on the other hand the value "Low".

This signal, referred to as the correlation pulse, becomes the subsequent transversal filter with the control signal / INIT

accepted.

The derivation of the optimum sampling clock is realized in the transversal filter 7, which will be described below. The correlation signal passes through the input QE to a switched as an interpolator two-stage shift register QO, Q1

(Prefilter), to which a decoder is connected whose output DC supplies the following signals:

QE QO Q1 DC

0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 0 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 1

Tab.4 output signal DC of the two-stage shift register in the transversal filter 7, where QE represents the correlation pulse at the input of the two-stage shift register

and thus eliminates correlation disorders of the duration of an interval. This η-stage shift register is also connected to an η-stage shift register clocked with / INIT, where η is the count of the

Phase counter 2 and thus the maximum length of the correlation signal - in terms of bit clocks - corresponds. To the

η-stage shift registers, a decoder is connected, which derives the position of the optimum sampling clock with an accuracy up to a constant phase shift. The decoder becomes active at the register center's symmetric assignment of the η-stage shift register. At the output of the transversal filter 7 thus creates a pulse with a constant

Runtime to the middle of the correlation signal- the synchronization pulse SYNCB for the second time base 8. The circuit can be interpreted for a plurality of bit patterns in a signal, in the embodiment 2 different Viewing synchronization patterns. The correlation to 2 Bitmustor takes place in 2 RISC processors working in parallel on each of the bit patterns

of the type described. The results of the correlation appear at corresponding control outputs for

Correlation pulses of the two RISC processors and are described in the logic for MODE detection described below

used. With two consecutive successful correlations, is the bit pattern correlated to the respective processor recognized as recognized and the corresponding bit in the transversal filter? downstream MODE register. On the processing circuit - Transversalfilter 7 - is only the valid via multiplexer

Correlation signal forwarded. The MODE bit is used to control the count of the second time base 8, To establish the time reference between sender and receiver, the clocked with / INIT in the receiver, with SYNCB on the Transmitter synchronized and thus arranged with this synchronously running counter arrangement second time base 8. This consists

a second phase counter and a multi-level second bit counter.

The permutation of the rows and columns of a η x m data matrix is done by the special assignment of the addresses of the Bit counter in conjunction with a bitwise addressable register with typically 8 bit length. The second bit counter is cascaded,

a first stage has the count amount 2 χ m, a second stage has the count amount, the length of the bitwise addressable

Register corresponds, typically 8, a third stage the count extent int (n / 8). These stages form the addresses for the data memory as follows: (ADR) = (1st stage) (3rd stage) (const.). The second counter stage addresses the bit position of the data bit during manipulation in the bitwise addressable register. The RISC processor processes three processes on a time division basis:

1. Detection of a specific bit pattern and derived therefrom the determination of phase position and position of the bit edge of the signal (synchronization).

2. Scanning and byte-by-byte formatting of data in a RAM.

3rd DMA process.

Memory access is organized such that each process serves a different area in RAM. In the following, these 3 processes will be described in more detail

 1. pattern recognition (synchronization):

Task of this sub-step is the synchronization of the second time base 8 on the phase position of the transmitter. The bit pattern to be recognized, depending on the transmitter mode, either as a contiguous pattern (concentrated mode) or time division multiplexed within a current data stream (oispcisiver mode). Furthermore, please note that the received Sigru! is noisy. Synchronization therefore takes place with the aim of ensuring signal sampling in the middle of the bit. For pattern recognition, a bit clock is divided into 10 intervals in the exemplary embodiment. For each interval, a comparison of the respective samples of the respective bit with the pattern is made in real time. The bit pattern and the necessary control signals are clocked by the instruction decoder 4 provided by the instruction counter 1 as shown in Figs. 1 and 2. In the address calculator 5, the addresses of the samples in the memory are calculated. The process of synchronization can be considered in two steps:

1. Storing the samples, Fig.3, and

2. Evaluation of the stored samples.

The corresponding samples and the bit pattern are supplied to the correlator 6. If this determines a match of the values with the pattern over the 28 correlation clocks used in the exemplary block, then the correlation signal with Hlgh level is forwarded to the transversal filter 7. The lower the signal-to-noise ratio of the input signal actual, the shorter the sequence of correlation impulses. A special prefilter ensures synchronization after at least successive successful correlations and interpolates individual bit errors of a disturbed sequence of corruption pulses. The transversal filter 7 represents a shift register with a connected decoder which, in the case of symmetrical (outgoing from the register center) normalization of high states, contains the synchronization pulse SYNCB for the second time base 8 In constant phase to the middle of the bit. The failure of the correlation for the duration of exactly one interval (Burststörquello) does not affect the work of the transversal filter The correlation signal, regardless of its actual width, takes a symmetrical position with respect to the bit center in the last bit of the bit pattern (see Table 5) ).

Length of the Correlation Signal (Intervals)

Location of the correlation signal within the last bit of the pattern

2 3 4 5 6 7 8 9 10

0 0 ( 0 1 1 0 0 0 0 0 0 ( J 0 1 1 1 0 0 0 0 0 ( ) 1 1 1 1 0 0 0 0 0 ( 3 1 1 1 1 1 0 0 0 0 I 1 1 1 1 1 0 0 0 0 I 1 1 1 1 1 1 0 0 1 I 1 1 1 1 1 1 0 0 1 I 1 1 1 1 1 1 1 1 1 I 1 1 1 1 1 1 1

Tab. 5 Location of the different width correlation signal within the last bit of the bit pattern

The transit time of the SYNCB pulse, measured from the bit edge of the last bit of the bit pattern to the LH edge of the SYNCB pulse, is independent of the number of correlation pulses. In the example, the runtime is 11 (+0, -1) intervals. The delay is attributed to the pre-filter (1 interval) and the main filter (10 intervals). The tolerance arises from possible fluctuations in the symmetry of the position of the correlation pulses to the middle of the bit with an odd number of pulses. With the SYNCB pulse, the second time base is set so that the second phase counter generates the bit clock within the second time base. Likewise, the frame for word synchronization is initialized by resetting the second time base; Fig.4, Fig.5.

Claims (6)

1. A method for clocked correlation and signal processing by means of RISC processor for synchronization to a bit pattern with variable, time-discrete bit spacing in message channels, characterized in that the RISC processor (4) performs the following steps in an orderly order at system start SCLK: a) Taking over the state of the bit counter (3) as the base address in the address computer (5) with the .Signal COPY, assumption of the correlation of the correlator (6) in the transversal filter (7) and subsequent initialization of the correlator (6) by the signal INIT . b) writing (WE) the current sample into the RAM (12) to the address determined by the phase counter (2) and the bit counter (3), c) reading the RAM (12) at the address corresponding to the differential bit-space of the first significant bit to the base address in the bit counter (3) and then outputting the first bit of the reference pattern (BITMUSTER) from the command decoder (4) and enabling the correlator (6 ) with the signal SCTRL, d) repetition of the previous step with the next differential bit spacing and the next bit of the reference pattern, wherein the address corresponding to the differential bit spacing, in the address computer (5) was obtained by addition to the base address. 2. Circuit arrangement for clocked correlation and signal processing by means of RISC processor for synchronization to a bit pattern by means of variable time-discrete bit spacing in message channels for carrying out the method according to claim 1, characterized in that a command counter (1) an instruction decoder (4) and a phase counter (2) a bit counter (3) are arranged downstream of the instruction counter (1) on the input side a system clock (SCLK) and the instruction counter (1), the phase counter (2) and the bit counter (3) a synchronization input (SYNC_1) for resetting the first Associated with time base are that the instruction decoder (4) on the output side by a control signal (COPY) with a time base (8) and via an address computer (5) with an address controller (11), via an initiator output (INIT) with a correlator (6) and a transversal filter (7) and a control output (WE) with a data controller (10), an output for bit patterns with the correlator (6) so as a control line (DMA) with a DMA controller (9) and the time base (8) is connected, that the phase counter (2) via a data bus (PHASE) with the data controller (10) and the bit counter (3) and the bit counter (3) connected to the address computer (5) that the correlator (6) on the input side, the data controller (10) and the output side of the transversal filter (7) and aem transversal filter (7) on the output side a data bus (STATUS) for data control (10) and a Synchronization control line (SYNCB) is assigned to the time base (8) that the data controller (10) on the output side via a bidirectional data bus with a RAM (12) and another data bus to the DMA controller (9) is connected and the input side via another data bus receives the samples, and that the DMA controller (9) on the output side is assigned to a DMA bus, and that the output of the time base (8) via the address controller (11) to the RAM (12) is connected. 3. Circuitry for clocked correlation and signal processing according to claim 2, characterized in that the transversal filter (7) consists of a pre- and main filter, that the pre-filter is a two-stage shift register with decoder which provides a signal at the output, if at two of three consecutive sampling times, the correlator (6) provides a signal, and that the main filter is a k-stage shift register with decoder (k = 50 ... 100% of the count of the phase counter (2)). 4. Circuit arrangement for clocked correlation and signal processing according to claim 2, characterized in that the clock frequency of the command counter (I) is selected so that it by the factor of the Zählu start of the program counter (1) and phase counter (2) is greater than that Baud rate of the transmitter. 5. Circuit arrangement for clocked correlation and signal processing according to claim 2, characterized in that a plurality of two-part RISC processors are arranged, whose number η the number of bit patterns used, wherein the first part of each RISC processor consisting of instruction counter (1) , Phase counter (2), bit counter (3), command decoder (4), address calculator (5), correlator (6) and transversal filter (7) each m channels with η bit patterns are assigned (m <n), and their second parts the time base (8) via an arrangement consisting of a logic which, in the case of two consecutive correlations, sets the bit corresponding to the recognized bit pattern in a mode register and a downstream one of the MODE register Decoder which performs the necessary mode switches (e.g., count amount) in the time base (8). 6. Circuit arrangement for clocked correlation and signal processing according to claim 2, characterized in that at selected addresses of the command counter (1), the phase counter (2) and the bit counter (3) an externally programmable decoder for generating time slots for a DMA traffic is arranged in the context of a system of a plurality of RISC processors, and in that the instruction counter (1), the phase counter (2) and the bit counter (3) is assigned a reset input (SYNC_1) for synchronizing a plurality of RISC processors operating in such a system.