EP0833477A2 - Method for the determination of a sampling phase - Google Patents

Abstract

The sampling phase determination method has each digital value (DB) of the digital data stream (DS) sampled a number of times, with a sub-data bit sequence (SDBF) entered in a serial register bank. The sub-data bits are divided into bit groups with a given number of bit positions, with detection of the same binary values for the corresponding bit positions within at least 2 bit groups, for determination of the required sampling phase for the digital data within the digital data stream.

Description

The invention relates to a method for determining a sampling phase, by means of digital data from a digital Data stream can be obtained. The invention further relates to a device for performing the method.

Such a method is e.g. for cordless telecommunication devices for wire-free transmission of data and Voice information used. With cordless telecommunications in the home area there is often a transmission after DECT standard (Digital Enhanced Cordless Telecommunication) used. For a better understanding of the invention before Background of the prior art will be described in the following data transmission according to the DECT standard, which is an important application for the present invention is.

According to this DECT standard, 120 transmission channels are available Available, with frequency bands in the range between 1.8 and 1.9 GHz can be used. Within each frequency band the data is transferred using the TDMA method (TDMA Time Division Multiple Access), which is a time division multiplex frame of 10 ms. Such a time division frame is shown in Figure 1. Through this time-division multiplex frame 24 time channels are defined (channels 0 to 23 in FIG. 1), which provides a framework. This framework scheme is used so that for each frequency band twelve mobile end stations, so-called mobile stations MS, with a base station BS can work in duplex mode at the same time, i.e. Transfers are possible from the stations MS to BS and from BS to MS or from BS to MS and from MS to BS. The 24th Time channels are assigned a time slot of 417 µs each, within which the data is transmitted.

In the TDMA method mentioned, for example, in each Time slot a time frame, also called "burst", of 365 µs transmitted, which is approximately a frame length of 420 bits and corresponds to a data throughput of 42 kbit / s. Related to taking into account the time-division multiplex frame, that at both ends of the time frame 30 bits each as security zones GS (Guard Space GS), e.g. to avoid Interference overlaps with adjacent time slots are provided are, a bit rate of 1.152 Mbps.

The temporal sequence of the transmitted impulses each According to FIG. 2, time-division multiplex frame corresponds to a PH channel, the so-called "physical channel", which is based on the layer model for data transfers of the physical layer (physical layer) is assigned. The transmitted data packet of 420 bits is called a PH packet and contains a D field. Of the 420 data bits, which are a sequence of H-L bit values corresponds to (H (High) - high level value; L (Low) - low level value) become 32 bits for synchronization and 388 bit for the transmission of user data NI (Net Information) used. Divide the 32 bits for synchronization again in two data bit sequences of 16 each Bit. The first data bit sequence, i.e. the episode with the first 16 H-L values, is a synchronization introductory word SY-EW, which is also called the preamble. Through this synchronization introduction word SY-EW becomes the synchronization initiated. For the transmission direction mobile station MS this synchronization initiation word exists after base station BS Ideally, SY-EW from an L-H-L-H bit sequence corresponding to a 0101 bit sequence. For the reverse direction of transmission from base station BS to mobile station MS the synchronization introduction word SY-EW from a periodic H-L-H-L bit sequence or a 1010 bit sequence.

The bit sequence with the second 16 H-L bit values, the second Data bit sequence, is a synchronization confirmation word SY-BW, with those with the synchronization introductory word SY-EW initiated synchronization must be confirmed. For such confirmation must be the synchronization confirmation word SY-BW at least for the most part of the data bits be recognized. Only then are those following the sync field Data accepted. The synchronization is then initiated, if it is assumed with a certain probability may have the sync initiation word SY-EW an L-H-L-H bit sequence or an H-L-H-L bit sequence.

A communication system according to the DECT standard includes in the simplest form a base station and at least one mobile station. More complex systems, e.g. networked systems several base stations, each with several mobile stations. Due to the 24 time channels defined in the DECT standard can be assigned up to twelve mobile stations to each base station with the respective base station in duplex mode communicate. For the one defined in the DECT standard Time multiplex frame of 10 ms has the consequence that in Duplex operation every 5 ms of data from the base station to one Mobile station or vice versa.

Figure 3 shows one for communication systems according to the DECT standard typical communication arrangement KA with non-wired Data transmission, the mobile station MS as Transmitting device SG and the base station BS as receiving device EG serves. The communication arrangement KA can also do this be modified that the base station BS as a transmitter SG and the mobile station MS serves as a receiving device EG. The transmitter SG has a transmitting antenna SA, through which one of the Transmitting device SG generates radio signal FS to receiving device EG is sent. In order to be able to receive the radio signal FS, the receiving device EG also has a receiving antenna EA.

As mentioned, the communication system works according to the DECT standard with a high frequency carrier signal with a carrier frequency between 1.8 and 1.9 GHz, which with a in the Transmitter SG present digital broadcast data stream SDS modulated a transmitter-specific clock (also called phase) becomes. The digital present in the transmitter SG Data stream contains the necessary for wireless transmission Information. This information also includes the synchronization and user information already mentioned, which are contained in the PH packet of 420 bit data length are. With the help of this PH data packet is now in the sending device SG generates the modulated radio signal FS (carrier signal) and according to the DECT standard for data transmission in regular, time intervals specified by the time division multiplex frame ZMR for a period of time predetermined by the time slot transfer.

To the transmitted data, e.g. those transmitted per time slot TS Voice information to be able to decrypt the radio signal FS, i.e. the modulated carrier signal, in the receiving device EG can be demodulated. After demodulation arises a digital receive data stream EDS, which at a interference-free transmission of the radio signal FS the same bit pattern has, like the transmission data stream SDS. This trouble-free Receive data stream EDS is shown in block EG on the right. In the event of a faulty transmission of the radio signal FS there is a deviation from the bit pattern of the transmission data stream Bit pattern, which is shown on the left in block EG. After the demodulation of the radio signal FS and the generation of the received data stream EDS must be for further processing in the terminal EG to a terminal-specific clock signal be synchronized. The phase position of the clock signal in with respect to the data bits of the received data is high Meaning. Sampling of the received data is desired in the middle of the data bits, because one scan outside of this bit center leads to an increased error rate and reduces the sensitivity of the receiving device EG.

DE 42 36 775 C2 describes a method for determining the Known sampling phase, using the digital data from a digital data stream can be obtained. The incoming data are oversampled 9 times per digital value, so that for each Digital value a bit group with nine bit positions is generated. To determine the optimal sampling phase, i.e. the sampling time in the middle of a digital value, the bit string at the beginning of each time frame (burst), i.e. the Preamble, evaluated. Based on the known bit pattern determines the middle of a digital value and the associated one Sampling phase set for the rest of the time frame is held. This sampling phase becomes a clock signal constant frequency generated, with the help of the received data are scanned with bit accuracy and the received data stream is won.

In the known method, the 9-fold oversampled Receive data loaded into a register bank. The binary values in this register bank are compared with a predetermined pattern and the respective bit center is determined. To the end of the bit pattern, i.e. at the end of the preamble, the last digital value determined sampling phase leading to a Bit center heard, recorded and then for the rest of the time frame maintained. The ones previously identified within the bit pattern Bit centers and the associated sampling phases are not considered. So it's the bit center of one Digital values or data bits responsible for the determination the sampling phase and thus for the generation of the digital Data from the received digital data stream. If so This data bit is disturbed, you get from the known one Process an inaccurate sampling phase, resulting in increased bit error rates leads within the timeframe concerned.

It is an object of the invention, a scanning method and a Specify the scanning device, which consists of a digital Data stream determined sampling phase with high accuracy in with respect to the center of the incoming data bits.

This object is achieved with a method according to the invention solved the following steps: the a predetermined bit pattern containing digital data stream with a fixed Data rate becomes n times per digital value according to oversampling scanned; the sub-data bit sequence created during the scan becomes temporary in a serial register bank stored, with each scan in agreement with a clock pulse a shift of the stored sub-data bits in the register bank by one bit position and the sub data bit generated during the scanning into the first bit position the register bank is written; those in the register bank Sub-data bits contained are in bit groups of n-bit positions divided; Binary values of at least one matching one Bit position within at least two bit groups are compared to each other in a match checked; depending on the result of the comparison, the sampling phase fixed.

In the invention, matching bit positions are at least two bit groups evaluated, the serial in the register bank are saved. The comparison with a given one Bit patterns as target patterns as in DE 42 36 775 C2 are omitted. The evaluation of at least two bit groups increases the statistical certainty for the determination of the sampling phase. The greater the number of bit groups evaluated, the greater will this statistical certainty. In practice it has it turned out that the evaluation of four bit groups and from five bit positions within each bit group to one compared to the prior art increased accuracy of the sampling phase leads. Since there are several digital values or data bits contribute to the sampling phase at a particular point in time fixed and then maintained for the rest of the time frame is the risk of freezing an unfavorable sampling phase significantly reduced. The sensitivity of the receiving device is accordingly by the inventive method clearly improved.

According to another aspect of the invention, a device to determine a sampling phase with the features of Claim 12 specified. The achievable with this facility Advantages are essentially the same as those adjust themselves when performing the above-mentioned procedure.

Figur 1 bis 3

Festlegungen der Datenübertragung gemäß dem DECT-Standard sowie die leitungsungebundene Datenübertragung zwischen einem Sendegerät und einem Empfangsgerät,

Figur 4

ein Blockschaltbild mit den wesentlichen Funktionseinheiten eines schnurlos arbeitenden Telekommunikationsgerätes mit einem Empfangsteil und einem Digitalteil,

Figur 5

ein Blockschaltbild mit wichtigen Funktionseinheiten des Digitalteils für die Demodulation eines modulierten Analogsignales und für die Erzeugung einer Abtastphase zur Synchronisation eines digitalen asynchronen Datenstroms auf ein gerätespezifisches Taktsignal,

Figur 6

ein Blockschaltbild der Einrichtung zum Erzeugen einer Abtastphase,

Figur 7

eine Schaltungsanordnung zum Erzeugen eines Datenwortes, anhand dessen ein Erkennungssignal und damit die Abtastphase festgelegt wird,

Figur 8

logische Verknüpfungen in Tabellenform zum Erzeugen des in Figur 7 dargestellten Datenwortes,

Figur 9

einen Zähler zur Ermittlung der Anzahl von Taktimpulsen bei denen der Wert des Datenwortes unverändert ist,

Figur 10

ein Flußdiagramm, welches Verfahrensschritte zur Erkennung des Maximum des Wertes des Datenwortes zeigt, und

Figur 11

eine Schaltungsanordnung zur Festlegung des Erkennungssignals und damit der Abtastphase auf der Grundlage der Anzahl der Taktimpulse für das Maximum.

In the following the invention is further explained with reference to the drawings, which show an embodiment of the invention in addition to the already known prior art. The figures show:

Figure 1 to 3

Definitions of data transmission in accordance with the DECT standard as well as line-free data transmission between a transmitting device and a receiving device,

Figure 4

2 shows a block diagram with the essential functional units of a cordless telecommunication device with a receiving part and a digital part,

Figure 5

2 shows a block diagram with important functional units of the digital part for the demodulation of a modulated analog signal and for the generation of a sampling phase for the synchronization of a digital asynchronous data stream to a device-specific clock signal,

Figure 6

2 shows a block diagram of the device for generating a sampling phase,

Figure 7

a circuit arrangement for generating a data word, on the basis of which a recognition signal and thus the sampling phase is determined,

Figure 8

logical links in table form for generating the data word shown in FIG. 7,

Figure 9

a counter for determining the number of clock pulses in which the value of the data word is unchanged,

Figure 10

a flowchart showing method steps for recognizing the maximum value of the data word, and

Figure 11

a circuit arrangement for determining the detection signal and thus the sampling phase on the basis of the number of clock pulses for the maximum.

Figures 1 to 3 were already at the beginning of the explanation of the prior art. In the following Figures is partly based on the representation in the figures 1 to 3 referenced.

FIG. 4 shows the structure of a by means of a block diagram cordless (line-bound) telecommunication device 1 as e.g. as a base station or mobile station in one, e.g. Cordless communication system defined according to the DECT standard is usable. The telecommunication device 1 has in addition to functional units not shown in detail Receiving part 10 for the reception of for information transmission modulated analog RF signals AS, a digital part 13 for evaluation and further processing of one from the respective RF signal AS demodulated digital data stream DS as well a peripheral part 18 for outputting or forwarding the using the RF signal AS and the digital data stream DS transmitted information. The receiving part 10 of the telecommunication device 1 is with the output terminal of an antenna 11 connected. Over a radio transmission link 2 can the RF signals emitted by a transmitter 3 AS are received. The signals from antenna 11 are one Receiving device 12 fed to a receiving circuit 120 and a demodulation circuit 121 contains. The receiving circuit 120 prepares that received by the antenna 11 modulated analog RF signal AS for demodulation in the Demodulation circuit 121 on. When demodulating the RF signal AS arises at the output of demodulation circuit 121 the digital data stream DS. This data stream DS is with a data rate of 1.152 Mbit / s via a data line 4 a control device 14 of the digital part 13 transmitted.

The demodulation circuit 121 is via a first control line 5 directly connected to the control device 14. Furthermore, the demodulation circuit 121 is via a second Control line 6 and a compensation circuit 19 in the receiving part 10 connected to the control device 14. The Control device 14, in particular the reception of the digital Data stream DS, the synchronization of the digital part 13 with the demodulated data stream DS and the switching of Controls connections according to the TDMA method, in turn connected to a computer 16 via a bus interface 15. The computer 16 contains a microprocessor 160 and one with this connected digital memory 161. The computer 16 is for all control and programming processes in the Telecommunication device 1 responsible. For example the control module 14 indirectly via the bus interface 15 programmed by the microprocessor arrangement 16.

The computer 16 also controls an ADPCM and CODEC circuit 17, what interface functions between the control device 14 and the peripheral part 18 takes over. For The circuit receives implementation of its interface function 17 also control signals from the control device 14. Das Peripheral part 18 contains devices that are different from the digital part 13 processed digital data stream DS after a D / A conversion e.g. converted into acoustic signals or the Data stream DS to an external analog communication network passes on.

Figure 5 shows the basic structure in a block diagram of the digital part 13 according to FIG. 4, in particular the structure of the parts necessary for the synchronization of the receiving part 10 received digital data stream DS are required. The control device 14 contains a sampling phase generator 140, the digital data stream used to generate the sampling phase APH DS is fed. The sampling phase generator 140 is with an oscillator 141, a registration device 142 and a detection circuit 143 connected to the noisy signals recognizes and signals this.

The oscillator 141 generates a clock signal TSI whose clock frequency is 9 times the frequency with which the digital Data stream DS is transmitted. The clock signal TSI is excluded the sampling phase generator 140 also the registration device 142 fed. Between the registration device 142 and the Sampling phase generator 140 are used during the generation of the Sampling phase APH status messages SM0 and SM1 exchanged. The registration device 142 also receives one from the computer 16 of the digital part 13 generated status message SM2 and a status message generated by the detection circuit 143 SM3. From the status messages SM0, SM2 and SM3 and the clock signal The registration facility generates the status message TSI SM1, which is fed to the sampling phase generator 140 becomes. The status messages SM0 to SM3, their function in context with the structure of the control device shown in Figure 6 14 still to be described are dynamic ones Time-changing status messages in the control device 14 arranged for the generation of the sampling phase APH Assemblies 140, 142, 143.

When the last status message SM1 is received, the sampling phase generator generates 140 from the digital data stream DS and the clock signal TSI the final sampling phase APH, which then in addition to the digital data stream DS for the synchronization of a Synchronization arrangement 144 is supplied. This synchronization arrangement 144 generated from the digital data stream DS and the sampling phase APH a synchronized digital Data stream SY-DS, which is then in the control device 14 of the Telecommunications device 1 is processed. The of the sampling phase generated by the sampling phase generator 140 however, not just the synchronization arrangement 144, but also supplied to the registration device 142. Along with the data stream also supplied to the registration device 142 DS, this registration device 142 generates the control signal STS, which via the control line 5 of Figure 4 Demodulation circuit 121 and the control line 6 after 4 of the compensation circuit 19 of the receiving part 10 is fed.

Figure 6 schematically shows the structure in a block diagram a device for sampling phase generation, the sampling phase generator 140, the oscillator 141, the registration device 142 and the detection circuit 143 contains (cf. Figure 5). The sampling phase generator 140 contains a suppression circuit 1400, a register bank 1401, an over a bus interface device 1402 with the register bank 1401 connected bit sequence detection circuit 1403 and one Selection circuit 1404. The sampling phase generator 140 serves to do this, together with the registration device 142 and the Detection circuit 143 from the digital data stream DS within a period of time by the sync word SY-EW (preamble) defined according to Figures 2 and 3 is, the sampling phase APH for synchronization in with respect to the data stream DS.

The data stream DS first becomes the suppression circuit 1400 fed. This suppression circuit 1400 operates according to the shift register principle, i.e. to push the Data stream DS a clock signal must be applied. In the present Fall becomes the clock signal generated by the oscillator 141 TSI with an n-fold clock frequency TFn on the suppression circuit Given 1400. Through this clock signal TSI the digital data stream DS is bit by bit with a sampling rate sampled according to the clock frequency TFn. Each one Data bit DB of the digital data stream DS is thus in one Series of sub-data bits SDB disassembled and then examined for errors. Multiple consecutive data bits DB result several series of sub data bits SDB; these series are in hereinafter referred to as sub data bit sequence SDBF.

The accuracy with which the sampling phase APH is determined can increases with the number of sub data bits SDB per data bit DB on. Since in the present case a 9-fold sampling of the digital data stream DS takes place at a transmission speed 1.152 Mbps of the digital data stream DS the clock signal TSI has a clock frequency TFn with n = 9 of 10.368 MHz.

In the suppression circuit 1400 for each data bit DB Data stream DS nine sub-data bits SDB generated as samples. The function of the suppressor circuit 1400 is to ascertained and e.g. inhomogeneous caused by noise H-L-H bitsubsequence or an L-H-L bitsubsequence of Recognize and suppress sub-data bit sequence SDBF. Thereby ensures that the suppression circuit 1400 downstream register bank 1401 only such data bits DB of the digital data stream DS are supplied at which a sub-data bit sequence SDBF without an inhomogeneous "H-L-H" bit sub-sequence or "L-H-L" bit sub-sequence is present.

Register bank 1401 contains four in the present case Shift registers SR1 to SR4, which are in a daisy chain are arranged. Each of these four shift registers SR1 to SR4 is used to clock the digital data stream DS the register bank 1401 with the clock signal TSI with a clock frequency supplied by TFn, where n = 9.

Each shift register SR1 to SR4 stores a data bit DB of the data stream DS. It follows that when scanning the Data bits DB a total of 36 sub data bits SDB as a sub data bit sequence SDBF are buffered in the register bank 1401. With each clock of the clock signal TSI changes in the Shift registers SR1 to SR4 cached sub-data bits SDS. After 36 consecutive clocks of the clock signal TSI is that in the zeroth bit position of the shift register SR1 cached sub data bit in the last bit position of the Shift register SR4 pushed through. The one in the register bank 1401 Sub-data bit sequence buffered at each clock time SDBF is via the bus interface device 1402 to the bit sequence detection circuit 1403, to the detection circuit 143 and to a bit equality detection circuit 1420 transferred to the registration device 142. The Bit sequence detection circuit 1403 has the task of 0101 or the 1010 bit sequence of the preamble of the data stream DS recognize and determine the point in time at which the respective Bit has reached its bit center. This middle bit sets then set the sampling time for the subsequent bits. in the The method used for this is explained in more detail below.

FIG. 7 shows schematically how the binary values contained in the individual shift registers SR1 to SR4 are linked to one another. In a first AND gate 30, the binary values of the fourth bit position of the bit groups stored in the shift registers SR1 to SR4 (1st bit to 4th bit) are linked together. It should be noted that the binary values of the different bit groups are negated alternately in order to be able to correctly evaluate the sequence of 1010 values or 0101 values. The fourth bit position in the respective shift register SR4 to SR1 is the middle bit position. In a second AND gate 32, the binary values of the third and fifth bit positions of the four shift registers SR1 to SR4 are linked, ie the bit positions adjacent to the middle bit position. Finally, there is a further link in the AND gate 34, the binary values of the second and sixth bit positions of the shift registers SR1 to SR4 being linked. In the case of the AND gates 32 and 34, the cable routing is not shown completely for reasons of clarity. The results of the AND gates 30, 32 and 34 are combined to form a data word a which has the bit positions a2, a1 and a0. Data word a can be interpreted as a binary number, ie as a2 ² + a1 ¹ + a0 ⁰ with base 2.

As mentioned, two are used as preamble in the DECT standard Cases distinguished, namely a bit pattern with an L-H-L-H bit sequence (0101 bit sequence) or an H-L-H-L bit sequence (1010 bit sequence). This results in an 0101 bit sequence the data word a with the coefficients a2, a1 and a0; For a 1010-bit sequence, a data word b results with the Coefficients b2, b1 and b0.

The results for the logic operations for both bit sequences are shown in a table in FIG. An underline indicates that the respective binary value in the bit position is processed inverted; the number before the point refers to the respective bit group, the number after the point refers to the respective bit position. The representation 1.4 & 2.4 has the meaning that the negated binary value of the fourth bit position of the first bit group is ANDed with the non-negated binary value of the fourth bit position of the second bit group.

As shown in FIG. 8 below, the respective coefficients of the data words a and b are ORed further, so that the result is the data word c with the coefficients c2, c1 and c0, the data word c being c2 ² + c1 ¹ + c0 ⁰ to base 2 is interpreted. The highest value of the data word c is thus in binary notation 111 and in decimal notation 7; its lowest value is 000 or decimal 0. Data words a, b and c represent a measure of the correspondence of the respective binary values in the shift registers SR1 to SR4. When the sub-data bits with the clock frequency TFn are shifted through the shift registers SR1 to SR4 , during the preamble the data word c will normally fluctuate between binary 000, ie decimal 0, and binary 111, ie decimal 7, and in between also assume the values binary 100, ie decimal 4, and 110, ie decimal 6. For the "binary 000" case mentioned, the transitions of the data bits DB are in the middle of the shift registers SR1 to SR4; the case "binary 111" is when the centers of the data bits DB match the middle bit position of the respective bit groups, ie the fourth bit position in the shift registers SR1 to SR4 according to FIG. 7. The case that the data words a, b or c have the maximum value binary 111, can occur in the evaluation shown in FIG. 7 for a maximum of five successive cycles. The middle of the data bits in the middle cycle is then below those cycles for which the maximum value has been detected.

It can happen that with heavily disturbed data bits DB with non-symmetrical pulse-pause ratio the maximum value binary 111 is not reached. However, it turns out to be a relative one Maximum one, for example a value for the data words a, b or c of 110 (decimal 6) or 100 (decimal 4). For this relative maximum, the middle clock also applies among those clocks for which this relative maximum is detected the middle of that shown in Figure 7 Data bits DB indicates. In this way, according to the invention the center of a data bit DB can be detected exactly, even if the data bits DB are disturbed. Because in the evaluation according to the example of Figure 7 four bit groups, i.e. four data bits DB are evaluated, there is a high statistical security when recognizing the middle of the data bit.

In order to determine whether the data word c has assumed a maximum value, the current data word c is compared with the data word c _alt , which was determined one cycle earlier. In practical terms, the data word c _{alt is held} by one cycle, so that it is still available for evaluation in the current cycle. If, for the first time, the value of the current data word c is less than that of the data word c _old , then the definition falls below a maximum. Since this maximum is usually present for several cycles, the width of the maximum, ie the number of cycles for which this maximum has been detected, must first be determined. A counter Z is used to determine the number of clock cycles for which the maximum value was present, and the clock pulses for the state c = c old counts. In Figure 9 the counter Z is shown as a Moore automaton. According to legend, the output signal A is a variable which indicates for how many cycles the value of the data word c has remained constant. The input signal G, on the basis of which a new state s0 to s7 is established, is generated in accordance with the sequence steps according to FIG. 10.

Figure 10 shows a flow chart, the processing of which already mentioned variable G is generated, which at the counter 9 is required as an input variable. Continue to be set the following binary sizes: Da and D, which ones as an input signal and output signal for an edge triggered Flip-flop according to FIG. 11 are used; the size M, which acts as an input signal to the circuitry 11 is used and indicates that a maximum has been determined; also the binary sizes V1, V2 and V3, which are also in the circuit arrangement according to FIG 11 are used and a shift of one or several cycles cause, as in connection with FIG. 11 is explained.

In the flowchart according to FIG. 10, it is determined in the first step 36 whether the current value of the data word c matches the previous value of the data word c _alt . If this is the case, the variable G is set to 1, the other variables D, M, V1 to V3 are set to 0. Setting the variable G to 1 causes the counter Z according to FIG. 9 to be counted up by 1, that is to say its output signal A is increased by 1. If no match has been found in step 36, then in subsequent step 38 it is checked whether the current value of the data word c is greater than the previous value c _old . If this is the case, the variable G is set to 0, which means that the counter Z according to FIG. 9 is reset and assumes the state s0. The other sizes are set to 0. If a negative result is determined in step 38, ie the current value of the data word c is less than the previous value c _alt - the maximum of the value was therefore undershot - then in the following step 40 the value of the variable D is checked. If the variable D has the value 1, the variable G is set to 0, the size Da to 1 and the other sizes to 0.

If the test result in step 40 is positive, it is dependent on the different from the current meter reading according to FIG Sizes set. When the counter reading is A = 0, the variables Da and M set to 1; the other variables G, V1, V2, V3 are set to 0. With a counter reading A equal to 1 or 2, the variable V1 is also set to 1. At the Meter reading A is 3 or 4, variable V2 is set to 1, and if the payer A is 5, 6 or 7, the Variable V3 set to 1.

Figure 11 shows a circuit arrangement for generating a Recognition signal ESI, which by a predetermined number of clocks, which are defined by the variables V1, V2, V3 against a maximum pulse is shifted by the variable M is defined with value 1. The circuit arrangement contains four cascaded flip-flops 52 to 58 which can be controlled by the clock pulse TSI. Furthermore contains the circuit arrangement AND gates 60 to 70, an input AND gate 72 and OR gates 74 to 78. The link elements mentioned have inverting inputs that are in the Figure 11 are identified by a dot. In the picture part A flip-flop 51 is shown at the top right of FIG. 11, which serves to delay the variable Da by one clock, i.e. the output variable D takes the after a clock pulse Value of the variable Da an.

The mode of operation of the circuit arrangement according to FIG. 11 is as follows. The set in the sequence control according to Figure 10 Variables M, V1, V2, V3, Da and D are called rectangular pulses interpreted, depending on the switching logic used the value 0 of a variable is an L value and the value 1 is an H value or vice versa. First the case be considered that the variables according to block 44 in Figure 10 are defined, i.e. for a payer A equal 0. After the variables V1, V2, V3 have the value 0 and M is 1, the input AND gate 72 generates a logic 1 at its exit. The flip-flop 52 is in the next clock generate a logical 1 at its output, whereupon the AND gate 60 has a logic 1 at its output generated and via the OR gate 74, the input of the flip-flop 54 is set to logic 1. The next bar will be similar Way the input of flip-flop 56 is set to logic 1, and at the next but one clock, the input of the flip-flop 80. The following clock appears at the output of the flip-flop 58 a logical 1, i.e. the detection signal is ESI set to logical 1. It should therefore be noted that the Change of state from logic 0 to 1 of the detection signal ESI by four bars compared to the appearance of a logical 1 where the variable M is shifted. Since the variable indicates M that a maximum has been recognized is the detection signal ESI delayed by four cycles compared to this maximum detection.

In the event that the counter reading A is 1 or 2, i.e. the maximum was for two or three bars, the Variables set according to block 46. The variable has V1 accordingly a logical 1, with the result that the input AND gate 72 is blocked. Lie at the input of the AND gate 62 however the variables V1 and M each with logical 1, and the input of flip-flop 64 is set. After expiration of three clocks of the clock signal TSI appears at the output of the Flip-flops 58 as a detection signal ESI a logical 1. Das Detection signal ESI is therefore opposite to the setting of the variables M shifted to logical 1 by three measures.

Similarly, there is a two shift Cycles when the variable V2 is set to logic 1, i.e. the variables are defined according to block 48 in FIG. 9, which is assigned to the meter reading A equal to 3 or 4. At a counter reading A is 5, 6 or 7 are the variables defined according to block 50, i.e. the variable V3 has the Logical value 1. There is a delay between the Appear variable M as logical 1 and the output signal of the flip-flop 58, the detection signal ESI, by one Clock of the clock signal TSI. That way to the respective Width of the maximum adjusted delay of the variables M leads to the average of the detection signal ESI Middle of those stored in register bank 1401 Data bits of the preamble of the data stream DS and thus an optimal one Sampling time, namely the sampling phase APH determined can be.

The selection circuit is used to correct the sampling phase APH 1404 used according to Figure 6. For example, it is as Counter formed by the oscillator 141 with clock pulses is controlled and each by the detection signal ESI reset to the bit center of the individual data bits becomes.

With the delivery of the detection signal ESI, the bit sequence detection circuit 1403 to a counter 1421 of the Registration device 142 from the status message SM0. With this Status message SM0 is communicated to the counter 1421, that the first 0101 or 1010 bit sequence has been recognized is. The counter 1421, which is also provided by the oscillator Is clocked, counts the number of transmitted to it Status messages SM0.

Has completed the procedure described above m times where m is generally less than n (e.g. m = 3), then the counter 1421 waits for an additional signal ZS from of bit equality detection circuit 1420 and evaluates the Status messages SM3, SM2 of the detection circuit 143 and the Microprocessor arrangement 16 from. Depending on the status messages SM2, SM3 or the additional signal ZS are the counting device 1421 the status message via an OR gate 1422 SM1 to the selection circuit 1404.

With this status message SM1 the further reset the selection circuit 1404, thereby preventing the sampling phase APH by feeding the detection signal for the last time ESI is generated. With the transmission of the additional signal ZS is the counter 1421 by the bit equality detection circuit 1420 communicated that the sync initiation word SY-EW has ended and the sync confirmation word SY-BW begins. At this point, the sampling phase APH generated for synchronization.

With the status message SM3, the counter device 1421, in the event that a "noisy" actual data stream I-DS or Data stream DS was recognized, reset. With the status message SM2 is informed to counter 1421 whether that Sync actuation word SY-BW was recognized, i.e. a DECT-specific Time slot TS is present.

Claims (19)

Method for determining a sampling phase (APH), by means of which digital data are obtained from a digital data stream (DS), with the following steps: the digital data stream (DS) containing a predetermined bit pattern with a fixed data rate is sampled n times per digital value (DB) in accordance with an oversampling, the sub-data bit sequence (SDBF) resulting from the scanning is temporarily stored in a serial register bank (1401), with a shift of the stored sub-data bits (SDB) in the register bank (1401) by one in accordance with a clock pulse (TSI) Bit position occurs and the sub-data bit (SDB) generated during the scanning is written into the first bit position of the register bank (1401), the sub-data bits (SDB) contained in the register bank (1401) are divided into bit groups (DB) by n-bit positions, Binary values of at least one matching bit position within at least two bit groups (DB) are checked for agreement with one another in a comparison, the sampling phase (APH) is determined depending on the result of the comparison. Method according to Claim 1, characterized in that the bit pattern is an LHLH bit sequence or an HLHL bit sequence. Method according to Claim 1 or 2, characterized in that n = 9 for oversampling. Method according to one of the preceding claims, characterized in that when comparing the binary values, matching bit positions of four successive bit groups (DB) are used. Method according to one of the preceding claims, characterized in that the binary values are subjected to a logical AND operation for comparison, the binary values being alternately negated in successive bit groups (DB). Method according to one of the preceding claims, characterized in that the middle bit position (4th bit position) of each bit group (DB) is used as the corresponding bit position. Method according to Claim 6, characterized in that the binary values of the two bit positions (3rd and 5th bit position) of the bit groups (DB) adjacent to the middle bit position are subjected to a second AND operation and that the sampling phase (APH) depends on the result of the first AND link and the second AND link is set. Method according to Claim 7, characterized in that the binary values of the bit positions (2nd and 6th bit position) of the bit groups (DB) adjoining the adjacent bit positions are subjected to a third AND operation and that the sampling phase (APH) depends on the result of the first AND link, the second AND link and the third AND link is determined. Method according to one of the preceding claims, characterized in that the number of matching non-negated binary values and negated binary values per clock pulse (TSI) is determined, that the number of clock pulses (TSI) for which the number remains the same is determined, and that the sampling phase (APH) depending on this number. A method according to claim 9, characterized in that the sampling phase (APH) is set so that it substantially coincides with the clock pulse which is defined by half the number. Method according to one of the preceding claims, characterized in that it is used for cordless telecommunication devices which operate according to the DECT standard. Device for carrying out the method for determining a sampling phase according to one of the preceding claims, with a sampling device which samples a digital data stream (DS) containing a predetermined bit pattern with a fixed data rate per digital value according to an oversampling n times, a register bank (1401), which serially temporarily stores the sub-data bit sequence (SDBF) that arises during the scanning, with each scanning in accordance with a clock pulse (TSI) shifting the stored sub-data bits in the register bank by one bit position and the sub-data bit (SDB) generated during the scanning in the first bit position of the register bank (1401) is written, the sub-data bits (SDB) contained in the register bank (1401) being subdivided into bit groups (DB) of n-bit positions, characterized by a logic circuit, the binary values of at least one matching bit position within at least two Bit groups (DB) linked to one another and checked for agreement in a comparison, the sampling phase (APH) being determined as a function of the result of the comparison. Device according to claim 12, characterized in that the bit pattern is an LHLH bit sequence or an HLHL bit sequence. Device according to claim 12 or 13, characterized in that for comparison the binary values are subjected to a logical AND operation, the binary values of successive bit groups (DB) being negated alternately. Device according to one of the preceding claims, characterized in that the middle bit position (4th bit position) of each bit group (DB) is used as the corresponding bit position. Device according to claim 15, characterized in that the binary values of the two bit positions of the bit groups (DB) adjacent to the middle bit position are subjected to a second AND operation, and that the sampling phase (APH) depends on the result of the first AND operation and the second AND - Link is set. Device according to Claim 16, characterized in that the binary values of the bit positions of the bit groups adjacent to the adjacent bit positions are subjected to a third AND operation, and that the sampling phase (APH) depends on the result of the first AND operation, the second AND operation and the third AND link is determined. Device according to one of the preceding claims, characterized in that the number of matching non-negated binary values and negated binary values per clock pulse (TSI) is determined, that the number of clock pulses for which the number remains the same is determined, and that the sampling phase (APH) depending on this number. Device according to claim 18, characterized in that the sampling phase (APH) is set so that it essentially coincides with the clock pulse which is defined by the half number.

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