DD289678A7 - 16-BIT MICROPROCESSOR SYSTEM - Google Patents

Abstract

The invention relates to a 16-bit microprocessor system. The present 16-bit microprocessor system finds application in 16-bit microprocessor devices and computers. The 16-bit microprocessor system with a matrix integrator of the data path performs byte and word operations on the 8-bit and 16-bit input-output devices and memory modules. The data link control integrator circuit allows the 8-bit and 16-bit input-output devices and memory modules to be connected to the common 16-bit information bus of the microprocessor system and protects the operating system memory from stacking in dependence upon the memory modules. This is done by means of identification signals, controlled by the 16-bit microprocessor, the 8-bit and 16-bit input-output devices and the memory modules. The data link control integrator recognizes these signals and controls the system information commutator. The advantages of the described 16-bit microprocessor system is that the 8-bit and 16-bit input-output devices and memory modules can be connected to the common 16-bit information bar of the microprocessor system. The 16-bit microprocessor performs byte and word operations on all input-output devices and memory modules, regardless of their real number of digits, and the operating system memory is not stripped of the number of digits of memory modules. {16-bit microprocessor system; Matrix integrating circuit; Memory modules; System memory; Identification signal; 16-bit input-output devices; data path; System Informationskommutator}

Description

16-bit MicroprozessorsyQtems. The data inputs and outputs of the matrix integrating circuit for controlling the data path are connected to the primary data path of the 16-bit microprocessor, while their return control input, control clock input and their control input for introducing an additional wait state are in communication with the corresponding corresponding outputs of the clock generator , The address inputs for defining the transmission type and the inputs for defining the operation type of the matrix integrating circuit are connected to the corresponding corresponding outputs of the 1-bit micro-processor. The control input for the subordinate device type, the control input for disposition of the subordinate 8-bit device, the control input for asserting the address in direct access, and the control output for selecting the input-output storage region of the circuit are control inputs and outputs of the IS-bit microprocessor system. The control output for cycle address storage (registration) of the circuit is connected to the corresponding input of the address register. The primary data path direct commutation control output, the primary data path return commutation control output, the secondary data path direct commutation control output, and the secondary commutation return output control output are in communication with the corresponding system data commutator inputs. The address memory control input and the modified type of operation circuit defining outputs are connected to the corresponding output and inputs of the bus controller, and their transmission type system address outputs are 16-bit microprocessor system outputs. The wait clock input is connected to the first input of the connector, the second input of which is connected to the control output for insertion of additional clocks of the clock generator, while its output is connected to the input for system wait times of the 16-Rit microprocessor , The matrix integrating circuit for data path control includes a word transmission condition detecting unit, a microprocessor state monitoring unit, a wait clock introduction unit, a buffer register control unit, a buffer register, a microprocessor type detecting unit, a control unit of the microprocessor System commutator, a control unit of the system address outputs for the transmission type, an unit for modifying the operation and a unit for selecting the input-output memory area. The word transfer condition output of the word exchange condition detecting unit is connected to the corresponding input of the microprocessor state monitoring unit, the cycle address storing output thereof to the corresponding inputs of the control unit of the system address outputs for the transmission type and the word transfer condition detecting unit is a control output of the matrix integrating circuit for controlling the data path; the wait start state output and the wait state output are in communication with the corresponding inputs of the wait clock import unit. The hidden transmission cycle start output is connected to the corresponding input of the control unit of the system address outputs for the transmission type; the output for the operation modification is in communication with the corresponding input of the unit for operation modification, the output for enabling the turning on of the buffer register is connected to the corresponding input of the control unit of the buffer register; the subordinate device type output is in communication with the corresponding input of the system commutator control unit and is a control input of the matrix integrating circuit for data path control; the output for the enable of the buffer register is connected to the corresponding input of the control unit of the buffer register; the hidden cycle end output is in communication with the corresponding inputs of the word transfer condition recognizing unit and the control unit of the system address outputs for the transfer type; the address storage input is connected to the corresponding input of the microprocessor type detection unit and is a control input of the matrix integrating circuit for controlling the data path; the reset input is in communication with the corresponding inputs of the word transfer condition detecting unit, the wait clock introduction unit, the control unit of the transfer type system address outputs, and the input-output storage area selection unit, and is a control input of the matrix Integrating circuit for controlling the data path. The control clock input is connected to the corresponding inputs of the control unit of the system address outputs for the transmission type and to the control unit of the buffer register and is a control input of the matrix integrating circuit for controlling the data path. The output for introducing waiting cycles of the unit for introducing wait files, the output for the selection of the input-output storage area of the unit for the selection of the input-output area from the memory, the output for the direct commutation of the primary data paths, the output for the primary commutation back commutation, the secondary commutation direct commutation output, and the secondary commutation output commutation output of the system commutator control unit, the matrix integrator data control outputs are control outputs. The output for turning on the buffer register and the output for loading the buffer register of the control unit of the buffer register are connected to the corresponding inputs of the buffer register. The inputs for controlling the transmission of the input-output memory selection unit, the operation-type-defining inputs to the operation-modification unit, the input for disposition of the sub-8-bit device of the system commutator controller, and the input for introducing additional wait symbols of the unit for monitoring the microprocessor state are control inputs of the matrix integrating circuit for controlling the data path. The input for determining the transmission direction from the control inputs of the transfer of the matrix integrating circuit for controlling the data path is a control input of the control unit of the buffer register. The transmission start output of the operation modification unit is connected to the corresponding input of the word transmission condition detection unit. The output for displaying the 16-bit micro-processor of the microprocessor-type detection unit is in communication with the corresponding inputs of the buffer register control unit and the system commutator control unit. The information (data) inputs and the information (data) outputs of the buffer register are data inputs and data outputs of the matrix integrating circuit for controlling the data path. The outputs for defining the modified mode of operation of the unit for operation modification are in communication with the corresponding inputs of the unit for selecting the input-output storage area and are control outputs of the matrix integrating circuit for controlling the data path. The address inputs to define the

The transmission type of the word transmission condition detection unit is connected to the corresponding inputs of the microprocessor type detection unit and the control unit of the system address outputs for the transmission type and are inputs of the matrix integrating circuit for controlling the data path. The input for enabling the address in case of direct access of the control unit of the system commutator is connected to the corresponding input of the input-output memory area selection unit and is a control input of the matrix integrating circuit for controlling the data path. The system address outputs for the transmission type of the control unit of the system address outputs for the transmission type are connected to the corresponding inputs of the control unit do a system grain torque and are address outputs of the matrix integrating circuit for controlling the data path. The advantage of the invention is that the data path of the 16-bit Microprozessorsy stems for the 8-bit and 16-bit subordinate Vprrichtungen is common, and that in a direct access of the operating memory in dependence on the number of digits of its modules not is stripped.

Another advantage of the invention is that the matrix integrator does not participate in the direct access control; this simplifies the microprocessor system.

Another advantage is that the 8-bit input-output devices and the memory modules can be connected to the primary or secondary system information rail (data path); this leads to the increase (increase) of the functional possibilities of the microprocessor system.

Ausführungsbelsplele

The invention will be explained in more detail with reference to an exemplary embodiment of the 8-bit microprocessor system according to the invention, illustrated in the accompanying figures. Show it

Fig. 1 is a block diagram of the 16-bit microprocessor system with a matrix integrating circuit for controlling the

Data path; Fig. 2 is a block diagram of the matrix integrating circuit for controlling the information path.

A 16-bit microprocessor system having a matrix integrating circuit for controlling the data path includes according to the invention a clock generator 1, a 16-bit microprocessor 2, a matrix integrating circuit 3 for controlling the data path, a system data commutator 4, a bus controller 5 and an address register 6. The reset control output 7 of the clock generator 1 is in communication with the corresponding inputs of the 16-bit microprocessor 2 and the bus controller 5. The control clock output 8 of the clock generator 1 is connected to the corresponding input of the 16-bit microprocessor. Microprocessor 2 connected to the address outputs 9, the data inputs of the address register 6 are connected. The primary data path 10 and the secondary data path 11 are in communication with the corresponding inputs of the system data commutator 4. The information outputs of the address register 6, the control outputs of the transmission 12 of the bus controller 5 and the primary system data path 13 and the secondary data path 14 of the Syriern data commutator 4 are accordingly a address rail 15, the control outputs of the transmission and sine primary and secondary information rail (data path) of the 16-bit microprocessor system. The data inputs and outputs 16 of the matrix integrating circuit for controlling the data path 3 are in communication with the primary information bus 10 of the 16-bit microprocessor 2, its reset control input 7, its control clock input 8 and its control input 17 for the introduction of additional waiting clock are in Connection to the corresponding corresponding outputs of the clock generator 1. Their address inputs for the definition of the transmission type 18 and their inputs for the definition of the operation type 19 are connected to the corresponding corresponding outputs of the 16-bit microprocessor 2. Its control input for the type of slave device 20, its control input for the disposition of the subordinate 8-bit device 21, its control input 22 for the release of the address in a direct access and its control output 23 for the selection of the input-output memory area Control inputs and outputs of the 16-bit microprocessor system. Its control output 24 for the cycle address storage is connected to the corresponding input of the address register 6. Its control output 25 for the direct commutation of the primary data paths, their control output 26 for the primary data paths, their control output 26 for the primary data paths, their control output 27 for the direct commutation of the secondary data paths and their control output 28 for the secondary commutation Data paths are associated with the corresponding inputs of the system data commutator 4. Its address memory control input 29 and its modified operation type definition outputs 30 are connected to the corresponding output and inputs of the bus controller 5, and their system address outputs 31 for the transmission type are outputs of the 16-bit microprocessor system. The output for introducing wait bits 32 of the matrix integrator circuit is connected to the first input of a connector 33 whose second input is connected to the control output 17 for introducing additional wait clocks of the clock generator 1, while its output is connected to the system input input 34 -Wartetakten the 16-bit Microprocessor 2 is in communication.

The matrix integrating circuit 3 for controlling the data path includes a unit for detecting the data

Word transfer condition, a state machine of the microprocessor, a wait-file introduction unit 37, a buffer register control unit 38, a buffer register 39, a microprocessor-type recognition unit 40, a system controller 41, a control unit of system address outputs for the transmission type 42, a unit 43 for modifying the operation and a unit 44 for selecting the input-output storage area. The word transmission condition output output 45 of the word transmission condition detection unit 35 is connected to the corresponding input of the microprocessor state monitoring unit 36, the output of which stores the cycle address 24 with the corresponding inputs of the system control unit 42 Address outputs for the transmission type and the word transmission condition detection unit 35 is communicated, it is a control output of the matrix integrating circuit for controlling the word transfer condition

Data path, the start-of-wait output 46 and the wait-out output 47 are connected to the corresponding inputs of the wait clock introduction unit 37; the hidden transmission cycle start output 48 is in communication with the corresponding input of the system address control output control unit; the operation modification output 49 is connected to the corresponding input of the operation modification unit 43, the buffer register enabling output 50 is connected to the corresponding input of the buffer register control unit 38, the subordinate device type input 20 is connected to the corresponding input of the control unit 41 of the system commutator and is a control input of the matrix integrating circuit for controlling the data path, the buffer register enabling output 51 is in communication with the corresponding input of the buffer register control unit 38, the output 52 for the end of the hidden cycle is connected to the corresponding inputs of the word transfer condition recognizing unit 35 and the control unit 42 of the transfer type system address outputs; the address storage input 29 is in communication with the corresponding input of the microprocessor type detection unit 42, and is a control input of the matrix integrating circuit for controlling the data path. The reset control input 7 is in communication with the corresponding inputs of the word transfer condition detecting unit 35, the wait-file input unit 37, the transmission-type system address outputs control unit 42, and the input-output storage region selection unit 44 and represents a control input of the matrix integrating circuit for controlling the data path. The control clock input 8 is connected to the corresponding inputs of the control unit 42 of the system address outputs for the transmission type and the control unit 38 of the buffer register and is a control input of the matrix integrating circuit 3 for control of the data path. The wait-queue-out output 32 of the wait-taker-introducing unit 37, the input-output-memory-selection output 23 of the input-output-storage-input selection unit 44, the primary data-path direct-connect output 25 The primary data path return commutation output 26, the secondary data path direct commutation output 27, and the secondary commutation return commutation output 28 of the system commutator controller 41 are control outputs of the matrix integrating circuit for controlling the data path. The buffer register turn-on output 53 and the buffer register load-out output 54 of the control unit 38 of the buffer register are in communication with the corresponding inputs of the buffer register 39. The control inputs 12 of the input-output memory region selection unit 44 are transferred , the inputs for defining the operation type of the operation modification unit 43, the input 8 for the disposition of the subordinate 8-bit device of the control commander 41 of the system commutator, and the input 17 for introducing additional wait clocks of the unit 36 for Supervision of the idicroprocessor state are control inputs of the matrix integrating circuit 3 for controlling the data path. The input 55 for determining the direction of transmission from the control inputs, ie, exchange control inputs 12 of the matrix integrating circuit 3 for controlling the data path, is a control input of the control unit 38 of the buffer register. The transfer start output 56 of the operation modification unit 43 is in communication with the corresponding input of the word transfer condition recognizing unit 35. The 16-bit microprocessor display output 57 of the microprocessor-type detection unit 40 is connected to the corresponding inputs of the buffer register control unit 38 and the system commutator control unit 41. The information inputs and the information outputs of the buffer register 39 are information inputs and information outputs 16 of the matrix integrating circuit 3 for controlling the data path. The modified operation type defining outputs 30 of the operation modifying unit 43 are connected to the corresponding inputs of the input-output storage area selecting unit 44, and are control outputs of the matrix integrating circuit 3 for controlling the data path. The address inputs 18 for defining the transmission type of the word transmission condition detecting unit 35 are in communication with the corresponding inputs of the microprocessor type detecting unit 40 and the control unit 42 of the system address outputs for the transmission type and are inputs of the matrix integrating circuit 3 Control of Information Rail (Data Path). The input-address-responsive input terminal 22 of the system commutator control unit 41 is connected to the corresponding input of the input-output storage-area selecting unit ^ A , and is a control input of the matrix integrating circuit 3 for data-path control. The system address outputs 31 for the transmission type of the control unit 42 of the system address outputs for the transmission type are in connection with the corresponding inputs of the control unit 41 of the system commutator i'nri «ind address outputs of the matrix Intogrierschaltung 3 for controlling the data path.

The operation of the 16-bit microprocessor system having a matrix integrating circuit for controlling the data path is as follows. At the beginning of each transfer cycle, the 16-bit microprocessor 2 activates via the channel its transmission-type definition outputs 19 which are repeated by the data-path control unit modification operation unit 43 in FIG it activates its outputs 30 to define the modified operation type and its output transmission output 66. The bus controller 5 recognizes the operation type and activates its output 29 for address storage. Only when the state at the modified operation type 30 outputs 30 indicates that the replacement with the input-output storage area will occur, the input-output storage area selection unit 44 activates its input-output selection output terminal -Speicherbereichs. At the beginning of each transmission cycle, the microprocessor state monitoring unit 36 repeats the state of its address memory input 29 in controlling its output 24 in storing the cycle address. During its active state, the 16-bit microprocessor 2 activates its address outputs 9 and its address outputs 18 to define the type of transmission. The word transfer condition detecting unit 35 and the microprocessor type detecting unit 40 of the data link control matrix integrating circuit 3 monitor the state of their address inputs 18 to define the transfer type. After a time interval equal to their reset duration, the outputs 9 and the address outputs 18 for defining the transmission cycle of the 16-bit microprocessor 2 are stored in the address register 6 and in the control unit 42 of the system address outputs for the transmission type of the matrix integrator circuit 3, respectively the bus controller 5 deactivates its output 29 for address storage, and the unit 36 for monitoring the state of

Microprocessor inactivates its output 24 to store the cycle address. At the beginning of the first transmission cycle over the channel, after the clock generator 1 has disabled its reset output 7, the microprocessor-type detection unit 40 determines the digit number of the microprocessor depending on the state of the address inputs 18 to define the type of transfer of the matrix integrator 3 Control of the data path. In a 16-bit microprocessor, the microprocessor-type detection unit 40 activates its output 57 to display the 16-bit microprocessor when the bus controller 5 deactivates its address memory output 29, the output remaining active during the entire operating time of the 16-bit microprocessor. Bit microprocessor system is maintained. In an 8-bit microprocessor, the microprocessor-type detection unit 40 does not assert its output to the display 57 of the 16-bit microprocessor, the buffer register control unit 38 does not operate, and the system commutator control unit 41 asserts its output 27 for the microprocessor direct commutation of the secondary data paths and their output 26 for the backbone mutation of the secondary data paths not. At the beginning of the second cycle of the transmission cycle, the bus controller 5 activates its outputs 12 for exchange control over the channel. For a 16-bit microprocessor, at the beginning of the word exchange cycle over the channel (the address of the cell from the slave device is even), the word transfer condition recognizing unit 35 will output its word transfer condition output 45 if the unit 36 is for monitoring the state of the microprocessor disables its output 24 to store the cycle adder. When the information exchange with an 8-bit subordinate device connected to the primary system data path 13 takes place, it does not activate its input 8 for the subordinate 8-bit device disposition and the subordinate device input 20 of the matrix device. Integrating circuit 3 for controlling the data path. During the second cycle of the replacement cycle, the system commutator controller 41 activates its channel 25 output for just commutation of the primary data paths, the system data commutator 4 connects the primary data path 10 to the primary system data path 13, and the unit 36 for monitoring the state of the microprocessor activates its output 46 for the beginning of the waiting period. At the end of the replacement cycle's two-tone clock, the wait-for-clock introduction unit 37 activates its wait-clock-in output 32 by the connector 33 activating its system-wait-clock-out output 34 and the exchange cycle at the end of the third clock the channel sets the 16-bit microprocessor 2 in a wait state for a time interval equal to the cycle duration. When the slave device is operating slowly, the clock generator 1 activates its output 17 to introduce additional wait clocks before activating the wait clock 32 output 32, and sets the microprocessor state monitoring unit 36 to a wait state after the end the third clock of the exchange cycle. After a time interval equal to the time of access to the slave device, the clock generator 1 inactivates the output 17 for introducing additional wait clocks, and at the beginning of the last additional wait clock of the le-bit microprocessor 2, the microprocessor state monitoring unit 36 activates the output 49 for the operation modification. The Oparationsmodification unit 43 modifies the operation-type definition inputs 19 of the data-path control matrix integrating circuit 3 by inactivating its outputs 30 to define the modified operation type. At the end of the last additional wait clock, the microprocessor state monitor unit 36 activates its buffer register enable output 51 so that the buffer register controller 38 activates the buffer register load output 54 and stores the buffer register 39 the state of the information inputs and outputs 16 of the matrix integrating circuit 3 for controlling the data path. At the beginning of the first wait clock, the bus controller 5 inactivates its outputs 12 for the exchange control, and the system commutator 41 deactivates the input 25 for direct commutation of the primary data paths. When the exchange with the input-output storage area takes place, the input-output storage area selection unit 44 inactivates the input-output storage area selection input 23. At the end of the first value clock, the microprocessor status monitoring unit 36 activates the hidden transmission start point output 48 and disables the operation modification output 49. The transmission type system address output control unit 42 modifies the system address outputs 31 for the transmission type, and the operation modification unit activates its outputs 30 to define the modified operation type.

During the second wait clock, the bus controller 5 begins the hidden exchange cycle over the channel by re-enabling its output 29 for address storage. The microprocessor state monitoring unit 36 does not repeat its state and does not assert its cycle address storing output 24, while the input-output memory region selection unit 44, when transmitting with the input-output memory area is activated, the output 23 for the selection of the input-output memory area. At the beginning of the third wait cycle, the bus controller 5 activates its outputs 12 for the exchange control and also its output 55 for determining the direction of transmission. The microprocessor state monitor unit 36 asserts its buffer register enable output 50. When the read operation is performed, the buffer register control unit 38 activates its output 53 to turn on the buffer register 39, and the buffer register 39 transfers the recorded byte to the microprocessor by activating the information outputs 16 of the data link control matrix integrator circuit 3. When the record (write) operation is performed, the buffer register 39 control unit 38 does not assert its output 53 to turn on the buffer register 39, and the buffer register does not send the data already recorded to the microprocessor. The system commutator controller 41 activates its secondary data path return commutation control 28 and the system information commutator 4 connects the primary data path 10 to the secondary system data path 14. At the end of the third and fourth wait clocks, the unit 36 activates monitoring of the state of the microprocessor outputs the exit 47 for the wait 47, and the unit 37 for introducing wait files deactivates its output 32 for introducing wait files. When the slave device is operating slowly, the clock generator 1 activates its output 17 for the introduction of additional wait clocks and sets the microprocessor state monitoring unit 36 to a wait state after the end of the fourth wait cycle and the output of the connector 33 , d. H. the system-waiting clock 34 output is actively maintained by the connector 33. After a time interval equal to the access time to the slave device, the clock generator 1 inactivates its output 17 for the introduction of additional wait clocks 17, and the connection element 33

disables its output 34 for the introduction of system wait files. At the beginning of the last additional wait clock, the 16-bit microprocessor 2 inactivates its outputs 19 to define the operation type and the unit for operation modification 43 inactivates its outputs 30 to define the modified operation type. At the beginning of the last cycle of the replacement cycle, the bus controller 5 inactivates via the channel its outputs 12 for the exchange control. The system commutator control unit 41 inactivates the secondary data path return-commutation output 28, and the input-output storage area selection unit 44 inactivates its output for selecting the input-output area of the memory when transmitting with the input-output area from the store. At the end of the last cycle of the exchange cycle, the microprocessor state monitoring unit 36 activates the hidden transmission cycle termination output 52, in which the word transfer condition detection unit 3d outputs its condition indicating output 45 a word transfer is inactivated, and the transmission type system address outputs control unit 42 returns the system address outputs 31 for the transmission type to the initial state. As a result of the described algorithm, the 16-bit microprocessor 2 for the 8-bit sub-devices is an 8-bit microprocessor, and the 8-bit sub-devices are 16-bit subordinate devices for the 16-bit microprocessor. This allows the 16-bit microprocessor to exchange words with the 8-bit subordinate devices.

When the 8-bit subordinate device with which the 16-bit microprocessor 2 is exchanging words is connected to the secondary system information rail 14, it activates the input for disposition of the 8-bit subordinate device 21 of the matrix system. Integrating circuit 3 for controlling the data path, in which all of their units operate in the manner described. The system commutator control unit 41 sequentially activates its primary data path back-commutation output 26 and its secondary data path direct commutation output 27, in which the system information commutator 4 includes the primary information bus 10 with the secondary system information bus 14 and the secondary information bus 11 connects sequentially to the secondary system information rail 14.

When the 16-bit microprocessor 2 performs a byte exchange, the monitoring unit 36 repeats the state of the microprocessor, the state of its address memory 29 input 29, and activates its cycle address storage output 24. The transmission type system address outputs control unit 42 stores the address inputs 18 for defining the transmission type, and activates the transfer type address outputs 31 of the matrix integrating circuit 3 to control the data path. In an 8-bit subordinate device connected to the primary system information bus 13, the system commutator controller 41 activates the output 25 for direct commutation of the primary information paths, if the address is an even one, or its output 28 for the return commutation secondary data paths if the address is an odd one. In an 8-bit subordinate device connected to the secondary system information bus 14, the system commutator controller 41 activates its output 26 for primary information path back-commutation if the address is a straight one or its output 27 for direct secondary commutation Data paths if the address is an odd one. The unit 44 for selecting the one-yy output range from memory operates as already described. The other units of the matrix integrating circuit 3 by controlling the data path do not work. When the 16-bit microprocessor 2 exchanges data with a 16-bit subordinate device, it activates the subordinate device type input input 20 of the matrix integrating circuit 3 to control the data path which functions as in the byte exchange however, the system commutator controller 41 activates its output 25 for direct commutation of the primary data paths in a straight-address byte exchange, or its output 27 for direct commutation of the secondary data paths in an odd-byte byte exchange, or its output 25 for a straight commutation of the primary data paths and its output 27 for a direct commutation of the secondary data paths in a word transmission.

The matrix integrating circuit 3 for controlling the data path allows the replacement of the 16-bit microprocessor 2 by an 8-bit microprocessor, without thereby changing the number of digits of the microprocessor system. The system commutator controller 41 activates its output 25 for a straight commutation of the primary data paths when exchanged with a subordinate 8-bit device connected to the primary system information bus 13 and when exchanging a even address with a subordinate 16-bit device. Device or its output for a return commutation of the primary data paths 26 when exchanged with a subordinate 8-bit device, connected to the secondary system information rail 14 and an exchange of an odd address with a subordinate 16-bit device. The further units of the matrix integration circuit 3 for controlling the data path function as in the described byte exchange (byte transfer). In this case, the slave devices perceive the 8-bit microprocessor as a 16-bit microprocessor.

In direct access, the direct access address enable input 22 is activated, in which the system commutator control unit 41 and the input / output range selection unit 44 set their outputs to an inactive state.

Claims (3)

A 16-bit microprocessor system including a clock generator, a 16-bit microprocessor, a system data commutator, a bus controller and an address register, wherein the reset control output of the clock generator is connected to the corresponding inputs of the 16-bit microprocessor. Microprocessor and the bus controller is connected, the control clock output of the clock generator is connected to the corresponding input of the 16-bit microprocessor whose address outputs are connected to the information inputs of the address register, the primary information rail and the secondary information rail with the corresponding inputs of the system Data commutator, while the address register data outputs, the bus controller output control outputs, and the system data commutator primary system information rail and system information bus secondary rails correspond to address rail outputs for ex transmission control and a primary and a secondary information rail of the 16-bit microprocessor system, characterized in that it also includes a matrix integrating circuit (3) for controlling the data path, the information input outputs (16) to the primary information rail (10) of the le bit microprocessor (2), the reset control input (7), the control clock input (8) and the control input for introducing additional wait clocks (17) to the corresponding outputs of the clock generator (1) are in communication, the address inputs (18) for defining the type of transmission and the inputs (19) for defining the type of operation to the corresponding corresponding outputs of the 16-bit microprocessor (2) are connected, that the control input (20) for the type of subordinate device, the control input (20 21) for the disposition of the subordinate 8-bit device, the control input (22) for release of the address Direct access and control output (23) for selecting the input-output area from the memory. Control inputs and outputs of the 16-bit microprocessor system are connected to the control output (24) for storing the cycle address to the corresponding input (6) of the address register in that the control output (25) is for a direct commutation of the primary data paths, the control output (26) for the re-commutation of the primary data paths, the control output (27) for a direct commutation of the secondary data paths and the control output (28) for a re-commutation of the secondary Data paths are connected to the corresponding inputs of the system data commutator (4), that the control input (29) for the address storage and the outputs (30) for defining the modified type of operation with the corresponding output and the inputs of the bus controller ( 5) that the system address outputs (31) for the Transmission type outputs of the 16-bit microprocessor system are that the output (32) for the introduction of wait files with the first input of a connecting element (33) is in communication, and that its second input to the control output (17) for introducing additional wait of the clock Clock generator (1) is connected, while the output of which is connected to the input (34) for introducing system waiting clocks of the 16-bit microprocessor (2). 2. 16-bit microprocessor system according to claim 1, characterized in that the matrix integrating circuit (3) for controlling the data path, a unit (35) for detecting the word transmission condition, a unit (36) for monitoring the state of the microprocessor, a Wait-file introduction unit (37), a buffer register control unit (38), a buffer register (39), a microprocessor-type detection unit (40), a system commutator control unit (41), a control unit (38) 42) of the system address outputs for the transmission type, an operation modification unit (43) and a memory input / output area selection unit (44), wherein the output (45) indicates the word transmission condition of the unit ( 35) for detecting the word transmission condition with the corresponding input of the unit (36) for monitoring the state of the microprocessor in connection st eht whose output (24) for storing the cycle address to the corresponding inputs of the control unit (42) of the system address outputs for the transmission type and the unit (35) for detecting the word transmission condition connected and a control output of the matrix integrating circuit (3) for controlling the Data path, and that the output (46) for the start of waiting and the output (47) for waiting with the corresponding inputs of the unit (37) for Introducing wait clocks, the output (48) for the beginning of the hidden transfer cycle is connected to the corresponding input of the control unit (42) of the system address outputs for the transmission type, the output (49) for operation modification with the corresponding input of the unit (43) is connected for operation modification that the output (50) for activating the turning on of the buffer register with the corresponding input of the control unit (38) of the buffer register is in communication that the input 0'O) for the type of subordinate device with is the corresponding input of the control unit (41) of the system commutator in communication, and a control input of the matrix integrating circuit (3) for controlling the data path is that the output (51) for effecting the loading of the buffer register to the corresponding input of the control unit ( 38) of the buffer register That is, the hidden cycle end output (52) is in communication with the corresponding inputs of the word transfer condition detection unit (35) and the system address output control unit (42) of the transfer type the input (29) for address storage is connected to the corresponding input of the microprocessor type detecting unit, and a control input of the matrix integrating circuit (3) for controlling the data path is that the reset control input (7) is connected to the corresponding inputs of Unit (35) for detecting the word transmission condition, the unit (37) for introducing wait files of the control unit (42) of the system address outputs for the transmission type and the unit (44) for selecting the input-output area from the memory and a control input the matrix integrating circuit (3) for controlling the information rail is that the control clock input (8) is connected to the corresponding inputs of the control-type system address outputs (42) and the buffer register control unit (38), and is a control input of the matrix integrating circuit (3) for controlling the data path (3) the output (32) for introducing wait cycles of the unit (37) for introducing wait cycles, the output (23) for the selection of the input-output area from the memory of the unit (44) iü. the selection of the input-output area from the memory, the output (25) for a direct commutation of the primary data paths, the output (26) for a return commutation of the primary data paths, the output (27) for a direct commutation of the secondary data paths and the output ( 28) for a return commutation of the secondary data paths of the control unit (41) of the system commutator. Control outputs of the matrix integrating circuit (3) for the control of the data path are that the output of the buffer transistor (53) and the output (54) the charging of the buffer register of the control unit (38) of the buffer register is connected to the corresponding inputs of the buffer register (39), the control inputs (12) of the transfer of the unit (44) for the selection of the input-output area from the memory, the outputs (19) for defining the operation type of the unit (43) for operation modification, the input (21) for the disposition of the subordinate one 8-bit device of the control unit (41) of the system commutator and the input (17) for introducing additional waiting clocks of the unit (36) for monitoring the microprocessor are control inputs of the matrix integrating circuit (3) for the control of the data path in that the input (55) for determining the direction of transmission from the inputs (12) of the transfer controller of the data integration matrix integrating circuit (3) is a control input of the control unit (38) of the buffer register, the output (56) being for the Transfer start of the unit (43) for operation modification with the corresponding input of the unit (35) for the word transfer condition is connected, that the output (57) for the display of a 16-bit microprocessor of the unit (40) for the detection of the microprocessor type with the corresponding inputs of the control unit (38) of the buffer register and the control unit (41) of the system commutator in that the information inputs and information outputs of the buffer register (39) are information inputs and outputs (16) of the matrix integrating circuit (3) for controlling the data path, the outputs (30) for defining the modified type of operation of the unit for Operation modification to the corresponding inputs of the unit (44) for the selection of the input-output area from the memory connected and control outputs of the matrix integrating circuit (3) for controlling the data path are that the address inputs (18) for the definition of the transmission type of the unit (35 ) for the recognition of the word transfer condition with the corresponding inputs of the unit for recognition of the microprocessor type (40) and the control unit of the system address outputs for Transmission type (42) connected and inputs of the matrix integrating circuit (3) for the control of the data path are that the input (22) for the release of the address in a direct access of the control unit (41) of the system commutator to the corresponding input of Unit (44) for selecting the input-output area from the memory connected and a control input of the matrix integrating circuit (3) for the control of the data path, and that the system address outputs (31) for the transmission type of the control unit (42) of the system Address outputs for the transmission type are connected to the corresponding inputs of the control unit (41) of the system commutator and are address outputs of the matrix integrating circuit (3) for the control of the data path. For this 2 pages drawings Field of application of the invention The invention relates to a 16-bit microprocessor system having a matrix integrating circuit for controlling the information path (the data path) used in the Ιβ-bit microcomputers and information systems. Characteristic of the known state of the art It is a 16-bit (16-digit) microprocessor system with an integrating circuit for converting the signals of a 16-bit microprocessor bus to an 8-bit microprocessor bus (Integralnaja Scheme - Preobrarovatel Signalov 8-i 16-Rasrjadnich Prozessorov; 1985, No. 9, p. 33), which includes a matrix integrator circuit for converting the signals in which its 16-bit system information bus is connected to the corresponding inputs and outputs of a 16-bit microprocessor, a 16-bit memory and le-bit input-output devices, and their 8-bit system information path (system data path) is connected to the corresponding inputs and outputs of 8-bit memory and 8-bit input-output devices. There is a possibility that a subordinate 8-bit microprocessor will be connected to the matrix integrator circuit. The matrix integrator circuit looks like a 16-bit memory or as an input-output device for a 16-bit microprocessor, and for the 8-bit memory and the 8-bit input-output devices - such as an e-bit microprocessor. In a byte exchange (byte transfer) of the 16-bit microprocessor with the e-bit input-output devices and memory, the matrix integrator circuit transfers data from the 16-bit system data path to the 8-bit Sydtem data path and forms the necessary control and synchronization signals. In a word exchange of the 16-bit microprocessor with the 3-bit input-output devices and the 8-bit memory sets the matrix integrator circuit to put this microprocessor into a wait state and, via the 8-bit system data path, pass two consecutive byte exchanges with the subordinate 8-bit Device off. A disadvantage of the known 16-bit microprocessor system with an integrating circuit is that the system path is divided into two parts, 16-bit and 8-bit, so that the 8-bit and 16-bit input-output - Devices and memory can be connected. A further disadvantage is that, in the case of a direct access, the main memory of the microprocessor system is coated as a function of the number of positions of the memory modules, and the matrix integrating circuit takes part in its control, which complicates the microprocessor system. Object of the invention The aim of the invention is to avoid the aforementioned disadvantages. Explanation of the essence of the invention The invention has for its object to provide a 16-bit microprocessor system with an integrating circuit for controlling the data path, which is connected to a common 16-bit system data path of 8-bit and 16-bit input-output devices can be so that the main memory of the microprocessor system is not stripped in a direct access depending on the number of positions of its modules. This object has been achieved by a 16-bit microprocessor system having a matrix integrating circuit for controlling the data path, comprising a clock generator, a 16-bit microprocessor, an integrating circuit for controlling the data path (information rail), a system data commutator, a bus (Channel) controller and an address register contains. The reset control output of the clock generator is connected to the corresponding inputs of the 16-bit microprocessor and the bus controller. The clock output of the clock generator is in communication with the corresponding input of the le-bit micro-processor whose address outputs are connected to the data input (data) inputs of the address register. The primary data path and the secondary data path are in communication with the corresponding inputs of the system data commutator. The address register data outputs, the bus controller exchange control outputs, and the system system primary data path and the system data commutator secondary system data path are respectively an address path, outputs for exchange control, and a primary and a secondary data path