DE2217609A1 - Access unit for data processing systems - Google Patents

Description

Patent attorney

Dipl.-Phys. Leo Thul

Stuttgart 2217809

J.S.Page - 2

INTERNATIONAL STANDARD ELECTRIC CORPORATION, NEW YORK

Access unit for data processing systems

The invention relates to data processing systems with a main computer or central computer and with one or more Unterreohnern or decentralized computers.

In such data processing systems, one task is to transfer data (that is to include control information) between to be transmitted to the main computer and a sub-computer. This task arises from the fact that the sub-computer with relatively simple, repetitive tasks, while the main computer is busy controlling, organizing, analyzing and Distributing the information generated by the sub-computer is busy.

The task of the access unit according to the invention is the main computer, the occupancy of the sub-computer and a To enable access to its main memory as if it were an expansion of the memory of the main computer.

The access unit according to the invention comprises the following devices:

a) a first gate circuit that is assigned to a trunk group that connects the main computer with the access unit, this gate switching to the appearance of an address of said main memory on the assigned trunk group appeals,

April 11, 1972

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b) a switching means which responds when the first torso posture determines a memory address in order to make the next free access to the main memory available to the main computer do,

c) second gate circuits, which are set up so that the desired memory address from said trunk group via these second gate circuits are transferred to another trunk group with which this access unit and the sub-computer and its main memory are connected when the switching means is actuated lot, and

d) control means acting on a corresponding sign on the first Activate the trunk group depending on the direction of the data transmission, third or fourth gates, after which During a data transfer from or to the main computer, the sub-computer is denied access to its main memory is.

It should be noted that if there are more than two sub-computers, separate access units with mutual locking must be provided are.

The invention is explained below using an exemplary embodiment shown in the drawing.

Fig.l shows part of a data processing system multiple computers.

2 shows the affiliation of storage registers in the Storage arrangement.

In the system according to FIG. 1, one or more sub-computers, such as sub-computer 2, are assigned to a main computer 1, which can be of the same or a different type.

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Both computers according to Fig.l have access to the memory arrangement 3, which forms the main memory of the subcomputer 2. In this case, the main computer 1 accesses the main memory 3 tiller the access unit 4. The computers share access to the main memory 3 with other devices of various types Kind, such as the control unit 5 of a large storage facility. The unit 5 shares the access to the main memory with the computers by means of the control by the computer 2 and using the data cable bundle 6 to which they themselves, the sub-computer 2 and the access unit 4 are connected. The access unit 4 and the main computer 1 are on a another group of lines connected to each other.

If there are several sub-computers, each has its own main memory 3 and other units such as the control unit 5 can be connected to this. Each sub-computer also has its own access unit 4, which the Control data transmission between lines 7 to the main computer and lines 6 to the sub-computer. Also then are locking devices known per se required in order to avoid interference between different access units to prevent.

It can thus be seen that the access unit 4 is the trunk group 6 is used in the same way as the control unit 5 »This enables the main computer to access the main memory 3 of the sub-computer 2 bu received. During one of these Access is the main memory 3 is not available to the subordinate 2, but it is unlikely that a such access should last longer. Therefore, the access unit 4 has means to prevent the subscribers 2 from denying Change the content of the main memory 3 during a solphen access.

If data transmission between the main computer 1 and the main memory 3 is required, then the access

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unit 4 from the main computer 1 via the cable bundle 7 Address that points to the main memory 3. The access unit 4 then waits for the next one based on the system cycle free option for access to the main memory 3 to enable the data transfer. When the access unit 4 no address related to main memory 3 on the Trunk group 7 detects, then no access is attempted and no data transfer can be found between the trunk groups 6 and 7 instead.

The access unit 4 includes a gate circuit 8, which then emits an exit character when on the trunk group 7 from Host computer 1 receives an address pattern which belongs to one of the registers of the main memory 3. The exit character the gate circuit 8 turns on a bistable flip-flop 9, and this turn-on acts via the trunk group 6 on the Subcomputer 2, so that the next free access to the main memory 3 is directed to the register which is determined by the address pattern is marked on the trunk group 7. This selection is carried out in that the address pattern from the trunk group 7 via the one opened by the bistable flip-flop 9 Gate circuits 10 is transferred to the trunk group 6.

After selecting the desired register in the main memory, the data are either sent via the trunk group 6, the gate circuits 12 and the trunk group 7 to the main computer or from the Hauptreohner via the trunk group 7 # the gate circuits and transmit the trunk group 6. The direction of transmission is through the switching state of a torso posture 13 or a Torso posture 14 is determined, one of which is opened by a sign on a line of the bundle 7. From the access unit 4, a token is received on the trunk group when the closest free access is possible. This causes a gate switch 15, to enable the above-mentioned address transfer via the gate circuits 10, which enables the data transfer in

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follows the desired direction. It should be noted that the connections in Pig.l indicate that the gate circuit 15 of the bistable flip-flop 9 and depending on the possibility access to the memory is controlled. The output of the gate circuit 15 also acts via not shown Connections for resetting the flip-flop switch 9 * when the transmission is finished. When transferring data A register 16 is created from the main memory J5 to the main computer used in the access unit as a buffer memory.

To enable an access or a series of accesses without changes in the meantime by the Unterreohner can be carried out, another character is picked up via another torso posture 17 from the trunk group 7, the a bistable busy toggle circuit 18 turns on. This flip-flop 18 prevents the line bundle 6 that the subcomputer 2 receives access to its main memory J5 during an access sequence on the part of the main computer 1. The flip-flop 18 is of course reset at the end of such an access or at the end of an access sequence.

The allocation of the storage registers in the RAM 3 explained. In the main memory 3 there are a number of registers or register groups, some of which are registers IRO, IHl, -IRn of the transmission to the sub-computer system and some Register 0RO, 0Rl, ... 0Rn are assigned to the transmission from the sub-computer system. These registers are status registers SRO, SRI, ... SRn assigned, namely one binary memory location in each case the status register is a register used for the transfer or such a register group.

When the sub-computer 2 removes data supplied by the main computer 1 from the transfer register ITO, etc., it is complemented he the corresponding bit or bits in the assigned status register. Similarly, the sub-computer 2 complements the or

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the corresponding bit in the status register if the data for writes the main user 1 in one or more transfer registers 0RO, etc.

If the main computer has activated the access unit, then it can access the main memory 2 and determine that the status registers are switched. When the bit of the status register for the transfer register IRO, etc. is switched are, then the main computer 1 can new information for the sub-computer 2 in the transfer register IRO, etc. enroll.

Similarly, the main computer 1 can receive new information from the sub computer Read 2 out of the transfer register 0RO, etc., if the corresponding status register bits have been toggled.

As already indicated, the access unit 4 is only corresponding marked when the main computer 1 requests such access.

3 claims

2 sheets of drawings,

3 figures

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Claims (2)

Claims / ll) Data processing system rait a main computer and one or more, independently working sub-computers, each sub-computer being assigned a working memory to which the main computer needs access for the transfer of information between the main computer and the working memory of the subordinate, and with an access unit for the control of data transmission, characterized in that the access unit (4) has the following circuits: a) a first gate circuit (8) assigned to a trunk group (7) is that connects the main computer (l) with the access unit (4), this gate circuit '* (8) on the Appearance of an address of said main memory (3) on the assigned trunk group (7) responds, b) second gate postures (10) which are arranged so that the desired memory address from said trunk group (7) via these second portals (10) to another trunk group (6) are transmitted, with which this access unit (4) and the Unterreohner (2) together with its working memory (3) are connected when the switching means (9) is actuated, and d) control means (15) * which respond to a corresponding sign on the first trunk group depending on the direction of the Data transmission third (I3) or fourth gate circuits (14) press, after which during a data transfer from or to the main computer (1) the sub-computer (2) access to his RAM (3) is denied. 2.) Data processing system according to claim 1, characterized in that further control devices (5) share access to the main memory (3) with the main computer (1), which in turn also from access to the main memory (3) during an access from the main computer (1) ) are locked out. 209850 / 1Q3A J.S.Page - 2 j5.Data processing system according to claim 1 or 2, characterized in that with several sub-computers (2) and
corresponding to the number of access units (4), the access units are locked against each other in a manner known per se. 209850/1 0 3 Blank page