DD142135A3 - MORE COMPUTER COUPLING - Google Patents

Description

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a) iitel the invention multi-processor coupling

b) Field of application of the invention

The invention relates to a Mehrrechnerkopplungsaystem with multiple computer units, which are connected via a uniform for all computer units geataltetea coupling interface so that one arithmetic unit ala "master" computer and the other ala "slave" calculator function.

Such multi-computer systems are used to increase the processing power to a single computer, in particular in the application of microprocessors for various tasks, for example, to control loading and processing processes with real-time character.

c) Characteristics of the known technical solutions

It is known to couple several computing units in one system. In DE-OS 24 46 970 a plurality of independently operating computing units are connected via an interface unit with a common memory, wherein the ranking of the arithmetic units is determined in the memory access by a priority function.

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In this type of coupling, the data exchange always takes place via the shared memory,

Ea are still peripherieartige couplings known about special Anschlußateuerungen. After Du) -OS 26 45 341 iat each coupling path between two arithmetic units associated with a coupling arrangement. This can be implemented as a compact independent unit or assigned to each arithmetic unit to be coupled. In arrangements with more than two arithmetic units, multi-computer systems can be constructed in ring or star structures.

The disadvantage of such Mehrrechnersyateme is that separate coupler devices are necessary for each connection between two arithmetic units.

d) Object of the invention

The aim of the invention is to provide a Koppelachaltung for a .Mehrrechnersystem that achieves high performance with very low circuitry and design effort and at the same time ensures a cost-effective and easy-to-use structure with a high level of unification of the modules used.

e) Presentation of the Weaena of the invention

The invention is based on the object, as simple as possible in its construction coupling system for several simultaneous and autonomous working on an overall task active computing units, one of which as "master" - and the remaining are provided as "slave" -Recheneinheiten with associated, programmable input Ausgabetorschal-

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Achieves that anaynchrone communication of the individual arithmetic units via interrupt calls allowed.

According to the invention, this object is achieved by arranging each arithmetic unit via an input / output port to common data and address information buses, and by assigning each input / output port to a asynchronous bus for transmission of the tax rebate to a bus. Direct and conflict-free data exchange between the "master" computing unit and one of the "alave" computing units angachloaaen iat, and that the "maater" -Recheneinheit associated input ZAuagabetorachaltung ausweiat by one operable data direction aaa signal that with the other input ZAuagabetorachaltungen for Determination of the transmission direction and the priority of the "maater" -Recheneinheit connected iat. The input / output device of the "maater" processing unit is equipped with a priority priority device for a plurality of simultaneously requesting "alave" processing units.

The control circuit has a conjunctive linkage member for the data direction signal output from the "maater" instruction unit and received by the "alave" calculator units, and for ready in-band output signal, the output of which is unharmed with a timing characteristic to a second conjunctive link. The second input of the conjunctive gate having sign-on characteristics is connected to the read-in read-ready signal terminal and has an output connected to the outside by a third connection

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for the data direction signal for the "maater" computing unit and dea dea negation for the "alave" computing units on the in-voice command request inputs of the remaining arithmetic units and on a fourth gate connected at its other input to the second input of the second conjunctive link and connected to the terminal for the read-in temporary readiness signal, fed to the input / output request input of the input / output port associated with the connected arithmetic unit.

The control circuit has an activation input, via which it is called by its arithmetic unit via the associated input VAusgabetorachaltung for data exchange.

Each input VAuagabetorachaltung weiew a Zeitachaltung for determining the waiting time within which the transmitted / received by her / data word from the other, involved in data processing unit must be taken / sent, and a programmable, to be triggered by the requesting arithmetic unit timing error message not within a waiting time from the called computing unit arriving acknowledgment signal.

The "alave" calculation units are intended to control various process sections or other identical or different tasks. Their punctures are directed and coordinated by the "master" processing unit. A request for data transfer may be made by one of the "slave" units or by the "master" unit via the address and control lines which are switched to the buses via the input / output adder circuits.

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f) Auaführungbeiapiel

The invention aoll be explained in more detail below on a Auaführungabeiapiel. In the accompanying drawing show:

Pig. 1: daa Blockachaltbild for 4 coupled computing units

Fig. 2: Daa Blockachaltbild the over. Interconnections associated with input / output portals

Pig. 3: the logic axis image for the control circuit of the control signals

Pig. 4: a signal diagram for a data transfer process.

In.vPig. 1 shows a multicomputer computer with a "master" computing unit MR 1 and three "slave" computing units IvIR 1 to MR 4. All of these arithmetic units MR 1 to MR 4 are interconnected via bus lines, the coupling bus B 1. Each arithmetic unit MR 1 bia MR 4 consists of a Zentralverarbeitungaeinheit ZVE 1 bia ZVE 4, a Datenübertragaeinrichtung DU 1 bia DU 4, each with an input ZAusgabetorschaltung EA 1 bia EA 4 and one memory Sp 1 bia Sp 4, the input and output accumulators AE 1 bia AE 4 and AA 1 to AA 4_.

In each arithmetic unit MR 1 bia MR 4, these assemblies are interconnected by a system bus B 21 bia B 24. The "slave" units MR 2 bia MR 4 control the processing of identical or even underachieving, simultaneously to be processed programs. For example, such programs control machining processes on tool machines. For example, a slave processor MR 2 can control the input from a

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stiffness reader, a keypad or other programmer and the output to an alpha-numeric display, screen display, printer, strip punch or other output device. The other "slave" units MR 3, MR 4 can be used to handle the process controlling information and the feedback signals. In this case, for example, a "slave" computing unit MR 3 again serve as a "master" computing unit for further "slave" computing units of a lower level, which likewise correspond to one another via a coupling bus B1 '. These "slave" computing units may, for. B. are used to control individual axes on a machine tool. The "slave" units MR 2, MR 3, MR 4 can also be used in such a structure for additional tasks, such as test and monitoring functions, test routines and the like. The "maater" -Recheneinheit MR 1 coordinates the operation of the "slave" -Recheneinheiten MR 2 to MR 4, supplies them with information from their memory Sp 1 and can also perform control functions themselves. Data transfers always take place between the "master" computing unit MR .1 and one of the "slave" computing units MR 2 to MR 4. For example, the "master" computing unit MR 1

, a data transmission to the "slave" -Recheeinheit RIR 3 desired, it occupies via the input-ZAusgabetorschaltung EA 1 of its data transfer device DU 1 the coupling bus B 1 with control and address signals from the input / output gate EA 3 of the data transfer device DU 3 as determined for the "slave" -Recheneinheit MR 3 determined. If the "slave" MR 3 unit is able to take over data, it does not

is busy with other, more priority tasks, it reports on the input-ZAusgabetorschaltung EA 3 their data transmission device DU 3, the coupling bus B 1 and the

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Input ZAuagabetorachaltung EA 1 of the data transfer device DU 1 of the "master" -Recheneinheit MR 1 their takeover ready juice back. Thus iat the connection between both arithmetic units MR 1 and MR 3 made and the data transmission can begin. The information to be output is initially as a word-wise constructed output block in the output accumulator of the "maater" -Recheneinheit MR 1, The first word transmitted sets in a word counter of the data transfer device DU 3 of acquiring "slave" -Recheneinheit MR 3, the number of words to be transmitted of the output block , which is then counted word by word during the further transmission. The last transmitted word has a special bit pattern. As soon as the word counter has counted down, it calls a comparator, which checks the last transmitted word for its correctness, thus obtaining information about the correctness of the transmission of the output block.

A data transmission from a "slave" -Recheneinheit MR 2 to MR 4 is carried out in the same way in the reverse direction. In this case, the "maater" -Recheneinheit MR 1 determines which of the "slave" -Recheneinheiten MR 2 to MR 4 in their simultaneous call to the "master" -Recheneinheit MR 1 first, in conjunction.

In Fig. 2, the input / Auagabetorschaltungen EA 1 to EA 4, connected by the buses for data B 11, addresses B 12 and control signals HS bus, are shown.

The input Auagabetorschaltungen EA 1 to EA 4 are divided into a data part Port A and an address part Port B. The input Z output gates EA 1 to EA 4 are constructed for bidirectional operation. Each input /

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Output gate EA 1 bia'.EA 4 are assigned to control suspensions LS 1 bia LS 4, which are connected to each other via the bus line HS-Bua for the control signals. A data exchange computing unit. IiR 1 bia MR 4 selects via the port B of their input VAuagabetorachaltung EA 1 bia EA 4 the desired by her participants.

For example, data is to be transferred from the ⁿ master ^fl -Recheneinheit MR 1 to the "alave" -Recheneinheit MR 2. the "maater" calculating unit MR 1 sends the address and interruption preambles for the "alave" calculating unit MR 2 to the collecting line B 12 via the port B of its input / output device EA 1. In this case, the data transmission is transferred from the "master" -Recheneinheit MR 1 desired. The signals output by the "maater" computing unit are located at the corresponding inputs of port B of the input Z output gate circuit EA 2 to EA 4. At the same time, the "maater" computing unit MR 1 has its control circuit LS 1 via its input / output gate circuit EA 1 called and the data direction signal b - data output from the "master" -Recheneinheit IvIR 1 - reported to this. The called "slave" computing unit MR 2 recognizes the call, sends back an acknowledgment to the "master" computing unit MR 1 and switches its control circuit LS 2 active and in the state specified by the data direction signal b. In the control circuits LS 1 and LS 2, the call signals and b are linked to the data output or data input signal RDY. The issuing arithmetic unit ("master") outputs a corresponding ready signal to the bus HS bus for the control signals. The receiving arithmetic unit ("slave" MR 2) forms in its control circuit LS 2 a Datenausleae - / - read-in signal, which is placed on the bus HS bus for the control signals. The data transfer then takes place from port A of the input / output gate circuit EA 1 of the "master" calculating unit MR 1

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via the data bus B 11 to the port A of the input / output gate EA 2 of the "slave" -Recheneinheit MR 2.

In the same way, one of the "alave" calculating units MR 2... MR 4 can request a data exchange with the "maater" calculating unit MR 1. The "maater" -Recheneinheit MR 1 sets the data direction signal b in the state that indicates the direction of transmission from the "slave" -Recheneinheit MR 2 to the "master" -Recheneinheit IvIR 1.

FIG. 3 shows the logic circuit diagram of the control circuit LS.

With EA is the terminal side of the input ZAagabetorachaltung and with HS bus that of the manifold. The output b outputting the data direction signal is fed to an inverter N 1 and to the bus HS bus. The output of the inverter N 1 and the output b of the input / Äusgabetorschaltung EA are connected via a switch S 1 to an input of an AND gate U 1 and a second inverter N 2 to an input einea AND-U 2 U-guided. The second input of the AND gate U 1 is connected to the output RDY of an AND gate Ur, whose first input is connected to the output ARDY of the input / output gate EA and whose second input is connected to the output b- of the input Z output gate EA , The output of the AND gate Ur is also connected to one input of an AND gate U 3 and a conjunctive input link of a timer MV. The second input of the AND gate U 3 iat to the output of the AND gate U 2 and the terminal of the control signal bus HS-Bua for the read / read request signals PSTB disjunctively linked such that a bidirectional effect iat guaranteed. The output of the AND gate U 3 iat on the input / Aualeaebefehleingingang STB the input ~ / Auaga

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mentoring management EA led. The second input dea AND gate U 2 iat connected to the output dea Zeitachaltgliedea MV. The deactivation switch position is for the "maater" control unit at the entrance and for the "alave" control units at the entrance to the Negatora N 1.

Daa data direction signal b is output from the "maater" processing unit. About the Anachluß b 1, the control circuit LS is called.

As soon as the associated arithmetic unit emits a signal via the connection ARDY of the input-outputting circuit, it reaches the output dea AND element Ur, which calls the AND gate U 1. Daa AND gate U 1 forms, together with the data direction signal b, a data read out ready signal PRDY, which is applied to the bus HS-Bua. Daa Datenrichtungsaignal b arrives at the Steuerachaltung LS 1 for the "maater" -Recheneinheit MR 1 from the respective Auagang the input / Auagabetorachaltung EA 1 via the switch S 1 directly to the AND gate U 1, while it is at the control circuits LS 2 to LS q from the bus HS-Bua on the negator and the switch S on daa AND gate U 1 passes. The data readiness ready signal PRDY provided to the bus line HS-Bua designates the associated arithmetic unit, MR 1 to MR 4, as a sender of information.

In order to form the read / write request signal STB, the timer MV sends out the data read wait signal PRDY which is sent by the read-out processor MR 1 bia MR 4 via the bus HS bus and the input / output gate EA via the AND gate. Termination Ur status trip signal RDY reported a short duration signal in which the Auatauach aea Datenwörter3 aein must be formed. This signal is linked by the AND gate U 2 to the negation of the data direction signal a b _Q and passes via the signal U 2.

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called AND gate U 3 to the input ZA uagabetorachaltung EA of the receiving arithmetic unit MR 1 to MR 4 and the output of the AND gate U 2 directly via the bus HS-Bua as a signal PSTB to the data-outputting arithmetic unit MR 1 to MR ,

In Pig. 4 shows the course of a data exchange. A denotes the side of the issuing arithmetic unit and E the side of the acquiring arithmetic unit. The data exchange is initiated by a call signal R from the issuing side A, which appears as the signal R 'on the receiving side E, which sets there the input state EG. Within a prescribed waiting time t, an acknowledgment signal Q must have been transmitted by the receiving side E and received by the issuing side A as signal Q ¹ . Otherwise, no Datenentibertragungaverbindung comes off. With the acknowledgment Q ¹ , the call signal R is reset at the issuing side A and the Auagabezuatand AG set. Thereafter, the first word to be transmitted, which includes the number of words to be transmitted within the block to be outputted, is output as word AS 1 and received within a predetermined waiting time t from the receiving side E. The following words AS 2 to AS n-1 are transmitted and adopted in the same way, the output signals are always pending for a certain waiting time in which the takeover must take place. To Abachluß the data transfer daa word AS η auauggeben to verify the accuracy of the data transfer. In the case of a faultless data transfer, a word AS n + 1 can additionally be transmitted. During the duration of the test, the input state EG is already reset.

Claims (4)

205 141 invention claim 1. Multicomputer coupling for autonomously operating, active computing units, one of which as a "master" computing unit and the others as "slave" -Recheneinheiten with connected to these, programmable input-ZAzzabetorschaltungen are formed and via address, control and data lines to. Solution assigned to them tasks for asynchronous data exchange according to an interruption principle, characterized in that each arithmetic unit (MR 1 to MR 4) via an input z / Ausgababetorschaltung (EA 1 to EA 4) to common data and address information collecting lines ( B 11, B 12) is connected, and that each input / output gate circuit via a special control circuit (LS 1 to LS 4) for transmitting the control signals (RDY, SiTB) to a bus (HS bus) for asynchronous, di- " Direct and conflict-free data exchange between the "master" -Recheneinheit (IiR 1) and one of the "slave" -Recheneinheiten (MR 2 to MR 4) is connected, and that the "master" -Recheneinheit (MR 1) associated input / Output gate circuit (EA 1) has an operable by this data direction signal output (b), with the other input / output gate circuits (EA to EA 4) for determining the transmission direction and the priority of "maater" -Recheneinheit (MR 1) is connected. , 2. Multiprocessor coupling according to item 1, characterized in that the input / Ausgabetorachaltung (EA 1) of the "maater" -Recheneinheit (MR 1) with a means for determining the priority of several simultaneously requesting "alave" -Recheneinheiten (AIR 2 to MR 4). 205141 13 3. Multicomputer coupling according to item 1 and 2, characterized in that the Steuerachaltung- (LS) a konjuhktivea Verküpfungaglied (U 1) for the auausgebene of the "maater" -Recheneinheit (MR 1) and the "alave" -Recheneinheiten (MR 2 bia MR 4) has a data direction signal (b) received via an inverter (N 1), and for which read / write ready signal (RDY), the output is routed to a second averaging subjunctive element (MV) having a timing characteristic Anchluß for daa Einleae- / Aualeaebereitachaftaaignal (RDY) connected iat, and deaaen Auagang a third a link member (U 2) with the Datenrichtungaaignal (b) for the "maater" -Recheneinheit (MR 1) and deaaen negation for the "alave "-Recheneinheiten (MR 2 bia MR 4) on the Einleae- / Aualeaeanforderungenseiningänge (PSTB) of the remaining Rechenein- units (MR 1 bia MR 4) and a fourth a linkage element (U 3) i with its other input to the zw The input of the second conjunctive logic element (MV) and the connection for the read / write ready signal (RDY) are aligned to the input / input request input (STB) of the input / output device associated with the connected arithmetic unit (MR 1 bia IvIR 4). Issuer delivery (EA 1 bia EA 4) led iat. 4. Multiprocessor coupling according to point 1 bia 3, characterized in that the control circuit (LS) aufweiat an activation input (b 1), via which it with its arithmetic unit (IvIR 1 to MR 4) via the associated input / output gate circuit (EA 1 to EA 4) is connected to the call for the Datenauatauach. 205141 14 Multi-computer coupling according to items 1 to 4, characterized in that each input-ZAuszabetorschaltung (EA 1 bia EA 4), a timer for determining the waiting time within the transmitted / received by her data word from the other, participating in data processing unit (MR 1 bia MR 4) must be adopted / sent, and a programmable, from the requesting arithmetic unit (JiIR 1 to MR 4) to be triggered timing error message for not within a waiting time (t) from the called arithmetic unit (MR 1 big MR 4) arriving receipt signal , For this JL.Seilen drawings