DE2912734A1 - MULTI-COMPUTER COUPLING - Google Patents

Description

-S-

Multi-computer coupling

The invention relates to a multi-computer coupling system with several computer units which are connected to one another via a coupling interface designed uniformly for all computer units in such a way that one computer unit functions as a "master" computer and the others as a "slave" computer. Such years without r sy stars serve to increase the processing power compared to a single computer, in particular when using microprocessors for various tasks, for example for controlling processing and processing processes with non-time character.

Ss is known to have several processing units in one system couple. In DE-OS 24 46 970 several processing units operating independently of one another are provided via an interface unit connected to a common memory, the ranking of the arithmetic units during memory access by a Priority determination unit is set.

Ö09846 / 05 & S

With / this type of coupling, data is always exchanged via the common Speicner.

Peripheral-like couplings via special connection controls are also known. According to DE-OS 26 45 341 is included each coupling path between two Kecheneinneiten a coupling arrangement assigned. This can be designed as a compact, independent unit or assigned to each computing unit to be coupled be. In the case of arrangements with more than two processing units, multi-computer systems can be set up in ring or star structures build up.

The disadvantage of such multi-computer systems is that for each connection between two processing units separate Coupling devices are necessary.

The aim of the invention is to create a coupling circuit for a multi-computer system that has very little circuitry and constructive effort achieves a high level of performance and at the same time a cost-effective one and easy-to-use structure with a high degree of standardization of the assemblies used.

The object of the invention is to provide a coupling system that is as simple as possible in its structure for several simultaneous and Active processing units working autonomously on an overall task, one of them as the "master" - and the others as "slave" computing units are provided with associated Creating coupling circuits that allow asynchronous communication of the individual processing units via interrupt calls.

909846/0565

291273k,

According to the invention, this object is achieved in that each Arithmetic unit is assigned an input / output gate circuit which is programmable for bidirectional operation and which has a data and an address and control part which are connected to one another via bus lines so that when data is exchanged always the "master" processing unit with a "slave" processing unit connected is.

Each input / output gate circuit is a special control circuit for the transmission of the control signals via a special bus line for the direct and conflict-free connection of the Arithmetic units involved in the data exchange are assigned via their input / output circuits. That of the "master" computing unit associated input / output gate circuit v / eist one through this actuatable data direction signal output, the one with the other input / output gate circuits to define the direction of transmission is connected. The control circuit has a conjunctive "logic element for that of the "master" processing unit output and by the "slave" processing units received data direction signal and for the read-in / Read-out readiness signal on, the output of which on a second conjunctive link with a time switch-o characteristic is led. The second input of the conjunctive logic element with time switching characteristics is connected to the connection for the Einiese-ZAuslesbeereitbeigssignal connected and be The output is via a third link with the output for the data direction signal for the "master" computing unit and its negation for the "slave" processing units on the read-in / read-out request inputs of the other processing units and via a fourth link, the one with its other Input at the second input of the second conjunctive link and the connection for the read-in / read-out readiness signal is connected to the input / readout request input of the connected processing unit assigned input / output gate circuit.

8098A6 / 0565

The control circuit has an activation input aul "via which it is called up by your processing unit via the associated input / output gate circuit for data exchange. The data part of the input / output gate circuit is for data in any code with a fixed length and the address part according to a single bit mode The connection between the "master" processing unit and the requesting or requested "slave" processing unit always exists for the duration of the exchange of information equipped with a device for determining the priority of several simultaneously requesting "slave" computing units. Each input / output gate circuit is assigned an error detection device sur Presetting by the arithmetic unit and in the input direction for presetting by the first './ort to be transmitted' is provided. The word counter is assigned an ITull-checking device, which is connected to a comparison device when calling up the check of the bit pattern of the last transmitted Y / ortes, which signals the termination if the data is correct and the termination if the data is incorrect. When a skate unit is called, a programmable timer is triggered in the requesting arithmetic unit, which responds and triggers an error message if the acknowledgment signal of the called arithmetic unit is not reported within the programmed V / arteseit. The "slave" processing units are intended to control different process sections or other identical or mutually different tasks. Your punctures are directed and coordinated by the "maater" computing unit. A request for data transfer can be made from one of the "slave" computing units or from the "mastor" computing unit via the address and control lines, which are routed via the input / output gate circuits

909846 / 058S

aiii 'connect the bus lines to earth.

The invention is intended below using an exemplary embodiment explained in more detail. In the accompanying drawing demonstrate:

Fig. 1: the block diagram for 4 coupled together Computing units

Fig. 2: the block diagram of the input / output gate circuits connected via bus lines

Fig. 3 · 'the logic circuit diagram for the control circuit of the Control signals

4: a signal diagram for a data transmission process

In Fig. 1 is a teaching computer system with a "master" computing unit IHl 1 and three "slave" computing units 1> TR 2 bis LIR 4 shown. All these arithmetic units LIR 1 to LIR 4 are connected to one another via uar.miel lines, the Iloppelbus B 1 tied together. Each computing unit LIR 1 to MR 4 consists of a central processing unit ZVS 1 to ZVE 4, a data transmission device DU 1 to DLT 4 each with an input / output gate circuit iäA 1 to BA 4 and a memory Sp 1 each to Col 4, the input and output accumulators AE 1 to AE 4 and AA 1 to AA 4.

These assemblies are in each arithmetic unit LiR 1 to LTR 4 interconnected by a system bus B21 to B24. The "slave" processing units LIR 2 to IVIR 4 control the processing the same or different programs to be processed simultaneously. With such programs, for example Machining processes controlled on machine tools.

609846/0565

For this purpose, for example, a "slave" computing unit MR 2 can control the input from a punched tape reader, a Keypad or another programmer and output to an alpha-numeric display, a screen display, a printer, tape punch or other output device. The other "slave" computing units MR 3; MR 4 can be used to handle the information controlling the process and the feedback signals. In this case, for example, a "slave" computing unit MR 3 can again serve as a "master" computing unit for further "slave" computing units of a lower level, which also have a Coupling bus B1 correspond to one another. These "slave" computing units can e.g. be used to control individual axes on a machine tool. The "slave" computing units With such a structure, MR 2, MR 3 and MR 4 can also be used for additional tasks, such as testing and monitoring functions, Test routines and the like. The "master" computing unit MR 1 coordinates the operation of the "slave" processing units MR 2 to MR 4, supply them with information from its memory Sp 1 and can also perform control functions itself. Data transfers take place here always between the "mast he" arithmetic unit MR 1 and one of the "slave" processing units MR 2 to MR 4. Is used by the "master" -re ch en unit MR 1, for example, a data transmission for "slave" arithmetic unit MR 3 is desired, it occupies via the Input / output gate circuit EA 1 of your data transmission device DU 1 the coupling bus B 1 with control and address signals, from the input / output gate circuit EA 3 of the data transmission device DU 3 can be recognized as intended for the "slave" arithmetic unit MR, provided that the "slave" arithmetic unit MR is able to accept data, so it is not busy with other, more priority tasks, it reports via the input / output gate circuit EA 3 of their data transmission device DU 3, the coupling bus B 1 and the input /

909846/0565

Output gate circuit FA 1 of the data transmission device DU 1 of the "master" computing unit MR 1 indicates its readiness to take over return. The connection between the two arithmetic units MR 1 and MR 3 and the data transmission are thus established can start. The information to be output is available initially as a word-wise output block in the output accumulator of the "master" computing unit MR 1 “The first transmitted Word represents in a word counter of the data transmission device DU 3 of the accepting "slave" computing unit MR the number of words to be transmitted in the output block, which is then counted blank word for word during the further transmission will. The last word transmitted has a special bit pattern. As soon as the word counter is empty, it calls a comparison device that checks the last word transmitted to ensure that it is free of errors, whereby an Aus ^ a ^ tf gained about the correctness of the transfer of the output block will.

A data transmission from a "slave" processing unit MR 2 to IiIR 4 takes place in the same way in the opposite direction. The "master" computing unit MR 1 determines with which one the "slave" processing units MR 2 to MR 4 with their simultaneous Call the "master" processing unit MR 1 them first contacts.

In Fig. 2, the input / output gate circuits EA 1 to EA 4, connected by the bus lines for data B 11, addresses B 12 and IIS bus control signals. The input / output gate circuits EA 1 to EA 4 are in a data part Port A and an address part Port B divided. The input / output gate circuits EA 1 to EA 4 are built for bidirectional operation. Any input / output gate circuit EA 1 to EA 4 are control circuits IjS 1 to LS 4 assigned, which are connected to one another via the HS bus for the control signals.

809846/0565

A computing unit MR 1 to MR 4 wishing to exchange data selects the subscriber desired by it via port B of its input / output gate circuit EA to EA 4. If, for example, data are to be transferred from the "master" computing unit MR 1 to the "slave" computing unit MR 2, the "master" computing unit MR 1 sends the address and interrupt signals for via port B of its input / output gate circuit EA 1 the "slave" computing unit MR 2 to the bus B 12. In this case, the data transmission from the "master" computing unit MR 1 is desired. The signals output by the "master" computing unit are at the corresponding inputs of the port B of the input / output gate circuit EA 2 to EA 4. At the same time, the "master" computing unit MR 1 has YES ^{via its input V output gate circuit I 1.} 1 their control circuit · LS 1 called and the data direction signal b - data output from the "master" computing unit MR 1 - reported to this. The called "slave" arithmetic unit MR 2 recognizes the call, sends an acknowledgment to the "master" arithmetic unit MR 1 and switches its control circuit TjS 2 active and into the state determined by the data direction signal b. In the control circuits LS 1 and LS 2, the call signals and b are linked with the data output or data input signal RDY. The processing unit ("master") that issues a corresponding readiness signal on the IIS bus for the control signals. The receiving arithmetic unit ("slave" MR 2) forms a data read-out / read-in signal in its control circuit LS 2, which is placed on the collecting line HS bus for the control signals. The data is then transferred from port A of input / output gate circuit EA 1 of "master" computing unit MR 1 via data bus B to port A of input / output gate circuit EA 2 of "slave" computing unit I.iR 2.

In the same way, one of the “slave” processing units MR 2... MR 4 can exchange data with the “master” processing unit Request MR 1. The "master" computing unit MR 1 sets the data direction signal b in the state that determines the direction of transmission from the "slave" processing unit MR 2 identifies the "master" computing unit MR 1.

909846/0565

In Fig. 3 the logic circuit diagram of the control circuit LS is shown.

RHt EA is the connection side of the input / output circuit and, with HS-Bus, that of the collecting line. The output b, which outputs the data direction signal, is fed to an inverter II 1 and "to the collecting line HS bus. The output of the lie gator IT 1 and the output b of the input / output gate circuit EA are via a switch S 1 to a Input of a UiTD element U 1 and via a second inverter N 2 to an input of an AND element U 2. The second input of the AND element U 1 is connected to the output RDY of an AND element Ur, the first input of which is connected to the output ARDY of the input / output gate circuit EA and whose second input is connected to the output b of the input / output gate circuit EA. The output of the AND element Ur is also each with an input of an AND element U 3 and a conjunctive input linkage of a timer MV "connected. The second input of the AND element U 3 is linked to the output of the UITD element U 2 and the connection of the HS bus control signal bus for the read / read request signals PSTB dis «junktiν so that a bidirectional effect is guaranteed. The output of the AND element U 3 is fed to the read-in / output command input STB of the input / output gate circuit EA. The second input of AND gate U 2 is connected to the output of the time switch member MV ", respectively. The position of the switch S 1 is responsible for the ^{l master!"} -Recheneinheit at the entrance and for the "slave" -Recheneinheiten at the output of the inverter N 1 .

The data direction signal b is used by the "master" processing unit issued. The control circuit LS is called up via the connection b 1.

Q098 46 / 0SGS

As soon as the associated arithmetic unit outputs a signal via the ARDY connection of the input / output gate circuit, this arrives at the output of the AND element Ur, which calls the AND element U 1. The AND element U 1 forms it together with the data direction signal b, a data read-out readiness signal PRDY, which is sent to the HS bus. The data direction signal b arrives at the Control circuit LS 1 for the "master" computing unit MR 1 from the relevant output of the input / output gate circuit EA 1 via the switch S 1 directly to the AND gate U 1, while it is in the control circuits LS 2 to LS 4 of the Collective line HS bus reaches the AND gate TJ 1 via the inverter and the switch S. That to the manifold Data read-out readiness signal PRDY output by the HS bus denotes the associated arithmetic unit MR 1 to MR 4 as the sender of information.

For the formation of the 5i sneeze / output there would be a requirement si gnalj · STB is made ready for data readout by the time switch MV tssignal PRDY, from the arithmetic unit ready to output, MR 1 to MR 4 via the HS bus is sent, and the read-out signal reported by the input / output gate circuit EA via the AND element Ur RDY a signal of short duration in which a data word must be exchanged. This signal is from the AND gate U 2 with the negation of the data direction signal b linked and arrives at the input / output gate circuit EA via the called AND element U 3 the receiving arithmetic unit MR 1 to MR 4 and from the output of the AND element U 2 directly via the HS bus as a signal PSTB to the data processing unit MR to MR 4.

$ 01846/0585

In Pig. 4 int shows the sequence of a data exchange. ItLi: A is the side of the issuing arithmetic unit and E is the side of the accepting arithmetic unit. The data exchange is initiated by a call signal R from the issuing side A, which appears as a signal R ^f on the receiving side "S, which sets the input state EG there. An acknowledgment signal Q must be sent out by the receiving side E within a prescribed waiting time t and have been received by the issuing side A as signal Q ^1. Otherwise, no data transmission connection is established. With the acknowledgment Q ', the call signal R is reset on the issuing side A and the output state AG is set. The first word to be transmitted, the contains the number of words to be transmitted within the block to be output, output as word AS 1 and received within a specified waiting time t by the accepting side E. The following locations AS 2 to AS n-1 are transmitted and accepted in the same way, whereby the output signals are always pending for a certain waiting time in which the takeover must take place. At the end of the data transfer, the word AS η is output to check the correctness of the data transfer. If the data transfer has taken place without errors, a word AS n + 1 can also be transferred. The input status EG is already reset for the duration of the test item.

Claims (11)

12th Claim: i Multi-computer coupling for active processing units, of which one as "master" and the rest as "slave" computing units via coupling devices and address, control and data lines to solve tasks assigned to them with one another for asynchronous data exchange according to an interruption principle are connected, characterized in that for each of the autonomous computing units (MR 1 to MR 4) one for bidirectional Operation of programmable input / output gate circuit (EA 1 to EA 4) is provided which have a data and an address and control part which are connected to one another via bus lines (B11, B12), and that every input / output gate circuit (EA 1 to EA 4J a special one Control circuit (LS) for the transmission of the control signals (RDY, STB) via a common line (HS bus) for direct and conflict-free connection of the input / Output gate circuits (EA 1 to EA 4) on the data exchange, which is always between the "master" computing unit (MR 1) and a "slave" processing unit (MR 2 to MR 4) takes place, participating processing units (MR 1 to MR 4) is assigned. 2. Multi-computer coupling according to claim 1, characterized in that that the input / output gate circuit (EA 1) assigned to the "master" arithmetic unit (MR 1) is one which can be actuated by the latter Has data direction signal output (b) that is connected to the other input / output circuits (EA 2 to EA 4) is connected to determine the direction of transmission. 909SA6 / Ü5SS ORIGINAL INSPECTED 3. Multi-computer coupling according to claim 1 and 2, characterized in that the control circuit (LS) has a conjunctive logic element (U 1) for the output from the "master" computing unit (MR 1) and from the "slave" computing units ( MR 2 to MR 4) via an inverter (N 1) received data direction signal (b) and for the read-in / read-out readiness signal (RDY), the output of which is led to a second conjunctive logic element (MV) with a time switching characteristic, the second input of which with the connection for the read-in / read-out readiness signal (RDY) is connected, and its output via a third logic element (U 2) with the data direction signal (b) for the "master" computing unit (MR 1) and its negation for the " slave "arithmetic units (MR 2 to MR 4) to the read-in ZAualeseannahmseedänge (PSTB) of the other arithmetic units (MR 1 to MR 4) and a fourth logic element (U 3), which has its other input at the second input de s second conjunctive logic element (MV) and the connection for the read-in / read-out readiness signal (RDY) is connected to the read-in / read-out request input (STB) of the input / output gate circuit (EA 1 until EA 4) is performed. 4. Multi-computer coupling according to claim 1 to 3, characterized in that the control circuit (LS) has an activation input (b1) through which it can communicate with its arithmetic unit (MR 1 to DOOR 4) via the associated input / output gate circuit (EA 1 to EA 4) is connected to the call for data exchange. 909846/0561 5. Multi-computer coupling according to claim 1 to 4, characterized in that the data part (port A) of the input / output gate circuits (EA 1 to EA 4) for data in any code with a fixed word length and the address part (port B) are constructed according to a single bit mode. 6. Multi-computer coupling according to claim 1 to 5, characterized in that there is always the connection between the "master ^u arithmetic unit (MR 1) and a requesting or requested" slave "arithmetic unit (MR 2 to MR 4) for the duration of the data exchange, the data direction output Cb) of the “master” computing unit (MR 1) being provided for determining its priority over the “slave” computing units (MR 2 to MR 4). 7. Multi-computer coupling according to claim 1 to 6, characterized in that each computing unit (MR 1 to IR 4) for detection its interrupt and address signals has a mask circuit and the "master" computing unit (MR 1) with a device for determining the priority for several simultaneously requesting "slave" computing units (MR 2 to MR 4) is equipped. 8. Multi-computer coupling according to claim 1 to 7, characterized in that each input / output gate circuit (EA 1 to EA 4) is assigned a fault detection device. 9 · Multi-computer coupling according to Claims 1 to 8, characterized in that each arithmetic unit (MR 1 to MR 4) has an iron word counter in its input / output device, the in the output direction for presetting by the arithmetic unit and in the input direction for presetting the first word to be transmitted is foreseen. Ö098A6 / 05G5 291273A 10. Multi-computer coupling according to claim 1 to 3, characterized in that the word counter is assigned a J) JuIIprUfungseinrichtung, which is connected to call the test of the bit pattern of the last transmitted word with a comparison device, which terminates the correct transmission and terminates the transmission the data signals. 11. Multi-computer coupling according to claim 1 to 10, characterized in that each computing unit (MR 1 to IvIR 4) has a timing circuit to determine the waiting time within which the data word sent / received by it from the other on Data traffic involved computing unit (MR 1 to MR 4) must be accepted / ended, which has when exceeded the waiting time interrupts the data traffic, and that each processing unit (MR 1 to MR 4) one per gran mi erable from the requesting Computing unit (MR 1 to MR 4) has triggered time circuit which leads to the error message | if not in the intended Waiting time (t) incoming acknowledgment signal from the called Computing unit (MR 1 to MR 4) / is provided. - 4 sheets of drawings - 0098 ^ 6/0565