DD149267A1 - DEVICE FOR EVALUATING FREQUENCY ANALOGUE SIGNALS - Google Patents

Abstract

The invention relates to a device for evaluating frequency-analog signals by means of a direction discriminator and a downstream forward-backward Zaehlers simultaneous quadrupling the output from an incremental encoder against each other by 90 degrees phase-shifted signals and is used in particular for digital Drehzahlistwerterfassung. In order to obtain an unaltered signal in the counter, the direction detection is carried out so that caused by shock interference short-term signal changes are not and thus not lead to the formation of additional Zaehlimpulsen.Dazu a clocked synchronous memory-affected switching system is used, with the help of the input signalzustaenden a short-term, drehzahlunabhaengiger representing a certain rotational direction state is formed, from which the actual Zaehlimpuls is derived, which is subsequently processed so that no count pulse is lost.

Description

Title of the invention

Device for evaluating frequency-analog signals

Field of application of the invention

The invention relates to a device for evaluating frequency-analog signals by means of a direction discriminator and a downstream counter, in particular for digital Drehzahlistwerterfasaung

Characteristic of the known technical solutions

For the evaluation of frequency-analog signals, it is known to lead two mutually phase-shifted emitted by an incremental encoder pulse sequences and their negated signals on a direction discriminator and detect by means of a downstream up-down counter. Since a simple pulse processing affects many times resolution and accuracy and a high accuracy and high resolution requires the transmission of high measuring frequencies with special facilities, simultaneously a pulse multiplication is performed, whereby the signals generated by the measuring system, for example, twice or quadruple evaluated and the transmitted Precmenz is reduced accordingly "

"From DB-AS 12 48 720, a logical network for forward-Poickwärts-discrimination of two phase-shifted signal sequences is known, which makes it possible with the help of two memory locations representing flip-flops and the switching state of these flip-flops and the current to the Incremental signals are used to determine if there is a new incrementer and whether the counts available at the output of the logic network are to be added or subtracted in a downstream counter, this logic network eliminating some of the disadvantages associated with dynamic discrimination the use of timing elements such as differentiating stages or monostable multivibrators thus occurs and is thus already more user-friendly in terms of complexity and susceptibility, but still has some disadvantages: the four- during a period determined by the incrementer of an input signal for counting abg Since these count pulses are distributed for each counting direction to two outputs of the logical network, there is still an additional outlay for a true quadrupling, which can not be realized by a simple pulse gate, because with such only a non-usable duration pulse would arise. The counting output pulses generated by the logic network represent the direct states of the input line and the memory locations used to store the respective previous state combinations of the input lines. Also, as can be seen from the Boolean equations given, only the one State of a flip-flop evaluated »This means that a fault is detected during the entire period of the cycle.

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flussung occurring temporary tilting of the flip-flop leads to the formation of an undesirable additional count. As can be seen from the description of the known technical solution further, the counter for registering the output pulses of the network is directly nachgeschältet this. This means that if the pulses used for payment, which, as they are speed-dependent, have neither a constant pulse interval nor a constant pulse width at a speed change, are evaluated by the payer in this form, in the case of disturbances occurring during a pulse or when an interference pulse occurs a pulse break, that the counter would register this as a pulse and thus indicate a false signal. Also, in the period from the expiration of the measuring time of the counter to the beginning of the following counting cycle count pulses are lost in an application of this arrangement.

Object of the invention

The invention has the aim of avoiding the known disadvantages, in particular the evaluation of frequency-analogue signals so shaped that the. Counter registered value remains largely unimpaired by interference.

Explanation of the essence of the invention

-The technical problem, which is solved by the invention.

The technical task is to carry out the direction detection and pulse multiplication so that

'A short time caused by interference signal change is not registered by the circuit and thus does not lead to the formation of additional counts, and that are provided for the counter easily evaluable and clocked in a fixed grid signals available, and the further processing of the counted in the counter value is only done at a time when there is no count pulse

Features of the invention

According to the invention the object is achieved in that the provided for the direction detection and pulse multiplication switching system except for the storage of the four possible Vierkombina.tionen the input signals required two memory devices has a further Speicherbaueleraent, and that by applying a common system clock to all three memory devices the switching system is clock-state controlled. The logical connection within dee switching sys terns takes place such that by comparing the instantaneous state of the input signal with the stored Vorzustand at the occurrence of a clock pulse at the outputs of the switching system, by short-term, speed-independent formation of a certain direction of rotation representing state of the outputs of all three Memory components, a pulse corresponding to the pulse width for different directions of rotation occurs. From this pulse at the beginning of each pulse, a pulse is combined with the system clock and with an original clock having the same frequency as the actual counting pulse its phase position and pulse width with the

Pulse at the outputs of the switching system identical pulses * _s whose pulse intervals correspond to the measuring time of the counter used. By linking it with the .Impulspause of the original clock in conjunction with the system clock creates a signal to take over the counter contents of .zähler in a memory. By further linking this pulse for the measuring time in conjunction with the pulse interval of the system clock a signal for subsequent reset of the counter is formed »

In an embodiment of the solution according to the invention, it is advantageous to use as memory components D-trigger. Furthermore, the logic switching system instead of conventional logic elements by using a decoder simplified or realized by means of a Pestwertspeichers be realized. In a further advantageous embodiment, the clock control can be done from a system clock, which is synchronized with a computer _e

embodiment

An embodiment of the invention will be described below with reference to drawings. From the drawings shows:

Fig. 1 shows the logical switching system using a decoder

Pig » 2. the counting pulse based on a pulse.

diagram. , ,

Fig. 3 shows the signal formation for storing and for

Resetting the counter based on a pulse diagram

The logical switching system has four inputs at which the signals phase-shifted by 90 ° el u. and up one

- '• te- 2 If 2

incremental encoders and their negated values U ₁ and u _? The switching system, which is constructed with NAND logic elements and a decoder, is subdivided into the overflow logic with the NAiID elements in the links shown in FIG. 1, which are achieved by a known input logic system serving to suppress interference 1 to 15, by means of which the necessary links shown in FIG. 1 are realized, into the register section with the three memory devices d., d ₂ and d 1, shown as D-trigger, whose clock inputs occupy the system clock b are and in the output logic with the NAND-Blementen 16 to 23 and the decoder 24, whose outputs each have a negator 25 is connected downstream. The NARD-Blements 16 to 23 are driven by the outputs q ^, q _pJ q ^, "qj""q _{2 to} ³ " ^ 3 of ^the ^ D-triggers in the link shown in S ¹ ig 1 The decoder 24 processes the logically true signals of the outputs q ^, q ₂ and q ^ of the D-trigger cL, dp and d ^ · Am. of the decoder 24 downstream inverters 25 output then signals are available, the ζ states to Z ₅ - *

₂ ⁼ ^ 1 ^q 2

3 ⁼ ^ 1 ^q 2

^Z 4 ^sq 1 ^ 2

q ₂ a.3

correspond. The outputs of the NAND elements 16 to 23

-and the signals z "to Z ₁ -the negators 25 are returned to the inputs of the transfer logic. The signal ζ at the inverter 25 forms the output A ₁ for the positive direction of rotation, the signal z. the output A_ for the negative direction of rotation .. Starting from the input campaigns U ₁ , U ₂ , tu, U _{2 of} the incremental encoder · for their four combinations U ^ U ₂ , u ^ u ₂ , U ₁ u ₂ and U ₁ U ₂ are four states Zp to ζ, - set, which are usable for both directions of rotation with proper consideration of all transitions between the above-mentioned signal combinations. To achieve a fault-free detection of the frequency analog measurement signal without any loss of pulse and the greatest possible interference independence, a clocking of the switching system is introduced. Since only pulses of the clock width are emitted as a result, a brief signal change caused by interference is not registered in the transfer logic and does not lead to the formation of additional counting pulses. In addition to the four fixed states Z ₂ to zv, two additional intermediate states ζ and Z _{1 are} introduced. This means that the transition from one of the four fixed states to a pole state takes place each time via an intermediate state z _Q or z * . This intermediate state, triggering either a pulse c at the negative output A_ or a pulse c at the positive output A respectively at the edges of the u-signals, which is speed-independent and represents a particular direction of rotation, has the advantage of the outputs A and A__ easily evaluated to be. The storage of these six states requires three memories for dual encoding. The Scha.lts.ystem operates on the well-known principle of the automatic mooring machine, according to which each subsequent state of the Vorzustand and the input signals when changing the input signals with the

next clock pulse is produced. The formation of the "short-term, rotational speed-independent Zvjischenzustand representing a certain direction of Breeding the outputs of the three D-triggers d., Dp and d ^, which gives the output logic, the pulse c with its constant the system clock b corresponding width occurs after each change in state of the on The signal sequence at the outputs of the three D-triggers is compared with the actual state of the input signals, irrespective of the type of logic elements used for implementation, the following link applies to the conversion logic:

^U 2 ^ Z (^ -i ^ q ^) + u ^ f U ^ q ^ (q ^ + qj) + ^u -j ^ 2

2 ^{= 11} I ^U 2 ^ T ^ ^{+ q} 3 ^ ⁺ * H ^U 2 ^ T ^q 2 ^ 3 ^{+ U} 1

u _? (qj + q ^ j qj) + ü

+ ^u -j ^ 2 ^q 2 ^ I ^q 3

A disturbance during the occurrence of the pulse c generated by the synchronous switching system of clock width corresponding to Pig 2 or the occurrence of a glitch during, the pulse break of c, the downstream gate-back counter could register as a count and thus indicate a false signal * Therefore and for complete detection of the frequency analog measurement signal .Wird

- cut out from the pulse c a voltage-time area, which is further processed as the actual count pulse f. The count f is at a defined time, namely at the beginning of the clock period by linking the pulse c with the system clock b and the double frequency having original clock a after the puncture

Count f = a.b.c, formed *

At a frequency of the Systerataktes b ^J of 500 kHz thus produces a count pulse of 500 ns width. This means that the next counting pulse f can certainly only occur at the start of the following clock period, so that a time of 1500 ns is safely available for further signal processing (storing the value of the actual value counter and resetting the counter). If one then introduces a further pulse e in accordance with FIG. 3, which is in phase with the pulse c and has the same pulse width, which is thus synchronized with the system clock b, but whose pulse intervals correspond to the delay time of the counter, then one obtains by its combination with the pulse break of the original clock a in connection with the system clock b after the puncture

S = e.a.b

a signal S that it. allows the counter contents to be transferred to a memory.

Thus, for the resetting of the counter, which should also take place before the arrival of the next count f, the earliest can occur until the next positive plank of the system clock b, · still stands ^half period of the system clock b at your disposal. The reset signal R is formed by linking the pulse e with the pulse break of the system clock b

ΊΟ <ρ§ 4. g:% η g-

after the function

R s e. b

With such a derivation of the clock pulses, no counting pulse is lost, and the actual value detection is absolutely accurate. The maximum frequency T ₁ to be transmitted via the measuring lines from the incremental encoder is thus only fj- = ^ ₅ and that of the switching frequency.

system provided pulse sequence c reaches a

f maxinality of. £ ~ h, where f. the frequency of

, _r D

Systefactaktes b is »

Claims (1)

Erfindungsanapruch: Means for evaluating frequency-analog signals with simultaneous quadrupling of two mutually phase-shifted pulse sequences of an incremental encoder using a r / a logic and memory devices for directional discrimination existing switching system which has separate outputs for different directions of rotation, where the comparison of the current at the inputs of the switching system lying incremental signals with the signals of the memory locations for the respective previous state combinations of the incremental signals used memory devices formed a specific direction of rotation representing states in pulse form and apply a downstream up-down counter, characterized in that except the two existing, the possible four Zuatandskombinationen the Singangssignale (u ^ j U ₂ ; uu; ü " _? ) Registering memory devices (d .. $ dp), another Speicherbaueleme nt (d0), and that by simultaneously applying a system clock (b) to all three memory devices Cd ^; dp "d) the switching system is · taktzuatandsgesteuert, wherein the logical link within the switching system is such that by comparing the current state of the input signals (u .; _u?; ü ,,; Up) with the stored state at the onset of a clock pulse a (b) by short-term, speed-independent formation of a state of the outputs of all three memory devices (d; d ₂ , d ^) representing a particular direction of rotation at the outputs (A .5 A_) of the switching system, a pulse width corresponding to the pulse width (c) for different directions of rotation occurs, and that from this pulse (c) j by its connection to the system clock (b) and having a double frequency having the original clock (a) , at the beginning of each cycle (b) the actual counting pulse (f) is formed, and in that a second pulse phase in its phase and pulse width with the pulse (c) at the outputs (A, A) of the switching system identical in the pulse interval of the measuring time of the Pre-Rückvjärts counter corresponding pulse (s) is used, the once by linking with the pulse break of the original clock (a) in conjunction with the system clock (b) a signal to take over dea Counter contents of the Vor-Hückvjärts-Zäiilers in a memory and 'weiteren by linkage in connection with the pulse break of the system clock (b) a signal sum resetting the VorVersion counter forms » 2 «device according to item 1, characterized in that the memory components (d *; d _?; D ^) are designed as D-triggers«, 3c device according to point 1, characterized in that the formation of the six states from the output signals of the three memory components (d.5 d ₂ ; d ~) takes place via a decoder (24) « -4 · Device according to item 1, characterized by. <That the logical switching system is realized by means of a read-only memory. 5. Device according to items 1 to 4, characterized by * that the system clock (b) is synchronized with a computer _e - For this 2 pages drawings -