DE4132574C2 - Clock synchronization method - Google Patents

Description

The present invention relates to a method for clock sync Chronization of incoming, from a serial bit sequence standing data words, with a given system clock of Receiver, with each data word entered by a start bit is leading.

The task of the receiver is to record the serial bit stream to make a decision when to receive a data bit has been to detect this and at an output for white to have further processing ready. For this, a clock to Ver can be provided in the recipient to a defined Time triggers the bit detection. The clock synchronization therefore has the task of a system clock in the receiver to synchronize the way that the synchronized Clock after arrival of the start bit after a defined time starts with a clock edge. This means that the system clock must be shifted by a certain phase, which of the Time of receipt of the start bit depends.

The simplest solution to the above problem would be a with the start bit triggered start-up process, which is a tactos zillator vibrates. In this case, however, you stand facing two crucial problems; once the Oszil same settling behavior with every switch-on process show and after a constant time to its maximum value be steady, on the other hand the settling time is over the amount of the transmission speed is a narrow limit puts. Another solution would be to work with one opposite the transmission speed higher clock frequency, but what can lead to such high frequencies that with normal elec tronic building blocks can no longer be processed.  

DE 36 04 834 A1 is already a circuit arrangement for clock synchronization of incoming, from a serial Bit sequence existing input signals known, in which the System clock of an oscillator at the receiving end continuously one of several circuits connected in series existing chain is supplied, with an incoming bit the output after a certain predetermined delay time that circuit releases at which at that time an edge change takes place.

From US 49 84 249 is a circuit arrangement known in which with the help of delay circuits received data signals with a high sampling or clock speed sampled and the samples are stored, around the optimal sampling time of the data signals determine.

The object of the present invention is a method of Specify the type mentioned above, which is simple and Way a synchronization of an incoming serial Bitfol enabled with the system clock of the receiver.

This object is achieved in that the Sy master clock of a receiving-side oscillator continuously one of several delay circuits connected in series existing delay chain is supplied, and that an on incoming start bit after a certain predetermined delay time the output of that delay circuit free the system clock is present at this time.

The basic idea is in the method according to the invention in keeping the oscillator turned on and in Starting moment the phase of this oscillator is sent so ver push that the required constant delay time is held. In this way, the swinging in and out behavior of the oscillator are ignored and it who which also does not need unnecessarily high clock frequencies.

To ensure a high level of functionality during the scan Ensure is a useful development of the invention according to the method characterized in that with the release the output of a delay circuit the outputs of all other delay circuits are blocked.

Using an example shown in the drawing Circuit arrangement for performing the invention The procedure will be explained in more detail below.

It shows

Fig. 1 shows the front part of an incoming data word with the corresponding synchronized clock,

Fig. 2 shows the basic structure of a clock synchronization unit for performing the method according to the invention, and

Fig. 3 shows more details of the structure of the Fig. 2 Darge presented clock synchronization unit.

In the embodiment shown here, it is assumed that the transfer rate is 1 Mbyte / s. This means that the bit width of the individual bits of the data word DW is 100 ns. The width of the start bit SB is also 100 ns. As can be seen from FIG. 1, the receiver would receive a negative clock edge upon arrival of the start bit in the embodiment shown, after receiving a "high" signal up to this point in time. The "high" signal means for the receiver to remain on hold until this point in time and not to process a received signal. This in turn means that the clock synchronization unit should also be on standby and not pass on a system clock T.

The start bit, more precisely its negative clock edge, should now trigger the start process for the clock synchronization unit. Since the first data bit arrives after 100 ns, the first query must therefore take place after 150 ns, as can be seen from FIG. 1. If the clock synchronization unit provides a starting clock that corresponds to the bit rate after this time, the subsequent data bits can now be read in with a clock frequency of 10 MHz. The receiver or the clock synchronization unit then switches back to the waiting position and the next data word can be received. In the example, it is assumed that the data word consists of a start bit and a stop bit, and eight pure information bits.

The basic structure of a clock synchronization unit is shown in FIG. 2. It essentially consists of n delay circuits V1 ... Vn and a decision logic EL. The system chain T is supplied to the delay chain consisting of the individual delay circuits, while the start bit SB is supplied to the decision logic EL. The output of each individual delay circuit V1 ... Vn is connected to the decision logic EL, at whose output the synchronized clock ST required for querying the information bits is present.

As already explained above, the basic idea of he exists inventive method in the quartz oscillator constantly to leave switched on and in the starting moment the phase of this Oscillators cleverly moved so that the required constant delay time is observed. So there will be by means of the Ver consisting of the delay circuits Delay chain generates different phases of the basic clock and at the appropriate point in time the phase called the closest requirements. From this it follows that the accuracy of this solution with the number of existing where different phases are increasing. Around 150 ns delay To achieve time, the signal synchronized in phase must only by a constant number of delay elements be postponed. The same effect would be through one It is possible to delay the start signal.

Stand z. B. ten different phases are available in the exemplary embodiment, each at a clock frequency of 10 Mhz shifted by 10 ns from each other. This would mean, that the constant required delay time fluctuates by 10 ns can. If you set the required time of the first posi tive clock edge in the middle of this fluctuation range, er gives an error of ± 5%. This would correspond to the same Chen accuracy of a system with a high clock frequency frequency of 100 Mhz would have to work.

The further operation of the method according to invention will be explained with reference to FIG. 3. The clock synchronization unit should be on z. B. nine delay circuits are limited and an error of 10% of the synchronized clock should be sought. That is, the decision logic EL is said to have placed one of the delayed clocks after 150 ns after the start bit has been received on the output.

This unit must therefore locate where the required Sy master clock is located. One can see the going through the system clocks through this delay circuit as one into this Imagine the directional positive flank that the En de the delay chain attains when a new clock edge on Entrance appears.

The object of the method according to the invention is now to cause this positive edge, wherever it may be at the time of the start bit, to trigger an operation which only leads this one cycle to the output. This is possible with a switching logic shown in FIG. 3.

As start bit SB, i.e. H. as a start signal, a change of Accepted "low" to "high". This start signal sets the "Clear" input C of a flip-flop FF to "high" potential and from this moment can trigger the "clock" on Clk said.

It is now to be assumed that the stage shown in FIG. 3 and considered here is currently being driven by a positive clock edge of the system clock T behind the delay circuit V1. Due to the combination of the system clock with the output signal of the output NQ of the flip-flop FF via the blocking gate SpG, this system clock is also present at the "clock" input Clk of the flip-flop FF and clocks the module. Before is exposed that the output signal of the output NQ is "high".

Up to this point, the state at the D input of the Flip-flops FF, which is the combination of all NO outputs of all existing flip-flops FF formed per delay circuit will be "high". This state is passed on to the Q output and enables the exit of the desired clock. At the same time, the barrier gate SpG with a level of "low" blocked by the NQ output and a new one  Clocking prevented. At the same time, all D inputs of the flip Flops FF set to the "low" level, since an input of the Tax gate StG is also "low". This ver prevents another delay from being clocked circuit associated flip-flops FF the same process would be directed. Through an OR operation in the output gate All outputs of the individual release gates FrG summarize in one.

Since the running time is shown by a delay circuit in the th embodiment is only 10 ns, must now be fixed to what extent existing switching and gate running times have an influence on the course of such an operation ha ben. A corresponding time balance must therefore be drawn up and then make a selection of the components so that the desired delay time is reached. In the present Example would have the internal, by the circuit arrangement ver caused delay time until a phase is activated 50 ns.

Claims (2)

1. A method for clock synchronization of incoming data words consisting of a serial bit sequence, with a given system clock of the receiver, each data word being initiated by a start bit, characterized in that the system clock (T) of a receiving-side oscillator is continuously one of several series-connected delay circuits (V1 ... Vn) to existing delay chain, and that an incoming start bit (SB) releases the output of the delay circuit (V1 ... Vn) after a certain predetermined delay time, at which point the system clock (T) is present. 2. The method according to claim 1, characterized, that with the release of the output of a delay circuit (e.g. V1) the outputs of all other delay circuits (V2 ... Vn) can be blocked.