DE2941697A1 - Measuring frequency of pulse series by summation - using defined time increments and comparison with summation limit value - Google Patents

Abstract

The system measures the frequency of a pulse series by counting the number of pulses occurring in a given time operation independently of periodic components in the pulse series. The device has a rapid response and a short integration time. It produces a digital output signal suitable for electronic data processing. The pulses are summed to form primary summed values at successive time intervals. The primary values are summed to form secondary summed values. The time intervals are chosen such that the number of pulses occurring in each does not exceed a given number. When the secondary summation exceeds the pulse limit by one, the corresp. first summation is reset to unity and the achieved value is output.

Description

Method and device for measuring the

Frequency of a Pulse Train The present invention relates to a Method according to the preamble of claim 1. The invention also relates a facility for carrying out such a procedure.

Facilities of the type of interest here are often called "ratemeter" when they are used to measure the instantaneous frequency (i.e. the number of pulses occurring during a certain time unit) of a sequence more or less irregularly occurring pulses are determined and suitable.

Means for measuring the frequency of one or more or less irregular pulse sequences should respond quickly (i.e. short integration times have), as insensitive as possible to a periodic modulation of the pulse train and provide a digital output signal from an electronic data processing system can be further processed directly.

There are both digital and analog working facilities known for measuring the frequency of a pulse train. Analog working facilities are not good for data acquisition for electronic data processing systems (EDP) suitable and also occurs with short integration times in the analog output signal a sawtooth ripple.

The known digital devices for measuring the frequency of a Pulse trains usually contain a counter that counts the number of input pulses counts that occur during a fixed time interval. Such facilities are only useful if the pulse sequence is purely statistical. But when the pulse train contains periodic components, beats occur with all higher Harmonics of the clock cycle and the counting frequency on what the measurements considerably can falsify.

The present invention is based on the object of a ver.

drive and a device for measuring the frequency of a pulse train indicate that are insensitive to periodic components in the pulse train, respond quickly, i.e. have a short integration time, and one for the electronic Provide a suitable output signal for data processing.

According to the invention, this object is characterized by what is defined in claim 1 Method and the device characterized in claim 4 solved.

Developments and advantageous embodiments of the invention The method and the device according to the invention are the subject of subclaims.

The method and the device according to the invention are very speaking fast, they are insensitive to periodic components (modulations) the pulse train and deliver a digital output signal that is fed directly to an EDP system can be.

The method and the device can also easily be configured in this way be that the digital output signal a linear function, a logarithmic function or any other function of the frequency (rate) of the Input pulse train is.

In the following, the concept of the invention is illustrated with the aid of exemplary embodiments explained in more detail with reference to the drawing.

The figures show: FIG. 1 a block diagram of an embodiment of the invention Device that provides a digital output signal that is a linear function the frequency of an input pulse train, i.e. directly proportional to this frequency is; Figures 2 and 3 are circuit diagrams of embodiments of the invention that incorporate a digital Provide an output signal which is a non-linear function of the frequency of an input pulse train is; and FIG. 4 is a circuit diagram of a logic input switching mechanism which is used in the Devices according to Fig. 1 to 3 can be used.

The device 10 shown in Figure 1 contains an input switching mechanism 12 with a signal input 14 to which a pulse train can be fed, the frequency of which or rate is to be measured. The input switching logic 12 also contains an overflow pulse input 16, a counting signal output 18 and a counting direction signal output 20, at which each according to the operating status of the input switchgear, a count-up signal or a Down counting signal.

The counting signal output 18 is one with a counting signal input 22 Up-down counting, s 24 connected. The counting direction signal output 20 is with a counting direction signal input 26 of the counter 24 is connected. The counter 24 has n digits and will in general like the other pulse-processing circuits the facility work binary.

The counter 24 has a count output 28 at which a digital signal which represents the number (count) contained in the counter. The count output 28 is coupled to a count value input 30 of an adder 32, the two summand registers 34 and 36 and an (n + 1) -digit adder 38 contains. The summand registers each have a summand input 34a or 36a, a clock input 34b or 36b and a summand output 34c or 36c. The clock inputs 34b and 36b are coupled to the output of a clock pulse generator 40 which has a clock pulse train with a frequency fR, which is preferably switchable to the measuring range the facility to be able to change, as will be explained.

The count output 28 is connected to the input 34a of the summand register 34 connected. The output 34c of the summand register 34 has a first summand input 38a of the adder 38 is connected. The adder 38 has n + 1 digits and a sum output 38c, which is connected to the signal input 36a of the summand register 36. Of the Output 36c of the summand register is connected to a second summand input 38b of the Adder 38 connected. The summand register 36 also has an overflow output 36d, at which an overflow pulse occurs if the binary number in the summand register 36 becomes greater than 2 (or more generally greater than n digits).

The output 34c is connected to a signal output 42 of the device 10 coupled to which there is a digital output signal which shows the current frequency represents the pulse train.

The count value output 28 can be coupled to a digital / analog converter 44 be, at the output 46 of which an analog output signal is available that represents the pulse repetition rate.

In the connection between the overflow pulse output 36d of the summand register 36 and the overflow pulse input 16 of the input switching mechanism 12 is preferred a pulse shaping circuit such as a univibrator 48 is connected.

The device according to Figure 1 works as follows: Es. suppose that the counter 24 and the registers 34, 36 are at zero and that at the counting direction signal output 20 is an up count signal.

The pulse sequence, the frequency of which (number of pulses per second) is to be determined, is fed to the signal input 14 of the input switching unit 12 and passed through this to the counting signal input 22 of the n-digit counter 24. The counter now begins to count the incoming signal pulses in upward direction. The count value reached in each case is available at the count value output 28 and thus at the summand input 34a of the summand register 34. The adder 32 is clocked by the clock pulses from the clock pulse generator 40 with the frequency. With each clock pulse, the adder 38 adds the number in the summand register 34 to the number in the summand register 36 and the result, i.e. the sum, is stored in the summand register 36 as a new second summand. The adder 38 thus adds the counter value present at the output 28 at the clock time t to the sum of the count values stored in the summand register 36 that occurred between the clock time 0 and the clock time t1. The summand register 36 has n + 1 places. If a bit occurs in the (n + 1) th position, an overflow pulse is generated and fed to the overflow pulse input 16 of the input switching mechanism. This then switches the counting direction signal at output 20 to "down counting" and establishes a connection between the overflow pulse input 16 and the counting signal output 18. The counter 24 counts the overflow pulses in the downward direction The frequency fp of the pulse train fed to the signal input 14 is equal to the frequency fO of the overflow pulses generated by the adder and the number Z (t) in the counter 24 is equivalent to the frequency of the input pulse train. The number Z (t) representing the output variable at the signal output 42 follows the relationship: where mean: fp = instantaneous pulse repetition frequency (pulses per second) fR = clock pulse frequency n number of binary digits of the counter 24 t = time in seconds.

For t + X = Z (ovo) = (2n - 1) fp / fR (2) The described Facility works linearly. The proportionality factor that defines the relationship between Z (t) and fp produces is determined by the one available for digitization standing number of digits n and the clock pulse frequency fR. The measuring range can be by changing either or both of these sizes.

The highest measurable input pulse frequency is equal to the clock pulse frequency. The lowest input pulse rate that can be measured is inversely proportional the number of digits in the adder.

Typical clock frequencies fR are 102 2 to 106 Hz.

The device 10 according to Figure 1 provides a digital output signal, which shows the input pulse frequency continuously and with the clock frequency in each case is brought up to date. There are no dead times during the measurement, the time dependency of the measurement (corresponding to the integration time constant of a analog frequency measuring device) is defined.

In Figure 2 is the block diagram of an embodiment of the frequency measuring device represented according to the invention, in which a non-linear relationship between the input pulse frequency and the digital output signal. Components are the same or corresponding functions are given the same reference numerals in FIGS. 1, 2 and 3 referred to, however, to distinguish the reference numerals in Figure 2 are a prime and two lines added to those in FIG.

The device according to Figure 2 only needs to be described insofar as than it differs from that according to FIG.

The main difference between the facilities according to Figure 1 and 2 is that in the device according to Figure 2 not with a adjustable, but fixed clock frequency during a measurement, but with a clock frequency dependent on the input pulse frequency is used.

The device according to FIG. 2 contains a clock pulse generator for this purpose 40 ', whose output pulse frequency fa by a signal at a frequency control input 40-a is controllable. The clock pulse generator 40 'may, for example, be voltage controlled Oscillator included, a range switchover can also be provided here be, so a switch of the frequency range in which the clock pulse frequency can be controlled by a signal at the frequency control input 40 'a.

In the device according to FIG. 2, the digital / analog converter belongs 44 '> its input with the count value signal output 28' of the n-digit counter 24 'is connected to the circuitry / which has the desired non-linear relationship between the input pulse frequency and the digital output signal.

The output of the digital / analog converter 44 'is connected to the input of a Functional unit 50 'coupled. The functional unit 50 'is a circuit arrangement the analog signal fed to its input, that of the input pulse frequency fp is proportional, converted into an output signal, which in the illustrated embodiment is a logarithmic function of the input signal. Circuit arrangements that a converting a linear input signal into a logarithmic output signal are known. The output signal of the functional unit 50 'is the frequency control input 40'a of the clock pulse generator 40 'supplied. With logarithmic transfer function the functional unit 50 'results in a logarithmic dependence of the digital Output signal at the signal output 42 'of the frequency f' of the input pulse train. The device p according to FIG. 2 has the additional advantage that the measuring time constant remains the same over the entire area.

If the functional unit has the transfer function 1, i.e. if the output of the digital / analog converter 44 \ directly to the frequency control input 40a of the clock pulse generator 40 'is coupled as indicated by a dashed line is indicated, corresponds to the dependence of the output signal on the input signal frequency a root function.

Figure 3 shows an embodiment of the invention in which a non-linear Dependence of the output signal on the input pulse frequency not as in the figure 2 by analog circuits 44 'and 50', but by a digital one Functional unit 50 "is effected. Functional unit 50" is between the count signal output 28 "of the counter 24 [and the summand input 34" of the summand register 34 "in the adder 32 "switched. The clock pulse generator 40 'operates at a fixed frequency f" (which can preferably be switched to p range switching).

The functional unit 50 ″ works digitally and provides the desired functional relationship between the input pulse frequency and the size of the Output signal that occurs at the digital signal output 42 ″, the one with the counting signal output 28 ". An analog output signal is available at output 46" of the digital / analog converter 44 "is available, which is connected as in FIG.

The functional unit 50 "can, for example, have a quadratic transfer function and then simply contain a multiplier whose two inputs are the Count value is supplied from the output 28. The functional unit 50 ″ can also have another Have a transfer function, e.g. a logarithmic transfer function which e.g. can be realized with the help of a table memory.

Fig. 4 shows, for example, a circuit arrangement that acts as an input switching mechanism 12 can be used.

The signal input 14 and the overflow pulse input 16 are respectively connected to a monoflop 60 and 62, which are used for pulse shaping. The exit of the monoflop 60 is connected to a pulse input 64 of a pulse synchronizer 66, with a first pulse input 66 of a flip-flop 68 and with an input of a OR gate 70 connected. The output of the monoflop 62 is with a pulse input 72 of a pulse synchronizer 74, with a second pulse input 76 of the flip-flop 68 and connected to a second input of the OR gate 70. The outcome of the OR gate is connected to a clock input 78 of flip-flop 68. The flip-flop 68 has two outputs 80 and 82 in which complementary output signals appear.

The output 80 is connected to a preparation input 84 of the pulse synchronizer 74 connected, while the output 82 with a preparation input 86 of the pulse synchronizer 66 is connected. The outputs of the pulse synchronizer are via an AND element 88 connected to the output 18 of the input switching mechanism. The output 82 of the flip-flop 68 is also connected to the counting direction signal output 20 of the input switching unit 12. The circuit arrangement according to Fig.

4 can be implemented with commercially available integrated circuits; the type designations of suitable circuits are given in FIG. 4, for example. The flip-flop 68 is a so-called skew flip-flop that does not require any preparation time, thus also switches over when the pulse at the preparation or key input 78 and arrive at the signal input 66 or 76 at the same time.

The input switching mechanism 12 according to FIG. 4 operates as follows: It assume that flip-flop 68 is in the reset state, below which the condition is to be understood which is set by a pulse at pulse input 76 is and with which at output 80 a signal accordingly a logical one One, while a signal corresponding to a logical zero is present at output 82.

When a pulse of the pulse train arrives on line 14, the Rate or frequency is to be determined, this pulse is generated by the monovibrator 60 shaped and from its output to the signal input 64 of the pulse synchronizer, the pulse input 66 of the flip-flop and, via the OR gate 70, the key input 78 of the flip-flop 68 supplied. The pulse synchronizer does not let this pulse through, because there is a zero at the preparation input 86. The one at inputs 66 and 78 of the Flip-flops 68 practically simultaneously occurring pulse switches the flip-flop 68 to the set state in which a zero at output 80 and a zero at output 82 a one lie. The one at output 82 simultaneously represents the signal "Forward Count ".

The next pulse, the one at the signal input 14 of the input switching mechanism 12 arrives, the pulse synchronizer 64 can now go through, since at its preparation input 86 is a one. The AND gate 88 is the pulse synchronizer with complement outputs 66 and 74 connected, each of which toggle from 1 to 0 when the pulse synchronizer in question passes an impulse. At the inputs and at the output of the AND gate 88 is therefore in the idle state of the pulse synchronizer each a one and at the output A zero occurs only when one of the pulse synchronizers has a pulse to the AND gate 88 passes, since the complement output of the pulse synchronizer switched to 0 when a pulse is passed. The up / down counter 24 counts these zero pulses.

The first impulse that has arrived at the signal input 14 is set that is to say the flip-flop 68, however, is not passed to the counter 24, 24 'or 24 ". The next pulse that arrives at the signal input 14 can use the prepared pulse synchronizer 66 pass through to AND gate 88, so that this pulse from the up-down counter in the forward direction is counted.

The pulses of the pulse train are counted in the forward direction as long as until the AdtiSerwerk 32, 32 'or 32 "generates an overflow pulse, which after forming by the monovibrator 62 to the pulse input 72 of the pulse synchronizer 74, the Pulse input (reset input) 76 of flip-flop 68 and the clock input 78 of the flip-flop 68 is fed. The pulse cannot pass through the pulse synchronizer 74, since there is a zero at the output 80 of the flip-flop 68, which is still set. That Occurrence of the pulse at the inputs 76 and 78 of the flip-flop 68 sets this however back, so that now the pulse synchronizer 66 is blocked and the pulse synchronizer 74 is ready to pass. There is now a binary zero at output 82, which represents the counter switches to "counting down".

If an overflow impulse occurs next, it runs through this the pulse synchronizer 74 and the AND gate 88 to the counter, where it is reversed is counted, i.e. the count value is reduced by one unit. So the counter counts back by one unit with each cycle, as long as there is no new pulse at the signal input 14 occurs.

If a pulse occurs again at the signal input 14, the input runs described operations again, the flip-flop 68 is set, the relevant However, the pulse is not passed on to the counter. When the impulses reach the Alternate inputs 14 and 16, the counter reading remains unchanged. At constant Repetition frequency of the pulses at input 14 is this frequency in the steady state the facility is equal to the frequency of the overflow pulses at the overflow entrance and the number in the counter is proportional to the repetition frequency of the input pulses.

Claims (11)

Method and device for measuring the frequency of a pulse train Claims 9 method for measuring the number of during a given Time unit occurring pulses of a pulse train with generation of a digital one Output signal, which is not shown that the impulses are below Formation of first sum values are added up; that the first total values, which are present at intervals in time, with the formation of second sum values are added up, the distances between each two successive times are chosen so that the sum of in such a Time interval occurring pulses of the pulse train does not have a specified number of digits exceeds, that every time in the formation of a second Sum value a carryover in a place (n + l) of the second sum value, which is around one is higher than the specified number of digits, which occurs at this point in time present first sum value is reduced by one, and that the resulting first sum values can be used as the output signal. 2. The method according to claim 1, d a d u r c h g e k e n n z e i c h n e t that the distances are the same. 3. The method of claim 1, d a d u r c h g e k e n n z e i c h n et that the distances are changed as a function of the first sum values. 4. Device for performing the method according to claim 1, g e k e n n n z e i c h n e t by a) an input switching mechanism (12), the al) a signal input (14) to which the pulse train can be fed, a2) an overflow pulse input (16), a3) a counting signal output (18) and a4) a counting direction signal output (20) at which a count-up signal or a count-down signal are, a5) a count-up signal Generated at the counting direction signal output (20) when a pulse of the pulse train is sent to the signal input (14) arrives and forwards each subsequent pulse to the counting signal output (18) until a pulse arrives at the overflow pulse input (16) and a6) a countdown signal generated at the counting direction signal output (20) if on at the overflow pulse input (16) The overflow pulse arrives and each subsequent overflow pulse is sent to the counting signal output (18) forwards until a pulse arrives at the signal input (14); b) an up-down counter (24), the bl) n digits, b2) a counting signal input (22), which is connected to the counting signal output (18) the input switching logic (12) is connected, b3) a counting direction signal input (26), the one with the Counting direction signal output (20) of the input switching logic (12) is coupled, and b4) has a count output; c) an adder (32) which cl) can be controlled by clock pulses, c2) n + l places, c3) a count value input (30), which is coupled to the count value output (28) of the up / down counter (24) is, c4) a clock pulse input to which clock pulses can be fed, each one Trigger adding process, c5) a sum output (38c), at which a sum signal accordingly the result of adding two summands occurs, c6) a result register (36) for storing the result of the last adding process, c7) one by clock pulses controlled adder (38), the two summands, one of which is from the Count value at the output (28) of the up / down counter (24) and the other the value stored in the result register (36) exist when each clock pulse occurs added, and c8) has an overflow pulse output (36d) at which an overflow pulse occurs when the result of an addition has more digits than the up / down counter (24) and coupled to the overflow pulse input (16) of the input switching logic is, d) a clock signal generator (40), the dl) a clock pulse train with a frequency (fR), which is at least equal to the highest pulse repetition frequency to be measured, supplies, and d2) has a clock pulse output that is connected to the clock pulse input of the Adder (32) is coupled, and e) a frequency signal output (42) with the count value signal output (28) of the up-down counter (24) is coupled, 5. Device according to Claim 4, that the frequency (fR) the clock pulse train of the clock signal generator (40 ') by one of the frequency the input pulse sequence dependent signal is controllable. 6. Device according to claim 5, d a d u r c h g e k e n n z e i c hn e t that the count output (28 ') of the up-down counter (24') over a circuit arrangement (44 ', 50'), the transmission function of which is a desired non-linear dependence of the frequency signal occurring at the frequency signal output (42 ') and corresponds to the frequency of the input pulse train, with a frequency control input (40'a) of the clock signal generator (40 ') is coupled. 7. Device according to claim 6, d a d u r c h g e k e n n z e i chn e t that the circuit arrangement between the count output (28 ') and the Contains frequency control input (40'a) switched analog-digital converter (44 ') and that the clock signal generator (40 ') contains a voltage-controlled oscillator, which can be controlled by the output signal of the digital / analog converter. 8. Device according to claim 6 because you r c h g e k e n n z ei c h n et that the circuit arrangement is a series circuit of a digital-to-analog converter (44 ') and a circuit (50') with a logarithmic transfer function, between the count signal output (28 ') and the frequency control input (40') are switched. 9. Device according to one of the preceding claims, d a d u r c h e k e n n n z e i c h n e t that the frequency signal output (42, 42 ') has a Clocked register (34, 34 ') with the counter value output (28') of the up / down counter (24 ') is coupled. 10. Device according to claim 4, d a d u r c h gek e n n z ei c hn e t that the count output (28 ") of the up-down counter (24") has a digital circuit (50 ") with non-linear transfer function with the one to the other input (34 "a) of the adder (32") is coupled. 11. Device according to claim 10, d a d u r c h g e k e n n z ei chn e t that the transfer function is logarithmic.