CS560281A1 - Registracni operacni jednotka - Google Patents

Registracni operacni jednotka Download PDF

Info

Publication number
CS560281A1
CS560281A1 CS815602A CS560281A CS560281A1 CS 560281 A1 CS560281 A1 CS 560281A1 CS 815602 A CS815602 A CS 815602A CS 560281 A CS560281 A CS 560281A CS 560281 A1 CS560281 A1 CS 560281A1
Authority
CS
Czechoslovakia
Prior art keywords
register
arithmetic
input
control
output
Prior art date
Application number
CS815602A
Other languages
Czech (cs)
English (en)
Inventor
Nikola K Ing Kassabov
Ljudmil G Ing Dakovski
Original Assignee
Kassabov Nikola K
Dakovski Ljudmil G
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kassabov Nikola K, Dakovski Ljudmil G filed Critical Kassabov Nikola K
Publication of CS560281A1 publication Critical patent/CS560281A1/cs

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • G06F7/575—Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3828—Multigauge devices, i.e. capable of handling packed numbers without unpacking them

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Analysis (AREA)
  • Software Systems (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computing Systems (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
  • Pharmaceuticals Containing Other Organic And Inorganic Compounds (AREA)
  • Complex Calculations (AREA)
CS815602A 1980-07-22 1981-07-20 Registracni operacni jednotka CS560281A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
BG8048568A BG33404A1 (bg) 1980-07-22 1980-07-22 Registrovo aritmetichno ustrojjstvo

Publications (1)

Publication Number Publication Date
CS560281A1 true CS560281A1 (en) 1984-11-19

Family

ID=3907804

Family Applications (1)

Application Number Title Priority Date Filing Date
CS815602A CS560281A1 (en) 1980-07-22 1981-07-20 Registracni operacni jednotka

Country Status (8)

Country Link
US (1) US4463441A (Direct)
JP (1) JPS5790752A (Direct)
BG (1) BG33404A1 (Direct)
CS (1) CS560281A1 (Direct)
DE (1) DE3128816A1 (Direct)
FR (1) FR2487547A1 (Direct)
GB (1) GB2081480B (Direct)
IT (1) IT1171408B (Direct)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58106636A (ja) * 1981-12-18 1983-06-25 Hitachi Ltd パイプライン演算装置
US5179734A (en) * 1984-03-02 1993-01-12 Texas Instruments Incorporated Threaded interpretive data processor
GB8517498D0 (en) * 1985-07-10 1985-08-14 Jesshope C R Data stack
JPH07113884B2 (ja) * 1985-12-28 1995-12-06 株式会社東芝 論理回路
US5261113A (en) * 1988-01-25 1993-11-09 Digital Equipment Corporation Apparatus and method for single operand register array for vector and scalar data processing operations
US5150469A (en) * 1988-12-12 1992-09-22 Digital Equipment Corporation System and method for processor pipeline control by selective signal deassertion

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3391390A (en) * 1964-09-09 1968-07-02 Bell Telephone Labor Inc Information storage and processing system utilizing associative memory
US3787673A (en) * 1972-04-28 1974-01-22 Texas Instruments Inc Pipelined high speed arithmetic unit
US4025771A (en) * 1974-03-25 1977-05-24 Hughes Aircraft Company Pipe line high speed signal processor
US4159520A (en) * 1977-01-03 1979-06-26 Motorola, Inc. Memory address control device with extender bus
US4206503A (en) * 1978-01-10 1980-06-03 Honeywell Information Systems Inc. Multiple length address formation in a microprogrammed data processing system
US4224676A (en) * 1978-06-30 1980-09-23 Texas Instruments Incorporated Arithmetic logic unit bit-slice with internal distributed iterative control

Also Published As

Publication number Publication date
GB2081480B (en) 1984-03-28
US4463441A (en) 1984-07-31
DE3128816A1 (de) 1982-07-22
IT8148947A0 (it) 1981-07-22
BG33404A1 (bg) 1983-02-15
FR2487547A1 (fr) 1982-01-29
IT1171408B (it) 1987-06-10
GB2081480A (en) 1982-02-17
FR2487547B3 (Direct) 1983-05-20
JPS5790752A (en) 1982-06-05
IT8148947A1 (it) 1983-01-22

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