JPS5790752A - Register arithmetical device - Google Patents

Register arithmetical device

Info

Publication number
JPS5790752A
JPS5790752A JP56113793A JP11379381A JPS5790752A JP S5790752 A JPS5790752 A JP S5790752A JP 56113793 A JP56113793 A JP 56113793A JP 11379381 A JP11379381 A JP 11379381A JP S5790752 A JPS5790752 A JP S5790752A
Authority
JP
Japan
Prior art keywords
register
arithmetical device
arithmetical
register arithmetical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56113793A
Other languages
English (en)
Inventor
Kazabofu Kazabofu Nikora
Georugiefu Dakofusu Riyudomiru
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BITSUSHIYU MASHIINOOEREKUTOROT
BITSUSHIYU MASHIINOOEREKUTOROTEKUNICHIESUKII INST
Original Assignee
BITSUSHIYU MASHIINOOEREKUTOROT
BITSUSHIYU MASHIINOOEREKUTOROTEKUNICHIESUKII INST
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BITSUSHIYU MASHIINOOEREKUTOROT, BITSUSHIYU MASHIINOOEREKUTOROTEKUNICHIESUKII INST filed Critical BITSUSHIYU MASHIINOOEREKUTOROT
Publication of JPS5790752A publication Critical patent/JPS5790752A/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • G06F7/575—Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3828—Multigauge devices, i.e. capable of handling packed numbers without unpacking them

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Analysis (AREA)
  • Software Systems (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computing Systems (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
  • Complex Calculations (AREA)
  • Pharmaceuticals Containing Other Organic And Inorganic Compounds (AREA)
JP56113793A 1980-07-22 1981-07-22 Register arithmetical device Pending JPS5790752A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
BG8048568A BG33404A1 (en) 1980-07-22 1980-07-22 Registrating arithmetic device

Publications (1)

Publication Number Publication Date
JPS5790752A true JPS5790752A (en) 1982-06-05

Family

ID=3907804

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56113793A Pending JPS5790752A (en) 1980-07-22 1981-07-22 Register arithmetical device

Country Status (8)

Country Link
US (1) US4463441A (ja)
JP (1) JPS5790752A (ja)
BG (1) BG33404A1 (ja)
CS (1) CS560281A1 (ja)
DE (1) DE3128816A1 (ja)
FR (1) FR2487547A1 (ja)
GB (1) GB2081480B (ja)
IT (1) IT1171408B (ja)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58106636A (ja) * 1981-12-18 1983-06-25 Hitachi Ltd パイプライン演算装置
US5179734A (en) * 1984-03-02 1993-01-12 Texas Instruments Incorporated Threaded interpretive data processor
GB8517498D0 (en) * 1985-07-10 1985-08-14 Jesshope C R Data stack
JPH07113884B2 (ja) * 1985-12-28 1995-12-06 株式会社東芝 論理回路
US5261113A (en) * 1988-01-25 1993-11-09 Digital Equipment Corporation Apparatus and method for single operand register array for vector and scalar data processing operations
US5150469A (en) * 1988-12-12 1992-09-22 Digital Equipment Corporation System and method for processor pipeline control by selective signal deassertion

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3391390A (en) * 1964-09-09 1968-07-02 Bell Telephone Labor Inc Information storage and processing system utilizing associative memory
US3787673A (en) * 1972-04-28 1974-01-22 Texas Instruments Inc Pipelined high speed arithmetic unit
US4025771A (en) * 1974-03-25 1977-05-24 Hughes Aircraft Company Pipe line high speed signal processor
US4159520A (en) * 1977-01-03 1979-06-26 Motorola, Inc. Memory address control device with extender bus
US4206503A (en) * 1978-01-10 1980-06-03 Honeywell Information Systems Inc. Multiple length address formation in a microprogrammed data processing system
US4224676A (en) * 1978-06-30 1980-09-23 Texas Instruments Incorporated Arithmetic logic unit bit-slice with internal distributed iterative control

Also Published As

Publication number Publication date
IT1171408B (it) 1987-06-10
GB2081480B (en) 1984-03-28
BG33404A1 (en) 1983-02-15
CS560281A1 (en) 1984-11-19
IT8148947A0 (it) 1981-07-22
US4463441A (en) 1984-07-31
FR2487547B3 (ja) 1983-05-20
GB2081480A (en) 1982-02-17
FR2487547A1 (fr) 1982-01-29
DE3128816A1 (de) 1982-07-22

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