CS254161B1 - Method of semiconductor plate's first masking during semiconductor component production - Google Patents
Method of semiconductor plate's first masking during semiconductor component production Download PDFInfo
- Publication number
- CS254161B1 CS254161B1 CS855328A CS532885A CS254161B1 CS 254161 B1 CS254161 B1 CS 254161B1 CS 855328 A CS855328 A CS 855328A CS 532885 A CS532885 A CS 532885A CS 254161 B1 CS254161 B1 CS 254161B1
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- Czechoslovakia
- Prior art keywords
- semiconductor
- thatch
- metal
- dummy
- masking
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 52
- 238000000034 method Methods 0.000 title claims abstract description 13
- 230000000873 masking effect Effects 0.000 title claims abstract description 12
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 5
- 229910052751 metal Inorganic materials 0.000 claims abstract description 29
- 239000002184 metal Substances 0.000 claims abstract description 29
- 239000004577 thatch Substances 0.000 claims abstract description 15
- 238000000489 vacuum metal deposition Methods 0.000 claims 1
- 238000001771 vacuum deposition Methods 0.000 abstract description 2
- 230000015556 catabolic process Effects 0.000 abstract 1
- 239000007787 solid Substances 0.000 abstract 1
- 238000000151 deposition Methods 0.000 description 9
- 230000008021 deposition Effects 0.000 description 9
- 238000001465 metallisation Methods 0.000 description 2
- 238000000638 solvent extraction Methods 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- -1 for example Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000003032 molecular docking Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000010025 steaming Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- Electron Beam Exposure (AREA)
Abstract
Riešenie sa týká sposobu prvého maskovania polovodičovej došky pri výrobě polovodičové] súčiiastky diodového typu a rieši prblém zcsúladenia polohy plošného členenia polovodičové) došky s polohou kovu, ktorý sa na polovodičová došku s plošným členěním selektívne vákuovo nadeponuje cez otvory v mechanické] cloně. Podstata riešenia spočívá v tom, že najskor sa kov selektívne vákuovo nadeponuje na atrapu polovodičovej došky. Táto atrapa potom slúži ako vzor na nastavenie polohy prvého maskovania funkčnej polovodičovej došky. Nakoniec sa vykonává prvé maskovanie funkčnej polovodičovej došky, pričom poloha maskovania a tým aj poloha plošného členenia funkčnej polovodičovej došky zostáva nastavená podfa atrapy polovodičovej došky so selektívne vákuovo nadeponovaným kovom.The solution relates to the method of first masking semiconductor thatch in semiconductor manufacturing] diode-type components and solutions a consistent alignment of the areal layout semiconductor) thatch with metal positioning which is on a semiconductor thatch with flat dividing selectively vacuum through the holes in the mechanical shutter. nature The solution lies in the fact that the metal first is selective vacuuming on a semiconductor dummy thatch. This dummy then serves as a pattern for setting the first masking position functional semiconductor thatch. Finally the first functional mask is performed semiconductor thatch, with the masking position and hence the location of the area breakdown a solid semiconductor dock remains set according to dummy semiconductor thatch with selective vacuum-deposition metal.
Description
3 4 2541813 4 254181
Vynález sa týká spósobu prvého 'masko-vania polovodičové] došky p,rl výrobě polo-vodičové] súčiastky diodového typu a riešiproblém zosúladenia polohy plošného čle-nenia polovodičové]' došky s polohou kovu,ktorý se na polovodičovú došku s plošnýmčleněním selektívne vákuovo nadeponujecez otvorý v mechanické] cloně. Súčasfou postupu výroby polovodičové]súčiastky ]e depozícia kontaktových kovovna povrch polovodičové] došky. Vrstva kovuspravidla nie je žiadúca na celom povrchupolovodičové] došky a preto sa volí buď ho-mogénna depozícia: kovu a následovně foto-litografické operácie, pri ktorých sa kovo-vá vrstva z určitých oblastí odstráni, aleboselektívna depozícia kovu, pri ktorej sa ko-vová vrstva nadeponuje len na určité ob-lasti na polovodičovej doske.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for the first " masking " of a semiconductor diode-type component, and to the attenuation of the positioning of a semiconductor ' in the mechanical] aperture. Part of the semiconductor manufacturing process] is the deposition of the metal contact surface of the semiconductor] thatch. The metal rule layer is not desirable on the entire surface semiconductor, and therefore either the homogeneous metal deposition and the photo-lithography operations are selected in which the metal layer is removed from certain areas, but the metal deposition is metal-depleted. the layer only extends to certain areas on the semiconductor board.
Nevýhodou homogenně] depozície kovu afotolitografického spracovania nadepono-vanej vrstvy je zložitý postup a množstvo o-perácií, pri ktorých može dfijsť k mechanic-kému alebo chemickému poškodeniu polo-vodičové] štruktúry. Selektívna depozíciakovu sa dá realizovat depozíclou kovu z roz-toku (chemicky alebo galvanicky) alebo de-pozíciou vo vákuu cez mechanickú clonu,ktorá umožní depozíciu kovu len na mies-tach, kde má mechanická clona otvory.The disadvantage of the homogeneously deposition of metal and the photolithographic treatment of the superimposed layer is a complex process and a number of operations in which mechanical or chemical damage to the semi-conductor structure can occur. The selective deposition can be achieved by deposition of the metal from the solution (chemically or galvanically) or by de-positioning in a vacuum through a mechanical screen which allows the deposition of the metal only on the sites where the mechanical screen has openings.
Nevýhodou selektívnej depozície kovu zroztoku je obmedzený sortiment použitel-ných kovov a nutnost nadeponovanú vrstvukovu ďalej tepelne a chemicky spracovávať,pričom može; dójsť k poškodeniu polovodičo-vé] štruktúry.The disadvantage of the selective deposition of metal is the limited range of usable metals and the necessity of over-layering the heat further and chemically, while being able to; semiconductor structure can be damaged.
Selektívna depozícia kovu vo vákuu cezmechanickú clonu s otvormi je jednoduchámetoda selektívne] depozície, doteraz savšak,používá len v prípadoch, keď polovodi-čová doska nemá žiadne plošné členenie apolohu mechanické] clony nie je nutné na-stavovat do súladu s týmto členěním. Nevý-hodou selektívne] depozície kovu vo vákuucez otvory v mechanické] cloně teda je, ženie je použitelná (pre zložitosť nastaveniapolohy) na polovodičovej doske s plošnýmčleněním.The selective deposition of metal in a vacuum through a mechanical orifice plate is a simple selective method of deposition, but is still used only when the semiconductor plate has no surface partitioning and mechanical positioning does not need to be aligned with this partitioning. The disadvantage of the selective deposition of the metal in the vacuum through the openings in the mechanical orifice is therefore that the bearing is applicable (for the positioning complexity) on the semiconductor plate with the flattening.
Podstata vynálezu spočívá v sposobe pr-vého maskovania polovodičové] došky privýrobě polovodičové] súčiastky diodovéhotypu, pri ktorej sa využívá selektívna vákuo-vá depozícia kovu cez otvory v mechanic-ké] cloně.SUMMARY OF THE INVENTION The present invention is based on the method of first masking a semiconductor die for the production of a semiconductor diode-type component, wherein a selective vacuum deposition of metal is utilized through the openings in the mechanical diaphragm.
Sposob podlá vynálezu sa vyznačuje tým,že v prvom kroku postupu sa kov selektívnevákuovo nadeponuje na atrapu polovodičo-vé] došky. Táto atrapa so selektívne nade-ponovaným kovom potom slúži v druhomkroku postupu ako vzor na nastavenie po-lohy prvého maskovania funkčnej polovodi-čové] došky. V treťom kroku postupu sa vy-konává prvé maskovanie Jednotlivých funkč- ných polovodičových dosiek, pričom polohamaskovania a tým a] poloha plošného čle-nenia funkčných polovodičových dosiek zo-stáva nastavená podlá atrapy polovodičové]došky so selektívne vákuovo nadeponova-ným kovom. Výsledkom tohto postupu je, že každátakto nemaskovaná funkčná polovodičovádoska má polohu plošného členenia zhodnús polohou kovu, ktorý bol selektívne vákuo-vo nadeponovainý na atrapu polovodičové]došky. Ak sa na takúto funkčnú polovodičo-vú došku, selektívne nadeponuje kov za zhod-ných poďmienok, pri ktorých sa kov selek-tívne nadeponoval na atrapu polovodičové]došky, poloha tohoto kovu je v súlade splošným členěním funkčně] polovodičové]došky.The method according to the invention is characterized in that, in the first step of the process, the metal is selectively extruded onto the semiconductor dummy. This dummy with the selectively doped metal then serves as a pattern for setting the position of the first masking of the functional semiconductor that is in the second step of the process. In the third step of the process, the first masking of the individual functional semiconductor plates takes place, and the positioning of the functional semiconductor plates remains set according to the semiconductor dummy type with selectively vacuum-bonded metal. As a result of this process, each non-masked functional semiconductor wedge has a position of a surface pattern identical to that of a metal that has been selectively vacuum-bonded to the semiconductor dummy. If, for such a functional semiconductor thatch, the metal is selectively overloaded under the same conditions in which the metal is selectively superimposed on the semiconductor dummy, the position of the metal is consistent with that of the functional semiconductor.
Teda výhodou spósobu prvého maskova-nia polovodičovej došky podlá vynálezu je,že umožňuje použil selektívnu vákuovú de-pozíciu kovu cez otvory v mechanické] clo-ně na polovodičové] doske s plošným čle-něním. V konkrétnom případe sa spracováva kře-míková doska o priemere 0 45 mm s dvomarovinnými ploškami na obvode (fazetami)zvierajúcimi uhol 90°, ktoré slúžia ako do-razové plĎšky. Atrapa polovodičové] doškymá rovnaké rozměry ako funkčná polovodi-čová doska.Thus, the advantage of the method of the first masking of the semiconductor dock according to the invention is that it allows the use of a selective vacuum de-positioning of the metal through the apertures in the mechanical cell on the semiconductor sheet. In a particular case, a 0 45 mm diameter silicon wafer is processed with two-line pads on the periphery (facets) at an angle of 90 ° to serve as finishing pads. Semiconductor dummy has the same dimensions as a functional semiconductor board.
Mechanická clona s otvormi je vystřihnu-tá z molybdénového plechu hrůbky 0,15 mma má rovnako ako polovodičová doska aatrapa polovodičovej došky dorazové plošky.Najskor sa atrapa polovodičové] došky za-kryje mechanickou clonou s otvormi, vo vá-kuovom naparovacom zariadení sa,spolu do-tlačia ku trom dorazovým kolíkom a napa-ří sa na ne dobré viditelný kov, napříkladhliník. Potom sa atrapa polovodičové] doš-ky vloží do fotolitografického expozičnéhozariadenia, kde sa dotlačí ku trom dorazo-vým kolíkom a poloha fotolitograficke] mas-ky sa optickou cestou zosúladí s polohouplošiek kovu napařeného na atrapě. Polohanastavené] fotolitograficke] masky sa zaare-tuje. Jednotlivé funkčně polovodičové doš-ky sa potom vkladajú do fotolitografickéhoexpozičného zariadenia, kde sa dotláčajú kutrom dorazovým kolíkom a exponujú sa ceznastavená fotolitografickú masku. Funkčněpolovodičové došky potom absolvujú ďalšietechnologické operácie, pri ktorých sa tvo-ří požadovaná štruktúra. Poloha plošnéhočlenenia daná prvým maskováním sa všakuž nemení a pri posledně] operácii, keď sana funkčnú polovodičovú došku napaří cezotvory v mechanickej cloně kontaktový kov,je poloha napařených plóšiek kovu v súlades polohou kontaktových oblastí polovodi-čovej došky.The mechanical orifice plate is cut out from the 0.15 mma molybdenum sheet and has, like the semiconductor plate, a semiconductor dock stop plate. The semiconductor dummy is covered with a mechanical orifice with holes in the vacuum steaming device together with they press against the three stop pins and a good visible metal, for example, aluminum, is applied to them. Thereafter, the semiconductor dummy is placed in a photolithographic exposure apparatus where it is pushed to three stop pins and the position of the photolithographic mask is optically aligned with the metal dropper vapor deposited on the dummy. Half-set] photolithographic masks are included. The individual functionally semiconductor plates are then inserted into a photolithographic exposure device, where they are pushed by a stop pin and exposed through a set photolithographic mask. Functional semiconductor docking then undergoes additional technological operations, in which the required structure is formed. However, the positioning of the first camouflage blanking does not change and in the last operation, when the functional semiconductor that is blown through the openings in the mechanical shield contact metal, the position of the vaporized metal flats is in line with that of the contact areas of the semiconductor thatch.
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Application Number | Priority Date | Filing Date | Title |
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CS855328A CS254161B1 (en) | 1985-07-22 | 1985-07-22 | Method of semiconductor plate's first masking during semiconductor component production |
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CS855328A CS254161B1 (en) | 1985-07-22 | 1985-07-22 | Method of semiconductor plate's first masking during semiconductor component production |
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CS532885A1 CS532885A1 (en) | 1987-05-14 |
CS254161B1 true CS254161B1 (en) | 1988-01-15 |
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CS855328A CS254161B1 (en) | 1985-07-22 | 1985-07-22 | Method of semiconductor plate's first masking during semiconductor component production |
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1985
- 1985-07-22 CS CS855328A patent/CS254161B1/en unknown
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CS532885A1 (en) | 1987-05-14 |
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