CS224099B1 - Simple timer for long times - Google Patents

Description

The invention relates to the connection of a simple timer for long times.

The known long-time timers, about tens of seconds, use either a quiescent or quiescent circuit design with high-quality tantalum capacitors whose residual current is so small that it does not affect the reliable operation of the timer in the desired function. The disadvantage of these circuits is the need to use costly high-quality capacitors or a non-zero quiescent consumption, which is particularly bad for simple devices powered by built-in battery power sources, which emphasize long battery life.

The connection of the simple long time timer according to the invention consists of a flip-flop consisting of three transistors, one capacitor and five functional resistors. The capacitor is of the conventional electrolytic type with leakage current The idle current of the entire timer is zero.

The simple long time timer according to the invention is advantageous for the possibility of replacing expensive high-quality capacitors with conventional types of leakage current electrolytic capacitors, and also for its zero quiescent current consumption, saving the built-in battery of simple devices.

In the accompanying drawings, FIG. 1 shows the electrical connection of a timer according to the invention, FIG. 2 the electrical connection of its modification to achieve long times, and FIG.

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Simple timer for long periods of time according to the invention, fig ₀ l is formed by the monostable multivibrator, consisting of a feedback transistor £, an output transistor 6 and the eighth transistor blocking capacitor 10, an electrolytic current type of leakage current, together with the charging resistor j? generates circuit time functions. The base resistor 2 ensures that the output transistor 6 is closed in the quiescent state. The resistor 2 then generates a negative current feedback when the circuit is open,

In Figure 3 are shown timing diagrams of the input voltage U _s, U _W output voltage, the base-collector voltage of the voltage Ug, U ^ blocking voltage, the feedback voltage and the capacitor voltage U ^ _o idle timer circuit, all three transistors 4, 6 8 closed, the quiescent current drawn from the positive pole of the supply voltage is zero Ujj and also capacitor voltage U _c and the output voltage U is zero. The negative trigger input voltage _U applied to the input partition member 1 timer causes a voltage drop on the resistance of the base 2, a voltage drop U-base, and the opening 6. From the output transistor its collector, from which is extracted also the output voltage U _W is through the collector resistor J, as the feedback voltage U1 increases, the current is fed to the base of the feedback transistor which opens, the collector voltage U2 drops and begins to flow current from the base resistor 2 and the base of the output transistor 6 through the resistor j into the collector the current then flows through the emitter resistor 2 to the negative pole of the supply voltage U _Q , thus creating a blocking voltage U ^. The feedback transistor 6 and the output transistor 6 remain permanently open even after the negative starting pulse of the input voltage U _at <>

A continuous positive output voltage U appears at the timer output.

From the collector of the output transistor 6, current flows to the capacitors 10 via the charging resistor 2, while the blocking transistor 8 is still closed. The capacitor voltage U5 increases on the capacitors 10 until it reaches the value o at the pulse time JT

At this point, the blocking transistor 8 begins to open and the currents flowing through the charging resistor 3 ^are now divided into two parts.

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One part flows as a leakage current to the capacitor 10 and the other to the base of the blocking transistor 8. This opens after the opening time and closes its 4-way transistor emitter-base transistor 4 at the same time. It generates a negative current feedback that accelerates the closing of the feedback transistor. Its rapid closing causes a sharp drop in current through the feedback resistor a and the base of the output transistor 6 that closes and the output voltage _Uw drops sharply to zero. At the moment of this drop, the capacitor 10 starts to discharge via the emitter-base transition of the blocking transistor 8 to the emitter resistor 11. For the opening time falls below the capacitor voltage hodnotuJJqjjq, the blocking transistor 8 is closed and the capacitor 10 now discharges to zero volts through its own leakage resistance with a time constant T ^ _o The timer circuit is restored the initial rest state. The 'voltage' knobs should be replaced by the collector-zmtbr in the system

The described timer is suitable for tens of seconds. To achieve long times, up to hundreds of seconds, the described timer can be used, replacing the blocking transistor 8, as shown in Fig. 2, by a double transistor 11 and 12. % as adjustable due to the large capacitance tolerances ε of the common electrolytic capacitors. The maximum value of the charging resistor 9 is limited by the current that must flow to the base of the blocking transistor 8 to keep it saturated.

Equivalent wiring of the timer to trigger a positive input module 2 GUI jL 2 c create a substitution of the polcrity of all voltages, transistors and capacitor.

The simple long time timer according to the invention can be used in automation, signaling, communication and security technology.

Claims (2)

A simple long-time timer consisting of a monostable flip-flop consisting of three transistors, one capacitor and five functional resistors, characterized in that the input (U _v ) is connected to one end of the base resistor (2) via the separating member (1), connected to the other end of the positive voltage supply pole further coupled to one end of the feedback resistor (3), connected to the other end of the feedback transistor collector (4) «also coupled to the output transistor (6) base whose emitter is connected to the positive voltage supply pole ( Whose collector is connected to one end of the collector resistor (7) and one end of the charging resistor (9) and the output voltage terminal (U ^), the other end of the collector resistor (7) being connected to the base of the feedback transistor (4) and a collector of the blocking transistor (8) and the other end of the charging resistor (9) is connected to the base of the blocking transistor (8) and one pole of capacitors (10), the other pole of which is connected to the negative pole of the supply voltage ( _UQ ), the emitters of the feedback transistor (4) and the blocking transistor (8) being connected together and at one end of the emitter resistor. (5), the other end of which is connected to the negative pole of the supply voltage (U _o ). 2 drawings