CN212277906U

CN212277906U - Time delay turn-off circuit, power supply control device and gate system

Info

Publication number: CN212277906U
Application number: CN202022177669.1U
Authority: CN
Inventors: 肖国庆; 陈志金
Original assignee: Shenzhen Jiayu Mechatronic Co ltd
Current assignee: Shenzhen Jiayu Mechatronic Co ltd
Priority date: 2020-09-28
Filing date: 2020-09-28
Publication date: 2021-01-01
Anticipated expiration: 2030-09-28

Abstract

The embodiment of the application provides a time delay shutoff circuit, power supply control device and floodgate machine system, and this time delay shutoff circuit includes: the charging and discharging control unit is connected with the charging and discharging unit, the reset end of the timing chip is connected with the triggering unit, and the triggering unit is used for accessing an external triggering signal; the discharge end or the output end of the timing chip is connected with the switch control end of the charge-discharge control unit, and the switch control end is used for controlling the charge or discharge of the charge-discharge unit; the trigger end and the threshold end of the timing chip are connected with the voltage detection end of the charge-discharge unit after being in short circuit; the output end of the timing chip is used for being connected with a controlled object, and the delay turn-off circuit is used for controlling the controlled object to be turned on and then turned off in a delayed manner after receiving an external trigger signal. The scheme can realize the control of the controlled object which is switched on and automatically closed after a period of time delay, and has the advantages of simple structure, low cost, strong practicability and the like.

Description

Time delay turn-off circuit, power supply control device and gate system

Technical Field

The application relates to the technical field of circuit design, in particular to a delay turn-off circuit, a power supply control device and a gate system.

Background

In some scenarios, for example, when the system power supply of the gate is powered down, in order to prevent personnel from being unable to pass through the gate in time, it is necessary to control the gate to be temporarily turned on and then turned off when the gate is powered down. In the existing schemes, some of the existing schemes utilize a special controller and a special driver to realize delayed turn-off, so that the cost is high, and the steps of wiring, writing a corresponding control program, burning the program and the like are required, so that the existing schemes are complicated; some schemes have no automatic power-off function, and only can supply power continuously, namely once the power supply is switched on, the power supply cannot be automatically switched off, so that the problem of uncontrollable power supply exists.

SUMMERY OF THE UTILITY MODEL

In view of the above, the present application provides a time-delay shutdown circuit, a power supply control device and a gate system to overcome the deficiencies in the prior art.

An embodiment of the present application provides a delay shutdown circuit, including: the charging and discharging control unit is connected with the charging and discharging unit;

the reset end of the timing chip is connected with a trigger unit, and the trigger unit is used for accessing an external trigger signal; the discharge end or the output end of the timing chip is connected with the switch control end of the charge-discharge control unit, and the switch control end is used for controlling the charge or discharge of the charge-discharge unit; the trigger end and the threshold end of the timing chip are connected with the voltage detection end of the charge-discharge unit after being in short circuit; the output end of the timing chip is used for being connected with a controlled object, and the delay turn-off circuit is used for controlling the controlled object to be turned on and then turned off in a delayed manner after receiving an external trigger signal.

In one embodiment, the charge and discharge control unit comprises a first resistor, a second resistor and a switching tube, wherein one end of the first resistor and the first end of the switching tube are respectively used for connecting a power supply, the other end of the first resistor is respectively connected with the second end of the switching tube and one end of the second resistor, the other end of the second resistor is connected to the discharge end or the output end of the timing chip, and the third end of the switching tube is connected with the charge and discharge unit.

In one embodiment, the charging and discharging unit includes a third resistor, a fourth resistor, a first capacitor and a second capacitor, one end of the third resistor is connected to one ends of the charging and discharging control unit and the first capacitor, the other end of the first capacitor is connected to one end of the fourth resistor, the respective other ends of the third resistor and the fourth resistor are grounded, the second capacitor is connected to two ends of the fourth resistor in parallel, and one end of the fourth resistor is connected to the trigger terminal of the timing chip as a voltage detection terminal.

In one embodiment, the value of the first capacitance is greater than twice the value of the second capacitance.

In one embodiment, the trigger unit includes a trigger signal incoming end, a fifth resistor and a third capacitor, one end of the fifth resistor is used for connecting a power supply, the trigger signal incoming end is respectively connected with the other end of the fifth resistor and the reset end of the timing chip, one end of the third capacitor is connected with the trigger signal incoming end, and the other end of the third capacitor is grounded.

In one embodiment, the delayed turn-off circuit further comprises: and the cathodes of the first diodes are connected with the discharge end of the timing chip, the anode of the first diode is connected with the other end of the second resistor, and the discharge end of the timing chip is also used for connecting another controlled object.

In one embodiment, the delayed turn-off circuit further comprises: and the discharge end of the timing chip is connected with another controlled object after passing through the second diode arranged in the reverse direction.

In one embodiment, the timing chip comprises a voltage division circuit formed by connecting three equal-value resistors in series, a first comparator, a second comparator, a trigger, a triode and an inverter;

one end of the voltage division circuit is used as a power supply end of the timing chip, and the other end of the voltage division circuit is used as a grounding end of the timing chip; the reverse end of the first comparator is connected to the 2/3 voltage division potential point of the voltage division circuit and serves as a voltage control end of the timing chip, and the forward end of the first comparator serves as a threshold end of the timing chip; the positive end of the second comparator is connected to the 1/3 voltage division potential point of the voltage division circuit, and the reverse end is used as the trigger end of the timing chip; the output ends of the first comparator and the second comparator are respectively connected with two input ends of the trigger, the output end of the trigger is respectively connected with the base electrode of the triode and the input end of the reverser, the reset end of the trigger is used as the reset end of the timing chip, the emitting electrode of the triode is grounded, the collecting electrode of the trigger is used as the discharge end of the timing chip, and the output end of the reverser is used as the output end of the timing chip.

Another embodiment of the present application provides a power supply control device, which includes the above-mentioned delay shutdown circuit and a standby power supply, wherein the delay shutdown circuit is connected to the standby power supply, the standby power supply is used for connecting to a load, and the delay shutdown circuit is used for controlling the standby power supply to supply power to the connected load and to power off in a delayed manner when receiving an external trigger signal.

In one embodiment, the backup power source is a super capacitor or a battery.

The power supply control device is connected with the gate, and the power supply control device is used for controlling the standby power supply to supply power to the gate and delaying power off when receiving an external trigger signal.

The embodiment of the application has the following advantages:

the delay turn-off circuit can realize the delay turn-off after the pilot-on of a controlled object connected with the circuit when receiving an external trigger signal based on the timing chip combined with the charge-discharge control and the charge-discharge unit, and the like, and the whole circuit can be restored to an initial state after the turn-off, so that the uncontrollable problem that the circuit cannot be automatically turned off once some existing schemes are turned on can be solved, and the circuit can be triggered to be turned on and turned off in a delayed manner only by extremely small current because the external trigger is input from the reset end of the timing chip, and the requirements on the strength and time of the external trigger signal can be reduced; in addition, compared with a scheme of realizing time delay turn-off by using a special controller and the like, the circuit has the characteristics of greatly reduced cost, simple circuit structure, strong practicability, suitability for popularization and application and the like.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.

Fig. 1 shows a first structural schematic diagram of a time delay shutdown circuit according to an embodiment of the present application;

FIG. 2 is a schematic diagram illustrating a timing chip of the delayed turn-off circuit according to an embodiment of the present application;

fig. 3 is a schematic structural diagram illustrating a charge/discharge control unit and a charge/discharge unit of the delayed turn-off circuit according to an embodiment of the present application;

FIG. 4 is a diagram illustrating a second structure of the delayed turn-off circuit according to the embodiment of the present application;

fig. 5 is a schematic structural diagram illustrating a power supply control apparatus according to an embodiment of the present application;

fig. 6 shows a schematic structural diagram of a gate system according to an embodiment of the present application.

Description of the main element symbols:

10-a time-delay turn-off circuit; 110-a trigger unit; 120-a charge and discharge control unit; 130-a charge and discharge unit; d1 — first diode; d2 — second diode; q1-switching tube; r1 — first resistance; r2 — second resistance; r3 — third resistance; r4-fourth resistor; r5-fifth resistor; c1 — first capacitance; c2 — second capacitance; c3 — third capacitance; c4-ground capacitance; 20-a power supply control device; 210-a backup power supply; 30-a gate system; 310-gate machine.

Detailed Description

Reference will now be made in detail to the embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are exemplary only for the purpose of explaining the present application and are not to be construed as limiting the present application.

It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only.

In this application, unless expressly stated or limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can include, for example, fixed connections, removable connections, or integral parts; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the templates is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Example 1

Referring to fig. 1, the present embodiment provides a time-delay shutdown circuit 10 designed based on a timing chip, which can be applied to various systems requiring time-delay shutdown control, for example, when a load suddenly loses power, the time-delay shutdown circuit 10 can be used to control a standby power supply to temporarily supply power and shut down the standby power supply after a period of time after power supply, so as to solve the problem of temporary power failure of the load. The time-delay shutdown circuit 10 will be described in detail below.

Exemplarily, the time-delay shutdown circuit 10 includes a timing chip, a trigger unit 110, a charge and discharge control unit 120, and a charge and discharge unit 130, wherein the charge and discharge control unit 120 is connected to the charge and discharge unit 130. In this embodiment, the timing chip includes a voltage divider circuit formed by connecting 3 equivalent resistors in series, a first comparator, a second comparator, a flip-flop, a triode, and an inverter, and the resistance of the equivalent resistor may be selected to be 5K Ω. As shown in fig. 2, two ends of the voltage divider circuit are respectively used for connecting an external power supply and a power ground, that is, one end of the voltage divider circuit is used as a power supply terminal VCC of the timing chip, and the other end is used as a ground terminal GND of the timing chip. The reverse end of the first comparator is connected to the 2/3 voltage division potential point (namely, 2/3VCC potential point) of the voltage division circuit and serves as the voltage control end CONT of the timing chip; the positive end of the timing chip is used as a threshold end THRES of the timing chip; the forward end of the second comparator is connected to 1/3 voltage division potential points (namely 1/3VCC potential points) of the voltage division circuit, and the reverse end of the second comparator is used as a trigger end TRIG of the timing chip; the output ends of the two comparators are respectively connected to the two input ends of the trigger. Typically, the flip-flop is an RS flip-flop, and the output of the first comparator is connected to the R pin, and the output of the second comparator is connected to the S pin. A reset pin of the trigger is used as a reset end REST of the timing chip, and output pins of the trigger are respectively connected to a base electrode of the triode and an input end of the inverter; the emitter of the triode is grounded, and the collector of the triode is used as the discharge end DISCH of the timing chip; the output end of the inverter is used as the output end OUT of the timing chip.

It is understood that the type of the above-mentioned timing chip is not limited, for example, the timing chip may be a 555 series chip, such as NE555, LM555, etc., or may be another type chip capable of directly replacing the function of the 555 chip, such as MC1455, etc.

In one embodiment, as shown in fig. 1, a reset terminal of the timing chip is connected to the trigger unit 110, and the trigger unit 110 is configured to access an external trigger signal; the discharge end or the output end of the timing chip is connected with the switch control end of the charge and discharge control unit 120, and the switch control end is used for controlling the charge or discharge of the charge and discharge unit 130; the trigger end and the threshold end of the timing chip are connected with the voltage detection end of the charge and discharge unit 130 after being in short circuit; the output end of the timing chip is used for connecting a controlled object. For other pin terminals of the timing chip, for example, the power terminal is connected to the operating power VCC, the ground terminal is connected to ground, and the voltage control terminal can be connected to ground through a ground capacitor C4. The delay turn-off circuit 10 is used for controlling the controlled object to be turned on first and then turned off in a delay manner after the circuit receives an external trigger signal.

In this embodiment, the main work flow of the circuit includes: after the reset end receives a trigger signal, the timing chip resets, level overturning occurs inside the chip at the moment, the overturned level is used for controlling a switching tube in a charge-discharge control unit to be switched on so as to realize capacitor charging of the charge-discharge unit, then the capacitor starts to discharge, when the voltage is lower than a preset threshold value, level overturning occurs inside the timing chip again so as to switch off the switching tube, and after the capacitor discharges completely, the circuit recovers to an initial state.

Generally, before an external trigger signal does not arrive, the output end of the timing chip outputs a high level for controlling an external object, when the reset end receives a low level trigger signal, the chip is reset, the output end outputs a low level at the moment, and meanwhile, the discharge end is pulled down by the internal circuit to output a low level. Accordingly, when the discharging end outputs a low level, the charging and discharging control unit 120 controls the switching tube therein to be turned on, so that the power supply can rapidly charge the capacitor in the charging and discharging unit 130, and the capacitor is almost instantly filled due to the current amplification effect of the switching tube. When the capacitor is fully charged, the output end of the timing chip outputs low level and the discharge end stops outputting low level. It can be understood that even if a trigger signal of a very short time is input from the outside, before the trigger signal is cancelled, the output end of the timing chip and the discharge end can realize low level output when triggered, then, the capacitor in the charge and discharge unit 130 starts to discharge, when the discharge voltage is smaller than the preset threshold, the output end outputs high level, because the discharge end is open-circuit output of the collector, the discharge end becomes no output, at this time, the switch tube is turned off, and after the circuit is completely discharged, the whole circuit is restored to the initial state.

It can be understood that, in the whole process, the time-delay shutdown circuit realizes 1 charge and 1 discharge per se, while the existing scheme can only realize 1 charge or 1 discharge and often cannot automatically recover to the initial state before triggering. In addition, in the prior art, an external trigger signal is often input from a trigger end of the timing chip, but the external trigger signal is input from a reset end of the timing chip in the embodiment, so that triggering can be realized only by a very small current, compared with the existing delay triggering technology, requirements of the delay turn-off circuit of the embodiment on the strength and time of the external trigger signal are not so strict, and charging and discharging control is realized by utilizing internal level inversion during resetting of the timing chip, so that any complex programming processing is not needed, the structure is simple, the cost is low, and the like.

Exemplarily, as shown in fig. 3, the charge and discharge control unit 120 includes a first resistor R1, a second resistor R2, and a switch tube Q1, wherein one end of the first resistor R1 and a first end of the switch tube Q1 are respectively connected to a power supply, the other end of the first resistor R1 is respectively connected to a second end of the switch tube Q1 and one end of the second resistor R2, the other end of the second resistor R2 is connected to a discharge end or an output end of the timing chip, and a third end of the switch tube Q1 is connected to the charge and discharge unit 130. Generally, the discharge end of the timing chip is used for connecting the charge and discharge control unit 120, and the output end is used for connecting the controlled object. Of course, the output terminal may also be used to connect the charging and discharging control unit 120 for control.

The first resistor R1 and the second resistor R2 form a voltage divider circuit, for example, a transistor Q1, a base of which is connected to the divided voltage, an emitter of which is connected to the power supply, and a collector of which is connected to the charging and discharging unit 130. The charging control process is that when the discharging end of the timing chip is pulled down, the base electrode inputs a low level, and at the moment, the triode is switched from the original off state to the on state, so that the power supply can charge the capacitor in the charging and discharging unit 130. On the contrary, when the discharge end is in a suspended state without output, the triode is turned off at the moment.

It can be understood that the discharge end of the open collector output is used to control the conduction of the switching tube Q1, so as to control the charging and discharging unit 130, and prevent the signal from being locked and unable to return to the initial state. It should be understood that the PNP transistor is only an example, and the type is not limited thereto, and if an NPN transistor is used, the PNP transistor can be adjusted slightly to control the switching transistor Q1 accordingly by using the low level of the discharge end. Of course, the switching function may be implemented by other devices such as MOS transistors, which is not limited herein.

Exemplarily, as shown in fig. 3, the charge and discharge unit 130 includes a third resistor R3, a fourth resistor R4, a first capacitor C1, and a second capacitor C2, wherein one end of the third resistor R3 is connected to one ends of the charge and discharge control unit 120 and the first capacitor C1, the other end of the first capacitor C1 is connected to one end of the fourth resistor R4, the other ends of the third resistor R3 and the fourth resistor R4 are grounded, the second capacitor C2 is connected in parallel to two ends of the fourth resistor R4, and one end of the fourth resistor R4 is connected to the trigger end of the timing chip as a voltage detection end.

During the charging process, the power supply will rapidly charge the first capacitor C1 and the second capacitor C2, and since the charging time is extremely short, the full voltage of the second capacitor C2 is equal to VCC C1/(C1+ C2) regardless of the triode voltage drop. When the voltage of the second capacitor C2 reaches the full voltage, the trigger terminal and the threshold terminal of the timing chip will get a high level, and the output terminal and the discharge terminal will maintain a low level state. Then, after the second capacitor C2 is fully charged, the second capacitor C2 starts to enter a discharge state due to the dc blocking effect of the first capacitor C1 and is discharged through the fourth resistor R4. Still taking the above example, when the voltage discharge of the second capacitor C2 is smaller than the preset threshold (e.g. 1/3 VCC), the output terminal will output a high level and the discharge terminal will not output a low level any more, and accordingly, the voltage connected to the base is high, so the triode will be turned off. Then, the second capacitor C2 still continues to be completely discharged through the fourth resistor R4, and the first capacitor C1 is completely discharged through the third resistor R3 and the fourth resistor R4, and after the complete discharge, the circuit returns to the initial state. In the whole process, a high level is output from the initial output end, a low level is output during triggering, the low level is maintained for a period of time after triggering, namely the period of time that the voltage of the second capacitor C2 is higher than 1/3VCC, and finally the state is changed into the initial high level state, namely the period of time from the first high level to the second high level realizes delay control.

In some applications requiring long delay (more than a few seconds), in order to fully charge and discharge a capacitor, requirements are made on the current and the time of a trigger signal, and the delay time of a circuit is influenced by the insufficient strength and time of the trigger signal. It should be noted that the delay shutdown circuit of this embodiment has no strict requirements on the strength and time of the externally input trigger signal, and the delay time is not affected. This is because the trigger signal is input from the reset terminal of the chip, and only a very small current is required. Typically, the current is indicated to be about 0.1mA as is known in the specification for the 555 series chip. And then, the timing chip is reset after being triggered, and at the moment, the charging operation is controlled by the discharging end of the chip and is amplified by the switching tube, so that the charging current intensity of the charging capacitor can be ensured. Furthermore, due to the blocking effect of the first capacitor C1, the second capacitor C2 can directly enter a discharging state after being fully charged, and the influence of the triggering time of the delay circuit is reduced. Of course, if the trigger signal is continuously present, the timing chip will always maintain the corresponding output state during triggering. At this time, the triggering duration can be controlled to be smaller than the delay duration. The time delay turn-off circuit starts timing from the trigger time, so that the influence of the trigger time length on the time delay time length is reduced.

In this embodiment, the value of the first capacitor C1 is greater than twice the value of the second capacitor C2. According to the internal working logic of the trigger terminal and the threshold terminal of the timing chip, since the timing chip includes the voltage dividing circuit formed by 3 5K Ω resistors, the voltage of the trigger terminal will be compared with the divided voltage of 1/3VCC, and the voltage of the threshold terminal will be compared with the divided voltage of 2/3 VCC. By setting the two capacitors to be in the multiple relation, the voltage of the second capacitor C2 after the circuit is triggered can be higher than 2/3VCC, and normal triggering and time delay of the circuit are further ensured.

Exemplarily, as shown in fig. 3, the trigger unit 110 includes a trigger signal access terminal, a fifth resistor R5 and a third capacitor C3, wherein one end of the fifth resistor R5 is used for connecting a power supply, the trigger signal access terminal is respectively connected to the other end of the fifth resistor R5 and the reset terminal of the timing chip, one end of the third capacitor C3 is connected to the trigger signal access terminal, and the other end of the third capacitor C3 is grounded. It can be understood that the third capacitor C3 can function to filter out the ripple interference, so as to ensure the validity and stability of the trigger signal input to the timing chip.

In the above-mentioned time-delay shutdown circuit 10, since the discharge end of the timing chip and the output end have the same level inversion change during the reset process, the discharge end or the output end can be used to connect the charge and discharge control unit 120 or an external controlled object. In one embodiment, the discharge end is used for controlling the switching tube Q1 in the charge and discharge control unit 120, and the output end is used for connecting an external controlled object. In the second embodiment, the output terminal is used for controlling the switching tube Q1, and the discharge terminal is used for an externally connected controlled object. In addition, in the third embodiment, the delay shutdown circuit 10 may also perform signal multiplexing on the discharge end.

Exemplarily, as shown in fig. 4, when the discharging terminal is already used to control the switching tube Q1, if it is further required to use the discharging terminal to control other controlled objects when outputting a low level, the delayed turn-off circuit 10 further includes: the positive electrode of the first diode D1, the positive electrode of the first diode D1 are connected with the second resistor R2, and the negative electrode of the first diode D1 is connected with the discharge end of the timing chip and is also used for being connected with another controlled object. It can be understood that the first diode D1 is provided to prevent the signal in another controlled object from affecting the state of the switching tube Q1 in the charge and discharge control unit 120.

Alternatively, when the discharge end of the timing chip is also used for connecting to the other controlled object, the second diode D2 may be arranged according to actual needs, as shown in fig. 3, the discharge end of the timing chip is simultaneously connected to the cathodes of the first diode D1 and the second diode D2, and the anode of the second diode D2 is used for the other controlled object, that is, the discharge end of the timing chip is connected to the other controlled object after passing through the second diode D2 arranged in the reverse direction.

The time delay turn-off circuit of the embodiment is used for realizing time delay turn-off after the pilot switch-on of the circuit based on the timing chip in combination with the charging and discharging control unit, the charging and discharging unit and the like, and the whole circuit is restored to the initial state after the turn-off. Because most of the existing delay circuit schemes delay a period of time after receiving a trigger signal and then output a specific signal but cannot return to the initial state, the delay switching-off circuit often cannot realize the delay switching-off after the pilot switch-on of the circuit, and the delay switching-off circuit can not only solve the uncontrollable problem that the existing schemes cannot automatically switch off once switched on, but also has no strict requirements on the strength and the time of an externally input trigger signal, and the delay time is not influenced; on the other hand, compare the scheme that utilizes special controller etc. to realize the time delay shutoff, cost greatly reduced, circuit structure is simple, and the practicality is strong, is suitable for popularization and application etc..

Example 2

Referring to fig. 5, the present embodiment provides a power supply control device 20, and exemplarily, the power supply control device 20 includes: a backup power supply 210 and the delay shutdown circuit 10 of embodiment 1, wherein the delay shutdown circuit 10 is connected to the backup power supply 210. In one embodiment, backup power source 210 is used to connect to a load; alternatively, the time-delay shutdown circuit 10 is located between the backup power supply 210 and the connected load. It is understood that the connection manner between the three is not limited, as long as the delayed turn-off circuit 10 can be used to control the backup power supply 210 to supply power to the connected load and to cut off power with a delay when receiving an external trigger signal.

For example, the external trigger signal may be a system power down signal, such that when the delayed turn-off circuit 10 receives the system power down signal, the standby power supply 210 is controlled to be connected to the load for temporarily supplying power to the load, and after a period of time, the standby power supply 210 is controlled to be disconnected to stop supplying power to the load. The backup power source 210 may be, for example, but not limited to, a super capacitor, a storage battery, or the like. The load may be any electrical device that can be powered by both the system power source and the backup power source 210.

It is understood that the external trigger signal can be set according to actual needs, and is not limited herein. In addition, the options of the delayed turn-off circuit 10 in the above embodiments are also applicable to the gate system 30, and therefore will not be described in detail herein.

Referring to fig. 6, the present application further provides a gate system 30, including the above power supply control device 20 and the gate 310, wherein the power supply control device 20 is connected to the gate 310, and the power supply control device 20 is configured to control the standby power supply 210 to supply power to the gate 310 and perform a delayed power-off when receiving an external trigger signal. For example, if the external trigger signal is a system power-off signal, the power supply control device 20 may temporarily turn on the gate 310 when the system is powered off. It is understood that the alternatives of the power supply control device 20 in the above embodiments are also applicable to the gate system 30, and therefore will not be described in detail herein.

In all examples shown and described herein, any particular value should be construed as merely exemplary, and not as a limitation, and thus other examples of example embodiments may have different values.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.

The above examples are merely illustrative of several embodiments of the present application, and the description is more specific and detailed, but not to be construed as limiting the scope of the present application. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application.

Claims

1. A time-delay shutdown circuit, comprising: the timing chip, the trigger unit, the charge and discharge control unit and the charge and discharge unit, the charge and discharge control unit is connected with the charge and discharge unit,

the reset end of the timing chip is connected with the trigger unit, and the trigger unit is used for accessing an external trigger signal; the discharge end or the output end of the timing chip is connected with the switch control end of the charge and discharge control unit, and the switch control end is used for controlling the charge and discharge of the charge and discharge unit; the trigger end and the threshold end of the timing chip are connected with the voltage detection end of the charge and discharge unit after being in short circuit; the output end of the timing chip is used for being connected with a controlled object, and the delay turn-off circuit is used for controlling the controlled object to be turned on and then turned off in a delayed manner after receiving the external trigger signal.

2. The time-delay turn-off circuit of claim 1, wherein the charge and discharge control unit comprises a first resistor, a second resistor and a switching tube, one end of the first resistor and the first end of the switching tube are respectively used for connecting a power supply, the other end of the first resistor is respectively connected with the second end of the switching tube and one end of the second resistor, the other end of the second resistor is connected to the discharge end or the output end of the timing chip, and the third end of the switching tube is connected with the charge and discharge unit.

3. The time-delay turn-off circuit according to claim 1 or 2, wherein the charge and discharge unit includes a third resistor, a fourth resistor, a first capacitor and a second capacitor, one end of the third resistor is connected to one end of the charge and discharge control unit and one end of the first capacitor, the other end of the first capacitor is connected to one end of the fourth resistor, the other ends of the third resistor and the fourth resistor are grounded, the second capacitor is connected in parallel to two ends of the fourth resistor, and the one end of the fourth resistor is connected to the trigger end of the timing chip as the voltage detection end.

4. The time delay shutdown circuit of claim 3, wherein a value of the first capacitance is greater than twice a value of the second capacitance.

5. The time-delay turn-off circuit of claim 1, wherein the trigger unit comprises a trigger signal access terminal, a fifth resistor and a third capacitor, one end of the fifth resistor is used for connecting a power supply, the trigger signal access terminal is respectively connected to the other end of the fifth resistor and the reset terminal of the timing chip, one end of the third capacitor is connected to the trigger signal access terminal, and the other end of the third capacitor is grounded.

6. The delayed turn-off circuit of claim 2, further comprising: and the cathodes of the first diodes are connected with the discharge end of the timing chip, the anode of the first diode is connected with the other end of the second resistor, and the discharge end of the timing chip is also used for connecting another controlled object.

7. The delayed turn-off circuit of claim 6, further comprising: and the discharge end of the timing chip is connected with the other controlled object after passing through the second diode arranged in the reverse direction.

8. The time-delay turn-off circuit of claim 1, wherein the timing chip comprises a voltage division circuit formed by connecting three equal-value resistors in series, a first comparator, a second comparator, a trigger, a triode and an inverter;

9. A power supply control device, comprising the delayed turn-off circuit as claimed in any one of claims 1 to 8, and a backup power supply, the delayed turn-off circuit being connected to the backup power supply, the backup power supply being used for connecting a load, the delayed turn-off circuit being used for controlling the backup power supply to supply power to the connected load and to cut off power with a delay when an external trigger signal is received.

10. A gate system comprising the power supply control device of claim 9 and a gate, wherein the power supply control device is connected to the gate, and the power supply control device is configured to control the backup power supply to supply power to the gate and delay power off when receiving an external trigger signal.