CS213930B1 - Circuit circuitry for evaluating the variable frequency divider ratio - Google Patents

Abstract

The purpose of the invention is to create a circuit that supplements the existing variable frequency dividers with some special properties. It is implemented by arranging a preselectable frequency divider in such a way that it allows its cyclic preselection via a register. The register records the resulting states of the preselected counter in cycles during which the frequency of the divided pulses is evaluated. The counter can operate bidirectionally and by setting the preselection and counting direction we obtain the lower or upper limit division ratio. The input of the counter is a series of pulses adjusted by a fixed divider and they correspond to the frequency of the divided signal for the cycle time given by the pulse generator. Between individual cycles, the control circuits reset and set the individual circuits.

Description

The invention relates to a circuit for the evaluation and automatic control of the dividing ratio of a variable frequency divider as a function of the frequency of the split signal, with the possibility of preselecting the limit dividing ratio.

Previously known systems employing variable frequency splitters operate either with a fixed split ratio or with a programmable split ratio.

For programmable dividers, predefined counters are mainly used. Changing the state of the divider setting inputs by the control circuit during counting then makes the fixed divider programmable. Divider programming is controlled by the algorithm. The disadvantage of these circuits is that they do not use the frequency information of the split signal to control the split ratio.

The aforementioned disadvantages are avoided by connecting a circuit for evaluating the dividing ratio of a variable frequency divider as a function of the frequency of the split signal according to the invention, characterized in that the pulse sensor output is connected to the first input of the programmable divider and is connected to a first input of a blocking gate whose output is connected to a first input of a preset counter whose output is connected to a first register input whose output is connected to a second input of a programmable divider whose output is the output of the entire circuit; connected to the second input of the interlock circuit and at the same time to the input of the control circuit, the first output of which is connected to the second input of the preselected counter and the second output of which is connected to the second register input.

The biggest advantage is the direct dependence of the dividing ratio on the input signal frequency adjustable within wide limits, another advantage is the possibility of setting the limit dividing ratio using a preset counter and a divider with a fixed but selectable dividing ratio. These circuits, together with a tunable pulse generator, give the circuit a wide choice of split or ratio.

The circuit according to the invention is apparent from the attached block diagram.

The circuit according to the invention consists of a pulse transducer 2, a fixed dividing divider 2, a blocking throat 2 of a preset counter 2 of a programmable divider register 6, a pulse generator 6 and a control circuit.

The funcoe according to the invention is such that the output signal from the pulse transducer 2 is applied to a divider input with a fixed selectable split ratio 2. Thus, a suitably reduced pulse frequency is routed via a blocking circuit 2 to a preset counter 4 input. or backwards.

For the duration of the clock pulse, the counter changes its state until the input signal is blocked. The final state of the counter 6 is transferred to the register 2 during the blocking of the input signal ^and maintained its output for the next clock pulse from the generator. Output state of the register 2 circuit £. At the same time, the pulses from the pulse sensor 2 are fed to the input of the programmable divider 2 which, for the 213930, leads to the actual division of the input pulses.

The above-described circuit for evaluating the dividing ratio of the variable frequency divider as a function of the frequency of the input signal according to the invention can be used for roller thickness controllers of the rolling mill using circuitry to register analog quantities with re-equipping. In particular, rolling mills for cold rolling of sheet metal, for example, twenty-cylinder mills, in which information on changes in the inlet waist thickness can be used to control the erection of the stool, and where the waist thickness and waist length sensors can be placed in front of the mill. Circuit wiring allows you to control the moment of selecting information about the input thickness of the waist depending on the waist speed.

Claims (2)

OBJECT OF THE INVENTION Circuit for evaluating the dividing ratio of the variable frequency divider as a function of the signal frequency, characterized in that the output of the pulse encoder ζΐ) is connected to the first input of the programmable divider (6) and to the input of the divider with a fixed divider. (2) whose output is connected to the first input of the blocking gate (3), whose output is connected to the first input of the preset counter (4), whose output is connected to the first register register (5), whose output is connected to the second programmable input and that the pulse generator output (7) is connected to the second input of the blocking gate (3) and simultaneously to the input of the control circuit (8), the first output of which is connected to the second input of the preset counter (4) and the second output is connected to the second register input (5).