CN87106288A - The transistor logic coupling circuit of reverse operation - Google Patents

Abstract

The transistor logic coupling circuit circuit of reverse operation, the polysilicon MOS that adopts polycrystalline Schottky or the input of polycrystalline diode and polysilicon resistance or drain-gate to connect altogether, the polysilicon MOS of grid ground connection is as load, plane V-shaped groove such as employing in the making, vertical channel and air insulated technology, extensively adopt self-registered technology, reduce diffusion and alignment number of times, make the transistor core area, knot face knot, junction capacitance, Rbb, the RC time constant is very little, to improve the speed and the integration density of circuit, has improved the rate of finished products of pipe and circuit simultaneously.

Description

At initial stage in the logical integrated circuit development, a kind of direct coupling transistor logic (DCTL) circuit once appearred.In DCTL, transistorized collector electrode output directly links to each other with the input of next stage transistor base, and its elementary cell is a phase inverter of being made up of transistor and resistance.As shown in Figure 1, resistance R for transistor at the corresponding levels provides drive current, makes it conducting in the unit when front stage transistor ends.And when the front stage transistor conducting, for front stage transistor provides collector current.

Though the structure of DCTL is simple, exists some important disadvantages, wherein the most outstanding is the problem (or claiming to rob current phenomena) of electric current maldistribution.Secondly the output logic amplitude of oscillation of DCTL is also lower, if introduce noise at input, causes the variation of base current easily, causes the instability of circuit.

Along with the development of integrated circuit technique, succeeded in developing integrated injection logic (I in recent years ²L) circuit is characterized in that: (1) adopts the circuit pattern of DCTL, forms a phase inverter with a load and a transistor, makes the circuit pattern simple, and element is few; (2) with the transistor collector region in the common integrated circuit as the emitter region, and with the emitter region as collector region, because DCTL has all crystals pipe emitter region common ground,, dwindled chip area greatly so in circuit, need not between each phase-reversing tube to isolate; (3) with the diffusion resistance among the PNP constant-current source replacement DCTL of common base connection, reach the reduction power consumption, dwindled the purpose of area.Have the integration density height, quality factor is good, die area is little, manufacturing process is simple, rate of finished products is high, can with the production of integrated circuits of other type on same chip, and the advantage that can under the situation of low-voltage, low current, work.But also have some shortcomings: promptly speed is lower, and logic swing is little, and interference free performance is poor, and as polylith I ²When the L circuit gathers together and uses, exist the problem that can the injection current of power supply uniform distribution in each piece circuit, or the like.These all will bring certain trouble to the use of circuit.

The present invention is exactly at I ²On the basis of L circuit, for overcoming I ²The shortcoming of L, the new improvement of in the design of pipe and load, doing.

Feature of the present invention is: it is under same design rule that A, discrete transistor are made: (1) adopts reverse common emitter back side ground structure; (2) adopt expansion extension base on the buried regions; (3) adopt NS or two kinds of dissimilar Schottky collectors of PS; (4) plane such as employing, V-shaped groove or vertical channel or air insulated technology extensively realize lead-in wire hole autoregistration; (5) adopt polysilicon base and inversion metal or metal silicide; The design of B, circuit: (1) adopts polysilicon resistance as load; (2) adopt polysilicon MOS to be similar to the complementary load of CMOS; (3) adopt Schottky-polysilicon or polysilicon diode to increase logic function as input.

The present invention has adopted best technological design, not only can shortened process, reduce diffusion and alignment number of times, and also be that the minimum and the optimization of die and circuit created condition.According to design philosophy of the present invention, can make 10 kinds of different reverse transistors, four kinds of loads, three kinds of inputs, four kinds of isolation, and be combined into the different circuit form of hundreds of kind.

The formal specification technology of the present invention that combines with load and transistor below.

The logical circuit of A, ten kinds of resistance-reverse direct couplings of transistor:

1, the isolation technology of plane, V-shaped groove or vertical channel such as employing:

A-1, resistance-PNS Schottky anti-saturation transistor are patrolled (R-PNSTL)

The equivalent circuit diagram of R-PNSTL is seen figure (2) a.Be example now, introduce the making of how finishing R-PNSTL with three kinds of different partition methods with the R-PNSTL circuit:

(1) planar isolated technology such as:

The vertical view of R-PNSTL is seen figure (2) b, and process section is seen figure (2) C.

Expand base technology on a, the buried regions: about 10 ^-3The P of Ω cm ⁺Expand buried layer above silicon polished, the concentration that expands phosphorus should be lower than P ⁺Substrate can not form PN junction before extension, then growing high resistant N ^- Epitaxial loayer 2～3 μ utilize the phosphorus feature bigger than boron diffusion coefficient to make epitaxial loayer form N ^-Go up to expand the base, base impurity is distributed as surface light (helping forming the Schottky collector), below densely (help reducing Rbb, improve the speed that discharges and recharges), this Impurity Distribution also can form an accelerating field in the base, can improve the characteristic frequency fT of tube core, also can prevent base barrier layer break-through, improve BVceo and improve upwards β, (on expand the also available outer notes phosphorus of delaying in base or annotate arsenic technology substitute).

B, etc. planar isolated technology: on epitaxial wafer earlier long 600 SiO ₂, grow 1500 again

Si ₃N4, the photoetching isolated area, (plasma is carved Si after removing N, O ₃N ₄SiO is floated with BHF in the back ₂), do the sidewall selective oxidation, require SiO ₂Thickness is about 2 μ, can keep apart fully expanding the base on the extension.

C, polysilicon process: hole, first photoetching base, remove O, N, O, grow 5000 then

Polysilicon, face injects the square resistance that phosphorus is transferred polysilicon, is about 5000 then

Hypoxemia is carved and is removed polycrystalline resistance area hypoxemia in addition, expands phosphorus then, allows phosphorus penetrate polycrystal layer and enters the extension base always and form ohmic contact, last photoetching polysilicon strip, N ⁺Polysilicon strip can be done the base stage line of a plurality of discrete transistors and the once wiring of crossing the power supply aluminum strip, and the ohmic contact of connection power strip is (in order to reduce the square resistance of a polysilicon wire, also available inversion metal of polysilicon or metal silicide wiring or aluminum strip short circuit in parallel), N ^-Face annotate the phosphorus zone and then form load resistance.

D, Schottky collector technology: on silicon chip, use one deck polyamic acid (PA) earlier then at N ₂The following 400 ℃ of imidizations of atmosphere protection; long upper strata PECVD-SiNH film is carved collector then as the mask (also available aluminium is as the mask of etching PI) of etching polyimides (PI) under 300 ℃ then; power supply and base stage input hole; earlier with fluoro plasma with the figure transfer of photoresist to the PI film (or with chlorine plasma with the figure transfer of photoresist to the Al mask), carve PI with oxygen plasma then and go the hypoxemia on O, N, the O(polysilicon floating SiO for the second time ₂The time just go clean), steam Al and carve the making of promptly finishing whole R-PNSTL circuit behind the Al alloy.

(2) V-groove isolation technology, it is suitable for isolating thicker epitaxial loayer, and it and isoplanar process difference are two steps of a, b, and its process section is seen figure (2) d.

Expand base technology on a, the buried regions: about 10 ^-3The P of Ω cm ⁺(100) expand phosphorus above the polished silicon wafer, other requires equal planar isolated technology.

B, V-groove isolation technology: elder generation long 600 on epitaxial wafer SiO ₂Grow 1500 again

Si ₃N ₄The photoetching isolation channel requires lines with (110 directions are parallel; After removing N, O, with KOH or N ₂H ₄The corrosion V-shaped groove expands to the extension can stop corrosion after the base separates, and makes about 2 μ of sidewall selective oxidation of pipe then, and it is mainly in order to reduce sidewall parasitic capacitance and to use for later self-registered technology.

The equal planar isolated of other processing step.

(3) vertical channel isolation technology: process section is seen figure (2) e, and it is suitable for isolating thicker epitaxial loayer, its technical process with etc. planar isolated technology similar, the step b that difference is just isolated:

B: elder generation long 600 on the epitaxial wafer of face expansion phosphorus buried regions

SiO ₂Grow 1500 again Si ₃N ₄The photoetching vertical channel requires about 2 μ of groove width, goes to utilize behind N, the O characteristic of reactive ion anisotropic etching, carves the vertical silicon groove, stops cutting after isolating fully between the extension base, does the selective oxidation of sidewall then, makes vertical channel be entirely SiO ₂Fill up.In addition, the method for the also available selectivity electrophoresis of V-shaped groove or vertical channel glass dust is carried out glassivation and isolation.

The Schottky collector can be finished with general Al in PNST, it has the dual-use function of collector and catching diode, it is Schottky anti-saturation transistor special case, it is simple to have technology when making, diffusion and alignment number of times are few, help realizing lead-in wire hole autoregistration and edge, therefore have advantages such as die area is little, junction capacitance is little, and the RC time constant is little, charge storage is little, the amplitude of oscillation is little, speed is fast.Also available Al of polysilicon or inversion metal or metal silicide short-circuit further reduce the square resistance of lead-in wire.

A-2 resistance-NPS Schottky anti-saturation transistor logic (R-NPSTL)

The equivalent circuit diagram of R-NPSTL is seen figure (3) a, and vertical view is seen figure (3) b, and process section is seen figure (3) c.

R-NPSTL circuit characteristic and manufacturing process are similar to the R-PNSTL circuit, and difference is: negative supply-Vcc → positive supply+Vcc, the minority carrier in the NPST base are electronics, than the hole among the PNS bigger mobility is arranged, so speed are faster.

The manufacturing process difference is: P ⁺Substrate → N ⁺Mix the As substrate; Expand P buried regions → expansion B buried regions; N ^-Last expansion extension base → P ^-Last expansion extension base; P injection → the B of polysilicon resistance injects; The polysilicon line is by expanding P → expansion B, and the Schottky collector is by Al → Ti-Al.

Planes such as the R-NPSTL circuit is the same with the R-PNSTL circuit, and is also available, V-shaped groove or vertical channel are isolated.

A-3, resistance NPNS transistor logic (R-NPNSTL).

The circuit diagram of R-NPNSTL is seen figure (4) a, and process section is seen figure (4) b.

The circuit characteristic of R-NPNSTL and manufacturing process are similar to the R-NPSTL circuit, relatively NPST is big for the collector of NPNSTL and the area of emitter, therefore upwards β is big than NPST, load capacity is also big than NPST, and the Rbb of NPST is little than the Rbb of NPST, therefore the RC time constant is little, and speed is fast.

Difference is on R-NPNSTL and the R-NPSTL technology: the epitaxial loayer of NPNST is slightly thick than NPST, and the B buried regions expands to epi-layer surface on not, at N ⁺Substrate and N ^-Form a P type interlayer, N between the epitaxial loayer when boron penetration polysilicon and hole, base ^-Epitaxial loayer expands the base that then forms the NPN pipe after logical with P type interlayer, does not expand the N of B ^-The epitaxial region then becomes collecting region, it and base stage hole join by autoregistration, this not only can make Rbb significantly reduce, the area of collector and the β that makes progress are enlarged markedly, but behind NSBD of collector polyphone output voltage swing is reduced, same R-NPNSTL is also available to wait plane, V-shaped groove or vertical channel isolation.

The R-NPNSTL circuit influences speed (it is opposite with the effect that Rbb reduces) owing to there is not clamped Schottky diode to have charge storage.

A-4 resistance-PNPS transistor logic (R-PNPSTL).

The R-PNPSTL circuit diagram is seen figure (5) a, and process section is seen figure (5) b.

R-PNPSTL and R-NPNSTL circuit difference are: use negative supply-Vcc, the available Ti-Al of series connection PS Schottky diode (PSBD) finishes, and other technological measure is opposite with R-NPNSTL, i.e. P → N, N → P.

A-5 resistance-NPNS ²Schottky anti-saturation transistor logic (R-N PNS ²TL)

R-NPNS ²The TL circuit diagram is seen figure (6) a, and process section is seen figure (6) b

R-NPNS ²TL and R-NPNSTL circuit difference are: increased a Pt-Si Schottky catching diode in base stage, can reduce charge storage and improve speed, but the amplitude of oscillation has been lower, this also helps raising speed.Require Pt-Si Schottky diode (NSBD ₁) forward junction pressure drop＞Ti Schottky diode (NSBD ₂) forward voltage drop, the difference of the two is the amplitude of oscillation.

A-6 resistance-PNPS ²Schottky anti-saturation transistor logic (R-PNPS ²TL)

R-PNPS ²The TL circuit diagram is seen figure (7) a, and process section is seen figure (7) b.

R-PNPS ²TL is as the anti saturation circuit of negative supply series, as long as PSBD ₁＞PSBD ₂The forward junction pressure drop, can finish foregoing circuit, amplitude of oscillation △ V is PSBD ₁With PSBD ₂Forward junction pressure drop poor.

More than six kinds of circuit plane, V-shaped groove or vertical channel isolation technology such as all can adopt.

2. adopt air insulated technology:

A-7 resistance-polysilicon base is inverted the NPS transistor logic (R-PSBNPSTL) of metal or metal silicide wiring

The R-PSBNPSTL circuit diagram is seen figure (8) a, and vertical view is seen figure (8) b, and profile is seen figure (8) C.

Air insulated technology:

A, emitter-self-alignment technology: about 10 ^-3Ω cm mixes arsenic N ⁺On silicon polished, first face expands B buried layer (concentration of B is lower than the AS in the substrate, makes substrate PN junction not occur) and grows 600 then

SiO ₂1500

Si ₃N ₄, 1500

Hypoxemia 2000

Refractory metal M(comprises Me, Ti, Ta, W and refractory metal silicide), 2000

P ⁺Polysilicon, polysilicon and refractory metal M are carved with plasma earlier in photoetching emitter hole then, remove O, N, O again, make to be inverted metal line M, form autoregistration with the emitter hole, make the Rbb minimum.

B, polysilicon process: carve the P under the polysilicon resistance district earlier ⁺Long again 0.5～1 μ polysilicon of polysilicon and refractory metal M, carve the polysilicon and the refractory metal M of polysilicon isolated area then, form the polysilicon base bar (PSB) of polysilicon resistance autoregistration and isolation, (also available low-temperature epitaxy of this step or molecular beam epitaxy technique are finished, make the extension head of district epitaxial single crystal layer of emitter hole silicon single crystal), inject the P type base that B transfers the square resistance of polysilicon resistance and forms the NPS pipe with face, grow 600 again SiO ₂, 1500

Si ₃N ₄Photoetching base stage hole and power supply are drawn the hole, remove O, N, O, and ion injects dense B and forms P ⁺Ohmic contact, (also available ion beam is carved the Si technology and is carved to P accurately ⁺Polysilicon layer replaces) grow 1500 again

Hypoxemia is carved the collector hole then and is removed O, N, O, with laser or electron beam annealing, or with silicon from injecting back low temperature thermal annealing, make the polysilicon monocrystallineization of emitter hole district (or marginal zone, emitter hole), form good intrinsic base region, finish the annealing that ion is annotated the B district simultaneously.

C, Schottky collector and metallization process: carve earlier and utilize following N, O hole after base stage hole and power supply are drawn the hole deoxidation, form autoregistration, deposit Ti-Al behind photoetching and alloy, promptly finishes entire circuit then.

This circuit has littler eb junction area than R-NPSTL circuit.Because junction capacitance, Rbb, and RC time constant minimum, so speed＞＞the R-NPSTL circuit, the β maximum because the area of collector and emitter than＞1, therefore makes progress, load capacity is the strongest, be a kind of desirable high speed circuit, M can use Mo, W, Ti, Ta or refractory metal silicide, requires can not melt when long low-temperature epitaxy layer or polysilicon.

The NPS transistor logic (R-PSBPSBDNPS TL) of A-8, resistance, polysilicon base and Schottky input

R-PSBPSBDNPS TL circuit diagram is seen figure (9) a, and profile is seen figure (9) b.

This circuit is compared with last circuit has increased the isolation of polycrystalline Schottky diode (PSBD) as input, therefore can become NAND circuit by NOR circuit, strengthens logic function.Can simplify logical design when VLSI designs, save element, reduce chip area, lower (amplitude of oscillation is PSBD to the amplitude of oscillation in addition ₁And PSBD ₂Forward junction pressure drop poor), the speed that discharges and recharges is faster.

On technology, collector hole (PSBD ₁), base stage hole (PSBD ₂) and the power supply hole to divide third photo etching, in addition, also to increase the Pt-Si Schottky processing, require PSBD ₁Forward junction pressure drop＞PSBD ₂

A-9, resistance polysilicon base, the NPN transistor logic (R-PSBPSDNPNTL) of polysilicon diode input.

The R-PSBPSDNPNTL circuit diagram is seen figure (10) a, and profile is seen figure (10) b.

This circuit is with the polysilicon diode PSD isolating diode as input, and because of forward junction pressure drop＜bc of PSD tie pressure drop, the two difference is the amplitude of oscillation, needs increase secondary N on the technology ⁺Diffusion (or injection of P and AS ion) but metallize fairly simple.

A-10, resistance, the NPS transistor logic (R-PSBPSDNPSTL) of polysilicon base polysilicon diode input.

The R-PSDNPSTL circuit diagram is seen figure (11) a, and profile is seen figure (11) b.

Forward junction pressure drop＞PSD of this circuit requirement PSBD, the two difference is the amplitude of oscillation, compares the N that can reduce by a collector with last circuit on the technology ⁺Diffusion (or injection), but to increase Schottky collector technology one time.

A-7 to A-10 has only listed the series of positive supply, in fact also the negative supply series of can drawing, because of the transit time＞electronics of hole in the base, to high speed circuit is disadvantageous, the input of finishing (only being suitable for A-9 and A-10) polycrystalline Schottky and polysilicon diode of the also available selective oxidation polysilicon of air insulated also is suitable for A-1 to A-6 in addition, in addition, technology and cross-section structure also can be done some changes, to adapt to our unit's working condition.

B, the above introduction with resistance as load and ten kinds of direct coupling transistor logics that reverse transistor is formed, they can adopt four kinds of isolation (waiting plane, V-shaped groove, vertical channel and air insulated), three kinds of inputs (directly input, polycrystalline Schottky, the input of polycrystalline diode), three kinds of two-layer wiring technologies (the once wiring of polysilicon, Al and inversion metal line or silicide), they can be combined into various circuit structures.

Except ohmic load, also available I ²Lateral complementary transistor among the L, and two kinds of complementary polysilicon MOS load and above ten kinds of reverse transistors that are similar to CMOS are combined into new circuit structure, for simply, each load is only drawn and the structure of A-1, A-2 combination.

B-1, lateral PNP and NPS Schottky transistor logic (PNP-NPSTL)

Circuit diagram is seen figure (12) a, and vertical view is seen figure (12) b, and profile is seen figure (12) C.

Technology: about 10 ^-3Ω cmN ⁺Silicon polished about 2～3 μ, the 0.3 Ω cmN of growth that goes up ^-Epitaxial loayer expands boron buried regions (or injecting B) and forms P type base in NPS die district, with O, N, O and selective oxidation, technology is isolated die, opens base stage hole and power strip hole and goes O, N, O to expand P ⁺(or injecting dense B), long again hypoxemia and carve the hole that contacts of base stage, power strip is finished once wiring with Al, and the medium of making two-layer wiring with PL is carved the collector hole and removed PL then, O, N, O finish the wiring of Schottky collector and secondary with Ti-Al and promptly finish entire circuit behind alloys.

B-2, horizontal NPN and PNS Schottky transistor logic (NPN-PNSTL).

On the technology: N ⁺→ P ⁺, P → N, P ⁺→ N ⁺, Ti-Al → Al.

PMOS that B-3, drain-gate connect altogether and NPS Schottky transistor logic (PMOS-NPSTL).

Circuit diagram is seen figure (14) a, and vertical view is seen figure (14) b, and profile is seen figure (14) C.

The PMOS-NPSTL that drain-gate connects altogether need adopt double level polysilicon and silicon gate self-aligned technology, as long as the V of control PMOS _T＞+0.4V pinch off promptly has the effect (NPST of the complementary load that is similar to CMOS ₁, admittance Vc ₁=0.4V, load PMOS ₂Pinch off; NPST ₂Admittance not, VC ₂=0.7V, load PMOS ₃Conducting).

NMOS that B-4, drain-gate connect altogether and PNS Schottky transistor logic (NMOS-PNSTL).

Circuit diagram is seen figure (15) a, and profile is seen figure (15) b.

It is just in time opposite with the polarity of PMOS-NPSTL, Vcc →-Vcc, P ⁺→ N ⁺, N → P, P → N, N ⁺→ P ⁺, Ti-Al → Al.

It also needs to adopt double level polysilicon and silicon gate self-aligned technology, as long as the V of control NMOS _T＜-0.4V pinch off promptly has the effect (PNST of the complementary load that is similar to CMOS ₁Conducting, Vc ₁=-0.4V, NMOS ₂Pinch off, PNST ₂Not conducting, Vc ₂=-0.7, NMOS ₃Conducting).

The PMOS of B-5, grid ground connection and NPS Schottky transistor logic (PMOS-NPSTL).

Circuit is seen figure (16) a, and vertical view is seen figure (16) b, and profile is seen figure (16) C.

It is compared with the PMOS-NPSTL that drain-gate connects altogether, need to increase the boron buried layer in a NPS die district, (form on the extension and expand the base), or in die district injection B formation base, but can reduce double level polysilicon and silicon gate self-aligned technology, it utilizes O, N, the O mask of selective oxidation, can form the dielectric of grid.

Need only control V during circuit production _T＞-0.4V pinch off promptly is similar to

Effect (the NPST of the complementary load of MOS ₁Conducting, Vc ₁=0.4V, load PMOS ₂Pinch off, NPST ₂Not conducting, Vc ₂=0.7V, load PMOS ₃Conducting).

The NMOS of B-6, grid ground connection and PNS Schottky transistor logic (NMOS-PNSTL).

Circuit diagram is seen figure (17) a, and profile is seen figure (17) b.

It is compared with last circuit, if polarity upset, Vcc →-Vcc, P ⁺→ N ⁺, N ⁺→ P ⁺, P → N, N → P, Ti-Al → Al get final product.

Require the V of control NMOS during circuit production _T＜0.4V pinch off promptly has the effect (PNST that is similar to the complementary load of CMOS ₁Conducting, Vc ₁=-0.4V, load NMOS ₂Pinch off, PNST ₂Not conducting, Vc ₂=-0.7V, load NMOS ₃Conducting).

Because the present invention has adopted various self-registered technologies widely in the making of pipe and circuit, the alignment number of times reduces when making photoetching, technological process is simple, improved the rate of finished products of pipe and circuit, also do very for a short time simultaneously, and improved the integration density of pipe and circuit because of die area and junction area.Below be that the domestic existing integrated circuit for example waits planar I ²The comparison of L circuit and PNS of the present invention or NPS die-size, (figure is relatively shown in figure (18)):

The model die area comprises the die area figure number of wall

I ²L 5 * 10,=50 6 * 11=66 figure (18) (a)

PNS or NPS 1 * 3.5=3.5 2 * 4.5=9 figure (18) are (b)

From as can be seen above, owing to extensively adopting various self-registered technologies, therefore can make die area, junction area is done minimumly, and junction capacitance, Rbb, Rc time constant are also minimum, fastest, the β maximum that makes progress, load capacity is the strongest.

The present invention is mainly used in digital circuit, can utilize its integration density height, low in energy consumption, low and the fireballing characteristics of supply voltage, can make the gate circuit series of microprocessor or formation low-voltage, be used for the toy circuit, tv remote control switch, camera etc. need with the occasion of dry cell as power supply.Also can utilize the good characteristics of its anti-radiation performance, need be used to the occasion of nuclear hardening.

Claims (2)

1, the transistor logic coupling circuit of reverse operation is characterized in that:

(1) adopts the input of polysilicon Schottky diode;

(2) adopt polysilicon diode PSD input;

(3) adopt polysilicon resistance as load;

(4) adopt the polysilicon MOS of polysilicon MOS that drain-gate connects altogether or grid ground connection to be similar to the complementary load of CMOS.

2, the manufacture craft of the transistor logic coupling circuit of reverse operation is characterized in that:

(1) adopts discrete planar collecting utmost point autoregistration and the base stage hole self-registered technology of waiting;

(2) adopt sidewall refractory metal or infusibility silicon compound base stage and emitter-self-alignment technology;

(3) plane, V-shaped groove, vertical channel (or electrophoresis glass dust is filled out groove) or air insulated technology such as employing;

(4) adopt reverse common emitter back side ground structure;

(5) expand the base on the employing extension buried layer;

(6) adopt NS or PS Schottky collector;

(7) connect each discrete transistor with the polysilicon lead-in wire;

(8) once connect up with aluminium and connect each discrete transistor;

(9) finishing inversion with refractory metal or refractory metal silicide once connects up.

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