CN86106353A - Semiconductor device with a plurality of transistors - Google Patents
Semiconductor device with a plurality of transistors Download PDFInfo
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- CN86106353A CN86106353A CN86106353.8A CN86106353A CN86106353A CN 86106353 A CN86106353 A CN 86106353A CN 86106353 A CN86106353 A CN 86106353A CN 86106353 A CN86106353 A CN 86106353A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
- H01L31/075—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PIN type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
- H01L31/202—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials including only elements of Group IV of the Periodic System
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
- H01L31/202—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials including only elements of Group IV of the Periodic System
- H01L31/204—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials including only elements of Group IV of the Periodic System including AIVBIV alloys, e.g. SiGe, SiC
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/548—Amorphous silicon PV cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
An amorphous Pin or niP containing semiconductor device wherein at least one interfacial layer is made of a semiconductor or insulator having a higher resistivity than the semiconductor of the adjacent interfacial layer. The interface layer is between the semiconductor layer or between the semiconductor and the electrode; the doping amount in the P type or n type layer at the P/i or n/i junction interface is minimum, and the doping amount gradually rises in the direction of the P/i electrode junction interface or the n/i electrode junction interface; or the P-type semiconductor layer with higher impurity density and/or the n-type semiconductor layer with higher impurity density are/is arranged between the P-type semiconductor layer and the P-type semiconductor layer on the same side, and/or between the n-type semiconductor layer and the n-type semiconductor layer on the same side.
Description
The present invention relates to semiconductor device, particularly relate to and be included in the semiconductor device that the photronic semiconductor device that has high open circuit voltage under the light radiation or photronic photoelectric conversion efficiency are improved.
Up to the present, as the material of optical-electrical converter, solar cell for example, employing be a kind of semi-conducting material that contains amorphous semiconductor such as a-Si:H, a-Si
1-x:Cx:H, a-Si
1-xGex:H, a-Si:F:H, a-Si
1-xNxH, a-Ge:H, a-Si
1-xGex:F:H, a-Si:H, uc-Si:H, uc-Si
1-xGex:H(wherein x satisfies relational expression 0＜X＜1) or partly comprise the semi-conducting material of these amorphous semiconductors.
Common solar cell has the Pin of stratiform, (niP, PinPin ... or niPniP ... etc. structure, they are by sequentially depositing congener amorphous semiconductor or just deposit the different types of amorphous semiconductor with wide energy gap in their doped layer.Except because during device production and the distribution of the dopant that causes of later thermal diffusion, the doping density in P type or n type layer is uniformly on thickness direction, is generally 0.01 to 5 atomic percentage.
Fig. 9 shows the common semiconductor device that solar cell adopted that the Pin N-type semiconductor N that uses three-decker is made.In Fig. 9, digital 31 is glass substrate, and a transparency electrode 32 is adhered on it.On transparency electrode 32, form p type semiconductor layer 34 successively, i type semiconductor layer 35 and n type semiconductor layer 36.On n type semiconductor layer 36, form an electrode 37 then.Semiconductor device 38 is made of glass substrate 31, transparency electrode 32, p type semiconductor layer 34, i type semiconductor layer 35, n type semiconductor layer 36 and electrode 37.
On above-mentioned semiconductor device 38, the direction that light arrow in Fig. 9 is pointed out is injected glass substrate 31, and sees through glass substrate 31 and electrode 32, and irradiation is to p type semiconductor layer 34, i type semiconductor layer 35 and n type semiconductor layer 36 then.Because this irradiation is when producing electronics and hole in each semiconductor layer 34,35 and 36.Electronics is collected in the n type layer and the hole is collected in the P type layer then, therefore produces positive charge on transparency electrode 32, produces negative electrical charge on electrode 37.Its sample just produces opto-electronic conversion, and semiconductor device 38 is had as photronic function.
Yet its shortcoming of semiconductor device with above structure is that it can not improve magnitude of voltage (representing with Voc below this) under open-circuit condition when photoirradiation, because this semiconductor device is being conditional aspect the raising internal electric field.
For example, utilizing under the above-mentioned device situation, when requiring electromotive force,, can be together in series a plurality of devices in order to overcome above-mentioned shortcoming greater than Voc.Yet, even so, suppose that the Voc of each device can improve, Chuan Lian device count can reduce so.Further, even if total all devices the conditional situation of area under, the method that increases by the area that makes each semiconductor layer can be suspected the performance of device and can improve greatly.
When noticing the structure of semiconductor device, effectively result of study is, we inventor finds under the situation of total area that does not increase all devices and series connection number of devices, found out than common semiconductor device have higher Voc and under specific voltage the semiconductor device of higher electric current (operating current), and realized this semiconductor device among the present invention.
In addition, generally all know, in common semiconductor device, when impurity density becomes big, diminish at p type semiconductor layer with at the contact resistance that reaches between the electrode of n type semiconductor layer and n type layer side between the electrode of P type layer side.It is desirable that this contact resistance is diminished, because when p type semiconductor layer and n type semiconductor layer during as photovoltaic devices, and solar cell for example, this resistance has reduced the duty factor of photovoltaic devices.Therefore, from then on viewpoint is set out, and wishes to increase impurity density.Yet, becoming too high as the impurity density of n type and p type semiconductor layer, the problem that can cause is that the characteristic as photovoltaic devices can degenerate, this is owing in those parts that contain impurity big optical absorption loss is arranged.
The present invention is in order to address the above problem, its objective is semiconductor device that a high open circuit voltage that has is provided and the semiconductor device that photoelectric conversion efficiency is improved under photoirradiation.
According to the present invention, it provides a kind of semiconductor device, and it is formed by first and second electrodes and by the accumulation semiconductor layer of the P type that contains amorphous fraction, i type and n type.Or by comprising amorphous fraction and being formed at the accumulation semiconductor layer of the n of two main lip-deep electrodes type, i type and P type.It is characterized in that having at least a boundary layer is to be made by semiconductor or insulator, and its resistivity is higher than the semiconductor that is adjacent to boundary layer, this boundary layer be between the semiconductor layer or semiconductor and electrode between.
The present invention further provides the semiconductor device of forming by the Pin type that contains noncrystal semiconductor layer and niP type layer and at least two electrodes, it is characterized in that the doping in P type and n type layer can be minimum on the junction interface of P|i or n|i, and on the direction at the interface that tends to P| electrode or n| electrode, increase gradually.
The present invention further provides semiconductor device, it comprises the niP type that contains amorphous semiconductor or Pin type layer and the electrode that is attached to P type layer in semiconductor, with the electrode that in semiconductor, is attached to n type layer, it is characterized in that (I) one of them p type semiconductor layer at least has the conduction type identical with P type semiconductor and higher impurity density and (II)-n type semiconductor layer has and the same conduction type of n N-type semiconductor N, and higher impurity density, between between the electrode of p type semiconductor layer and p type semiconductor layer homonymy and/or between the electrode of n type semiconductor layer and n type semiconductor layer homonymy.
In the present invention, noun " Pin type or niP type device mean that device comprises following each layer at least: (A) a kind of conductive type layer, (B) non-doping or slightly some doping be actually intrinsic layer and (C) a kind of layer and at least two electrodes of and above-mentioned conductivity type opposite.And then it in fact comprises the device that many P, i and/or n layer are formed.And the cascade connection type device of being piled into by Pin or niP unit.
Fig. 1 comprises the semiconductor device of a Pin type semiconductor layer and the sketch of first kind of situation of explanation the present invention.
Fig. 2 comprises the semiconductor device of a niP type semiconductor layer and the sketch of first kind of situation of explanation the present invention.
Fig. 3 is the view of the semiconductor device embodiment of second kind of situation of explanation the present invention.
Fig. 4 is the view of the common semiconductor device embodiment of explanation.
Fig. 5 is that explanation the present invention is used in the example of second kind of dopant distribution in the Pin type semiconductor layer under the situation and the view of the example of dopant distribution in common Pin type semiconductor layer.
Fig. 6 is the diagram of the V-I characteristic of the solar cell that is obtained in the example 2 in the example 12 and by comparison.
Fig. 7 is the view profile of the semiconductor device in the example 13 of the third situation of the present invention.
Fig. 8 is at the example 13 and the curve chart of the V-I characteristic of the semiconductor device in the example 3 by comparison.
Fig. 9 is the view profile of common semiconductor device.
At first the first kind of situation of the present invention according to the claim 1 that is mentioned to later described.
Noun " the Pin type device that contains amorphous semiconductor " means that generally such device namely has structure used in a-Si photovoltaic devices or photodiode, and is any satisfied The equal of the semiconductor devices of this condition can adopt in the present invention.
Moreover noun " semiconductor that contains amorphous " means that it is that semiconductor or (3) amorphous semiconductor that is dispersed in the amorphous semiconductor is the semiconductor that is dispersed in the big granular Crystalline Semiconductors that (1) semiconductor only forms (2) crystallite semiconductor by amorphous. These semiconductors usually are referred to as non-single crystal semiconductor.
Here preferably use the a-Si:H of boron-doping, a-Si1-xCx:H, or other similar material is as the P type (hereinafter referred to as P type layer) that contains amorphous semiconductor; A-Si:H, a-Si1-xGex:H, or other similar material is as the i type layer (hereinafter referred to as i type layer) that contains amorphous semiconductor; Mix the a-Si:H of phosphorus, these are to be used in common amorphous semiconductor photovoltaic devices or the photodiode as the N-shaped layer (hereinafter referred to as N-shaped layer) that contains amorphous semiconductor for uc-Si:H or other similar material.
Be higher than resistivity with the adjoining semiconductor layer of this boundary layer as its resistivity of boundary layer of the present invention, usually best employed its conductance of layer be not more than i type layer conductance 1/10th (for example the conductance of i type layer is approximately 5 * 10 in the a-Si:H situation-9（Ω·Cm）
-1) and be not more than one of the percentage of the conductance of the P type layer of adjacent interface layer or N-shaped layer. For example, the object lesson of above-mentioned boundary layer is by the resulting oxidation titanium film of electron beam vacuum deposition method or silicon oxide film; Si1-xNx:H or Si1-xCx:H(wherein x satisfies relational expression 0＜X＜1), Si1-x Cx：X：Y、Si
1-xNx:X:Y or Si1-xOx:X:Y(wherein x satisfies relational expression 0＜X＜1, and x is H, Cl, F or Br, and Y is H, Cl, F or Br), above component is to short circuit current, and the impact of the curve factor and other factors is little, and the insulating barrier that other layers are had no adverse effect. In these examples, Si1-xCx:H(here x satisfies relation or 0＜X＜1) with can significantly improve Voc this Point is especially favourable.
Above-mentioned semi-conductive resistivity can easily be regulated by changing its composition ratio, i.e. the value of doping in the above-mentioned fraction of mentioning or " x ".For example, in the present invention, the trivalent of from 0.001 to 5 atomic percentage or pentad such as phosphorus or boron can be used as dopant.
Its resistivity is higher than the boundary layer of adjacent with it semiconductor layer resistivity, can be formed on by the following face place of respectively tying in the Pin N-type semiconductor N device shown in Figure 1: the junction interface (a) of transparency electrode 2 and P type layer 3; The junction interface (b) of i type layer 4 and P type layer 3; The junction interface (c) of n type layer 5 and 1 type layer 4; The junction interface d of metal electrode 6 and n type layer 5; And following each place, junction interface of niP N-type semiconductor N device shown in Figure 2: the junction interface (e) of transparency electrode 2 and n type layer 5; The junction interface (f) of metal electrode 6 and P type layer 3; The junction interface (b) of i type layer 4 and P type layer 3; The junction interface (c) of n type layer 5 and i type layer 4 and in P type layer and n type layer.Under semiconductor device situation shown in Figure 1, junction interface (a) at transparency electrode 2 and P type layer 3, particularly the boundary layer of the junction interface (b) of P type layer 3 and i type layer 4 formation is best, because these interfaces are in the light incident side of light, so Voc can further improve.
Comprise semiconductor or the insulator of its resistivity greater than the resistivity of the contiguous semiconductor layer of boundary's interbed at the thickness of formed boundary layer between the semiconductor layer or between semiconductor layer and electrode, its value is 10 to 500
, the best is 10 to 200
, be more preferred from 10 to 100
, when interfacial layer thickness less than 10
The time, the raising of Voc is a bit, otherwise, when it is worth greater than 500
The reduction of the curve factor becomes very big.
In semiconductor device of the present invention, the manufacturing of boundary layer can be adopted glow discharge decomposition method, sputtering method, hot CVD (chemical vapour deposition (CVD)) method, optical cvd method or other similar methods.Basically all there is the device of Pin type or niP semiconductor layer to can be used as the monotype device with this, cascade connection type device, integrated-type device.Adoptable in the present invention semiconductor is restriction especially not, can use any semiconductor device that comprises Pin type or niP N-type semiconductor N as long as that is to say.
Preferably use under light source such as the fluorescent lamp of low illuminance by the semiconductor device of the present invention that said method obtained, under this light source irradiation, series resistance can not become serious problem, because semiconductor device of the present invention can make series resistance increase, and therefore reduces the curve factor or other similar factor.
Can be made into semiconductor device as top mentioned device, it has high electric current under specific voltage and high Voc as long as very small amount of dopant is added to makes this degree that reaches in the boundary layer, and promptly the resistivity of boundary layer is not less than the resistivity of adjoining with it semiconductor layer.
Below second kind of situation of the present invention explained that it requires 7 corresponding to the claim of mentioning later.
As the i type layer that contains amorphous Pin type or niP type semiconductor layer, the thickness of this layer is approximately 2500 to 9000 in the present invention
Comprising for example: a-Sic:H, a-Si:H, a-SiGe:H, a-Ge:H, a-Si:F:H, a-SiN:H or a-SiSn:H; Or these are by phosphorus or boron doped amorphous semiconductor.Can adopt the layer that forms by mixing as P type layer, its thickness is about 80 to 300
, a-SiC:H for example, μ c-Si:H or a-Si:H with the III a family element of periodic table as P type dopant.And then, as n type layer, can adopt the layer that forms by mixing, its thickness is about 80 to 300
, for example, a-SiC:H, μ c-Si:H or a-Si:H, the V a family element of using periodic table is as n type dopant layer.Yet the i type layer among the present invention, P type layer and n type layer are not to limit to these layers above-mentioned.
In the mentioned in the above P type layer, the layer that is obtained by III a family element doping a-SiC:H or a-Si:H is best, because they have little activation energy and little optical absorption loss.And then in the related in the above n type layer, with the V a element doping a-SiC:H of family, the layer that μ c-Si:H or a-Si:H obtained is for best, because they have little activation energy and high conductivity.
In the explanation in front, illustrated that mixing as the P type is that the III a family element of periodic table is B, Al, Ga, In and Te and is that the V a family element of periodic table is N, P, As, Sb, Te and Po as n type dopant.Yet employed in the present invention dopant is not confined to those elements recited above.Any dopant is as long as it can produce the P type with mixing or the n N-type semiconductor N all can be used.
In the Pin type or niP type semiconductor layer of second kind of situation of the present invention, at least in P type layer and n type layer to have the minimum part of dopant dose be in the junction interface of P/i or n/i and this dosage is progressively increasing on the junction interface direction of P/ electrode or n/ electrode.
Fig. 3 is the embodiment of explanation semiconductor device of the present invention.In Fig. 3, on glass substrate 11, provide again-p type semiconductor layer 13 with transparency electrode 12, provide by this way, promptly dopant dose is minimum on the junction interface of P/i.On p type semiconductor layer 13, form i type semiconductor layer 14 successively, n type semiconductor layer 15 and back electrode 16.
In the semiconductor device of Fig. 3, dopant dose is minimum on the P/i of junction interface.Yet semiconductor device can prepare in this manner, i.e. the distribution of the dopant in p type semiconductor layer is uniformly and dopant dose is minimum on the n/i of the junction interface of n type semiconductor layer.Semiconductor device can also this mode prepare, and promptly in P type and the two-layer surface layer of n N-type semiconductor N, dopant dose is minimum on junction interface P/i and n/i respectively.In Fig. 3, light 17 is injected from P type layer side, but it also can be injected from n type layer side.The quantity of Pin layer is not restricted to one, and it can be stacked into 2 to 5 layers.In this case, some layers of first Pin layer top can prepare by this way, and promptly dopant is minimum on the junction interface of i layer, or makes with the common Pin layer that is shown in Fig. 4.Number 18 in Fig. 4 is common P type layers.
Some are used in dopant dose 0.01 to 5 atomic percentage normally in P type or the n type layer, but in the present invention near the junction interface of P/i or n/i (minimum at this dopant, preferably from the junction interface 20 to 30
That part, be more preferably from the junction interface 100
That part of doping preferably be not more than 0.01 atomic percentage, more preferably be not more than 0.001 atomic percentage.These facts are to understand from the trial result of inventor's semiconductor device.
The distribution that requires dopant is that the junction interface from the junction interface of P/i or n/i to P/ electrode or n/ electrode progressively increases.Utilize this structure, the diffusion that enters the dopant of i layer is minimized, and the interface between i layer and the doped layer improves.Therefore open circuit voltage is improved.
Illustrating of " increasing gradually " in this manual is not to mean because the increase naturally of the dopant that thermal diffusion causes, but mean owing to regulate the continuous or stepped increase that amount obtained of dopant when mixing, under the sort of situation, from improving the viewpoint of Voc, each component rather than the dopant preferably talked in P type or n type layer are not have marked change.
Fig. 5 is the view of the embodiment of dopant distribution in the semiconductor device of explanation the present invention second kind of situation, and wherein P type i type, and n type layer is respectively a-SiC:H, a-Si:H and a-Si:H.A shows the distribution curve of P type dopant in the p type semiconductor layer in Fig. 5, and B shows the distribution curve of n type dopant in the n type semiconductor layer, and C and D show the distribution curve of P type dopant and n type dopant in the common semiconductor device.
Fig. 5 only shows the preferred examples of dopant distribution in a kind of P type or the n type layer, and distribution occasion need not be confined to the condition shown in Fig. 5.In other words, only require that the dopant content that has a conductive layer at least is minimum at P/i or place, n/i junction interface.
When application a-SiC:H produced semiconductor device of the present invention as doped layer, making did not have the a-SiC:H that mixes to locate as the junction interface that insulation is present in P/i or n/i.So in the present invention structure can adopt.
The electrode that adopts among the present invention is restriction especially not, but can adopt transparent electrode, metal electrode, silicon compound electrode, or the pellet electrode that obtains from produce normally used these materials of solar cell.
Produce arrangement of semiconductors among the present invention and can adopt capacity plate antenna coupled mode ionomer cvd device, electric induction coupled mode plasma CVD equipment, heat plasma body device, ecr plasma CVD device, the optical cvd device is excited formula CVD device and other similar device.But adoptable device is not limited to these.Produce the method for semiconductor device and the not restriction especially of material of use thereof among the present invention.
Pin structure among the present invention or niP structure are structures commonly used in photoelectric device that contains amorphous semiconductor and photodiode.
The third situation of the present invention of mentioning in the claim 16 after will illustrating below.
The situation of third aspect present invention is that semiconductor device comprises the niP type that contains amorphous silicon or the semiconductor layer of Pin type, wherein at least one semiconductor layer (1) has identical conductivity type and has higher impurity density with adjacent semiconductor layer (II), and this contains the niP type of amorphous silicon or the semiconductor layer of Pin type places between a semiconductor layer (II) and the electrode.
Being used for the Pin type that contains amorphous of the third situation of the present invention or the semiconductor of niP type is: as the i type semiconductor layer, can adopt thickness to be about 200 to 9000
One deck, material for example is a-Si:H, a-SiGe:H, a-Ge:H, a-Si:F:H, a-Sin:H or a-SiSn:H, these amorphous semiconductors of a-SiC:H or mix very a spot of B or P.Can adopt thickness to be about 80 to 300 as p type semiconductor layer
Doped layer, a-SiC:H for example, the layer that uc-Si:H or a-SiC:H form with the element doping of periodic table III a family.Also have,, can adopt thickness to be about 80 to 300 as the n type semiconductor layer
Doped layer a-Si:H for example, the layer that uc-Si:H or a-SiC:H form with periodic table V a family element doping.Yet, the i type among the present invention, P type and n type semiconductor layer are not limited to above-mentioned some that mention layer examples.
In the p type semiconductor layer of mentioning in the above, best with the layer that III a family element doping obtains with a-SiC:H or a-Si:H, this is because they have little activation energy to produce the hole little with optical absorption loss that the semiconductor conductance is had the tribute boat.Also have, in the above-mentioned n type semiconductor layer of mentioning, use a-SiC:H, μ c-Si:H or a-Si:H are best with the layer that V a family element doping obtains, this is that it has contribution and make it that high conductance be arranged semi-conductive conduction because they have little activation energy to produce electronics.Yet in above-mentioned i type, the material that is adopted in P type and the n type semiconductor layer is not limited to above-mentioned described material.
In the above description, the element of having described as P type dopant is the element of III a family in the periodic table, i.e. B, Al, Ga, In and Te, as the element of n type dopant be V a family in the periodic table element promptly, N, P, As, Sb, Te and Po.Yet dopant of the present invention is not limited to those that the top describes, and any dopant is as long as can produce the P type or the n N-type semiconductor N both can use with its doping.
In the present invention, be in p type semiconductor layer and between the electrode of p type semiconductor layer homonymy, and/or the impurity concentration that is in n type semiconductor layer and P type between the electrode of n type semiconductor layer homonymy and/or n type layer is 2 times greater than common impurity concentration, preferably 4 times.The upper limit of impurity concentration has no particular limits, but adjusts to no more than 10 atomic percentages usually.The thickness of high-density semiconductor layer is 10 to 300
, preferably 30 to 150
Thick.
Now example and the comparative example with regard to first, second and the third situation of the present invention describes.Wherein example 1 is to belong to first kind of situation of the present invention to example 11 and comparative example 1, and example 12 and comparative example 2 are to belong to second kind of situation of the present invention, and example 13 and comparative example 3 belong to the third situation of the present invention.
Example 1 is to example 8
With the hot CVD method thick be 1, the thick SnO of deposit 0.1 μ m on the sheet glass of 1mm
2Make glass substrate.
Above-mentioned glass substrate is heated to 240 ℃, and forming thickness in parallel plate capacitor coupled mode plasma CVD apparatus thereon is 150
P type a-SiC:H layer, the gaseous mixture of the diborane of three kinds of 100PPm of introducing 50Sccm in the device, promptly (A) diborane is released with single silane alkene, (B) diborane with methane dilution and (C) diborane with hydrogen dilution (A), (B) and (C) flow rate ratio is 1: 3: 1, and is that 13.56MHz and rf power are that 30W carries out the glow discharge decomposition with the rf frequency.
The carbon that contains 20 atomic percentages in the P type a-SiC:H layer of making approximately.The conductance of a-SiC:H layer is about 10
-7(Ω Cm)
1
After getting rid of remaining gaseous mixture, the gaseous mixture that will contain the methane of the single silane of 20Sccm and 30Sccm is incorporated in the device with the boundary layer of formation-a-SiC, and its thickness is shown in table 1.Without impurity gas.
After getting rid of remaining mist again, introduce single silane gas of 50Sccm, and the rf power of 13.56 rf frequency of describing with the top and 30W carries out glow discharge in the same way, and to decompose to form thickness be 7000
I type a-Si:H layer.Then, the same power of mentioning with the top is that rf carries out electric glow discharge method and goes to decompose, and the phosphine gas that passes to the 1000PPm of the 100Sccm that single silane and hydrogen with 20Sccm dilutes then is 300 with formation thickness
N type a-Si:H film.
Then, adopt the vacuum evaporator of resistance heating type, with on the aluminum evaporation as back electrode to make optical-electrical converter.
With above-described same mode, 5 optical-electrical converters have been prepared again.The open circuit voltage of 6 optical-electrical converters (Voc) and the curve factor record under the fluorescent lamp of 200Lux illumination.Its result is summarised in the table 1.
Example 9 to 11
Repeat the program of example 4 and, promptly, locate (hereinafter referred to as i/n) (example 10) everywhere in the junction interface of i type layer and n type layer in the place, junction interface of transparency electrode and P type layer (hereinafter referred to as TE/P) (example 9) at the following boundary layer of making; Locate (hereinafter referred to as n/Al) (example 11) with junction interface at n type layer and Al electrode.Open circuit voltage Voc records to example 8 by example 1 with the curve factor the samely, and its result is summarised in the table 2.
Comparative example 1
With the hot CVD method thick for deposition thickness on the sheet glass of 1.1mm be the SnO of 0.1 μ m
2And make glass substrate.
The glass substrate that makes is heated to 240 ℃, and forming thickness with parallel plate capacitor coupled mode plasma CVD equipment thereon is 150
P type a-SiC:H layer.Introduce three kinds of gaseous mixtures of the 1000PPm diborane of 50Sccm in the device, promptly (A) with the diborane of methane dilution and (C) with the diborane of diluted in hydrogen ((A), (B) and the ratio of flow rate (C) be 1: 3: 1), and is that 30W, frequency are that the radio frequency rf of 13.56MHz carries out the glow discharge decomposition with power with the diborane (B) of single silane dilution.
The conductance that the carbon amount of about 20 atomic percentages is included in a-SiC:H layer in the resulting P type a-SiC:H layer is about 10
-7(Ω .Cm)
-1
Then, after discharging remaining mist, single silane of introducing 50Sccm with above-mentioned same mode power be that the 30W frequency is that the radio frequency of 13.56MHz carries out glow discharge to decompose with formation thickness be 7000
I type a-Si:H layer.Then, carry out glow discharge with the radio frequency of above-mentioned same power and decompose, the phosphine gas that at this moment passes to the 1000PPm of the 100Sccm that single silane and hydrogen with 20Sccm dilutes is 300 with formation thickness
N type a-Si:H film.
Then, be heated by resistive the type vacuum evaporator, with in the Al evaporation as back electrode to make an optical-electrical converter.
According to above-mentioned same mode, 5 optical-electrical converters then are made into.In illuminance the Voc and the curve factor that records 6 optical-electrical converters under the fluorescent lamp of 200Lux.Voc is 0.60 to 0.62V(average out to 0.606V), the curve factor is 74.5%, these results are summarised in table 1 and the table 2.
Example 12 and comparative example 2
Prepared the solar cell of structure as shown in Figure 3 as test.
As its thickness of transparency electrode is 800
SnO
2Be deposited on the sheet glass with as substrate.
Is 150 with plasma CVD method with thickness
P type a-SiC:H film be deposited on the substrate.P type a-SiC:H is used SiH
4, CH
4And B
2H
6(being diluted to 1000PPm with hydrogen) as unstripped gas, and wherein 70
Film, the SiH of usefulness
4, CH
4And B
2H
6Flow be respectively 10Sccm, 30Sccm, 200Sccm.Then, continue glow discharge, when reducing B gradually
2H
6Air inflow the time, the a-SiC:H of remaining 80A deposition forms.B when the P layer deposition process is finished
2H
6Flow be zero Sccm, go out 7000 with the glow discharge decomposition method deposit
The i type a-Si:H layer of thickness.Then, going out thickness with glow discharge decomposition deposit is 300
N type μ c-Si:H layer, at that time with the PH of the 1000PPm of the 100Sccm of hydrogen dilution
3SiH with 20Sccm
4Mist pass through.Thickness is 1000
Al vacuum evaporation thereon as metal back electrode to make 1Cm
2Device.
Work as B
2H
6Volume flow when constant dopant dose in the P type layer be 2 atomic percentages.
For comparison purpose, be 150 except thickness
P type a-SiC:H be under above-mentioned constant flow rate outside the deposit, with method for preparing the solar cell of common type.
Prepared two kinds of solar cells are to measure its V-II characteristic under the fluorescent lamp of 200Lux in illuminance all, and its result is shown among Fig. 6.
The about 0.6V of the open circuit voltage of the solar cell of comparative example 2.Otherwise the open circuit voltage in Mrs's positive electricity pond of example 12 is 0.7V, can aware electric current and FF(curve duty factor) improvement arranged slightly.
Example 13
Fig. 7 shows the example 13 of semiconductor device of the present invention, and wherein semiconductor layer is the Pin type of three-decker.In Fig. 7 at p type semiconductor layer 24 and formed the p type semiconductor layer 23 of high impurity density between with lateral electrode 22.Semiconductor layer 23 is attached to the top surface of electrode 22 with under the basal surface of p type semiconductor layer 24.
In example 13, the structure of Pin type semiconductor layer is to be similar to use the made general photovoltaic devices of amorphous semiconductor and the structure of photodiode or other similar device.
Below, the method for the semiconductor device of preparation example 13 once is described.
At first, be transparency electrode at the electrode 22 of P type side, be deposited on the glass plate 21 SnO with sputtering method
2Be used as the material of transparency electrode, the thickness of electrode is 5000
Then, on the electrode 22 of P layer side, the p type semiconductor layer 23 of the high impurity density that makes with boron doped SIC: H with plasma CVD method.In the process of the p type semiconductor layer 23 that forms high impurity density, used SiH
4, CH
4And B
2H
6/ H
2(B
2H
6Concentration be 1000PPm) its flow rate is respectively 10Sccm, 30Sccm and 200Sccm.The thickness of the p type semiconductor layer 23 of resulting high impurity density is 100
, its impurity density is 4 atomic percentages.
Then, on semiconductor layer 23 except with B
2H
6Flow rate change into outside the 50Sccm, with above-mentioned same mode with plasma CVD method from B boron doped SIC: H makes p type semiconductor layer 24.The thickness of the p type semiconductor layer 24 that makes is 100
, its impurity density is 1 atomic percentage.
Then, with SiH
4Is that the i type semiconductor layer 5 of a-Si:H be formed on p type semiconductor layer 24 on glow discharge decomposition method with component as unstripped gas.The thickness of resulting i type semiconductor layer 25 is 5000
Then, use SiH
4And PH
3/ H2(PH
3Density be 1000PPm) decompose with glow discharge n type semiconductor layer 26 be formed on the i type semiconductor layer 25.SiH
4And PH
3/ H
2Flow rate be respectively 10Sccm and 50Sccm, the thickness of the n type semiconductor layer of making 26 is 300
, its impurity density is 0.5 atomic percentage.
And then, forming electrode 27 with vacuum evaporation Ag silver on the n type semiconductor layer 26 and on its side, the thickness of electrode 27 is 1000
Area according to the prepared semiconductor device of said method is about 1Cm
2, but might prepare its area reaches 1 to 500Cm
2Therefore, the area of device of the present invention is unrestricted.
In the semiconductor device of example 13, light is injected along the direction of arrow shown in Figure 7, resemble in semiconductor layer 23,24,25 and 26, produce electronics the semiconductor device in Fig. 9 and the hole right, and on the electrode 22 of P layer side, produce positive charge and on the electrode of n layer side, produce negative electrical charge.In the present example, because the electrode 22 of P layer side contacts with the p type semiconductor layer 23 of high-quality density, the contact resistance between them is able to remarkable reduction.And because the thickness of the p type semiconductor layer of high impurity density approaches, the optical absorption loss of this extrinsic region does not increase.
Comparative example 3
Repeat the technology of example 13, and to make the same quadrat method of p type semiconductor layer 24 in the example 13, same quality of materials makes 100
Semiconductor layer with the highdensity p type semiconductor layer 23 in the alternative 13.
For example 13 and comparative example 3 its V of semiconductor device-the I characteristic is at 100mW/Cm
2Solar simulator under measure.Its result is shown in Figure 8.
According to the V shown in Fig. 8-I characteristic, duty factor (F.F.) is to be calculated by following formula:
(maximum output)/(short circuit current * open circuit air pressure) * 100
The duty factor of example 13 is about 70%, and the duty factor of comparative example 3 is about 60%.
In example 13, the p type semiconductor layer 23 of high impurity density is to be between the electrode 22 and p type semiconductor layer 24 of P type layer homonymy.Yet, when the n type semiconductor layer of high impurity density being in the n type semiconductor layer and between the electrode 27 on the n layer side, also can reaching same effect.
And then in example 13, light is injected from P layer lateral electrode.But with electrode 27 make transparent after, light also can be injected from the electrode 27 of n layer side.
Though, in example 13, only form one group of P type, i type and n type semiconductor layer, the group number can reach 6 to 15, and stacking sequence can begin to be followed successively by the n type, i type and P type layer from the substrate of Fig. 7.
SnO in example 13
2Can be used as the material of transparency electrode, but other material for example ITO also can use.Yet Ag can be used as the material of the electrode 27 of n layer side, but also available other electric conducting material, such as Al or Au, conductor for example silicon and the synthetic silicide of other metal group, and these conducting metals and conductor pellet electrode or other similar electrode.
In example 13, the material of the semiconductor layer 23 of high impurity density is identical with p type semiconductor layer 24, but as long as it is that P type semiconductor also can be the material that is different from p type semiconductor layer 24.For example, replace the SiC:H in the example 13 also to be fine with Si:H, in the case, not only available B boron also can be with other impurity in the example 13.Certainly, adopting the semiconductor layer of same-type is that impurity can be used other kind material instead.This modification also is applicable to the n N-type semiconductor N and the n type semiconductor layer of high impurity density.
Impurity density changes to the p type semiconductor layer 23 of high impurity density discontinuously in the example 13 from p type semiconductor layer 24.Yet it also can increase by P type (or the n type) semiconductor layer from P type (or n type) semiconductor layer to high impurity density gradually.
Method as each layer of preparation semiconductor device in the example 13 can adopt sputtering method, vacuum vapor deposition method plasma CVD method or other similar method.But as long as used method can obtain film, any method all can adopt.For example, employed in the present invention CVD device includes, and as, parallel plate capacitor coupled mode plasma CVD equipment, electricity is led the coupled mode plasma CVD equipment, the hot CVD device, and ecr plasma CVD device, the optical cvd device is excited the CVD device of type.
The material that is used for forming each layer is not limited in those materials that adopted in the example 13.
Have than high electric current (operating current) under high Voc of common device and the specific voltage according to the semiconductor device of first and second kinds of situations of the present invention like that just as described above, therefore, it is best suited for the solar cell that consumption is used.Particularly be equipped in low-light (level) the light source for example electricity used down of fluorescent lamp and the solar cell on the electronic instrument.
And then, not only reduced between the electrode on p type semiconductor layer and the P type layer side according to the semiconductor device of the third situation of the present invention, and/or the contact resistance between the electrode on n type semiconductor layer and the n type layer side, and can also keep optical absorption loss very little, therefore, compare with common semiconductor device and can improve photoelectric conversion efficiency.
Claims (22)
1, semiconductor device comprises that one contains amorphous semiconductor Pin type layer or niP type layer and at least two electrodes, it is characterized in that, at least one boundary layer is to be made of semiconductor, or constitute by the semi-conductive resistivity that connects boundary layer near having high semiconductor or insulator, this boundary layer be between the semiconductor layer or be in semiconductor and electrode between.
2, according to the device of claim 1, wherein boundary layer is formed between P type semiconductor and the i N-type semiconductor N and/or is formed between n N-type semiconductor N and the i N-type semiconductor N.
3, according to the device of claim 1, wherein boundary layer is formed between a kind of semiconductor and electrode of conductivity type.
4, according to the device of claim 1, boundary layer wherein is from Si
1-xCx:X:Y, Si
1-xNx:X:Y and Si
1-xOx:X:Y(wherein x satisfies the relation of O＜X＜1; X is that H, Cl, F or Br, Y are H, Cl, F or Br) gang in select.
5, according to the device of claim 1, wherein boundary layer is Si
1-xCx:H(wherein x satisfies the relation of 0＜X＜1).
6, according to the device of claim 1, wherein boundary layer has at least one to be formed in the P type layer that contains amorphous semiconductor adjacent.
7, according to the device of claim 1, wherein boundary layer is formed on to P type and i type and contains between the semiconductor layer of amorphous.
8, according to any device of claim 1 to 7, wherein the thickness of boundary layer is 10 to 500
9, semiconductor device comprises Pin type layer or niP type layer and at least two electrodes that contain amorphous semiconductor, it is characterized in that, doping in P type or n type layer is minimum on the junction interface of P/i or n/i, and increases gradually on the direction at the interface that trends towards P/ electrode or n/ electrode.
10,, be the a-SiC:H layer one of in P type layer and the n type layer at least wherein according to the device of claim 9.
11,, be the a-Si:H layer one of in P type layer and the n type layer at least wherein according to the device of claim 9.
12, according to the device of claim 9, wherein doping rises on the direction at the interface that trends towards P/ electrode or n/ electrode gradually, and this part in P type or n type layer has 20 at least from the junction interface of P/i or n/i
Thick.
13, according to the device of claim 9, wherein doping rises on the direction at the interface that trends towards P/ electrode or n/ electrode gradually, and this part in P type or n type layer has 100 at least from the junction interface of P/i or n/i
Thick.
14, according to any one device of claim 9 to 11, wherein the dopant in the P type layer is the element of choosing from the family of B, Al, Ga, In and Tl.
15, according to any one device of claim 9 to 11, wherein the dopant in the n type layer is the element of choosing from N, P, As, Sb, Te and Po family.
16, semiconductor device comprises niP type layer or Pin type layer and at least two electrodes that contain amorphous semiconductor, it is characterized in that at least one semiconductor layer (1) and the semiconductor layer (II) of adjacency are same conductivity types, and have higher impurity density, and be between semiconductor layer (II) and the electrode.
17, according to the device of claim 16, conductivity type wherein is the P type and/or is the n type.
18, according to the device of claim 17, wherein the thickness of semiconductor layer (I) is 10 to 300
19, according to the device of claim 15, wherein P type and/or n type semiconductor layer (I) comprise-a-SiC:H.
20, according to any one devices of claim 17 and 19, wherein the P type and or n N-type semiconductor N (I) layer comprise-a-Si.
21, according to any one device of claim 17 to 19, wherein the doping density of the p type semiconductor layer of highly doped density and n type semiconductor layer (I) is the twice of semiconductor layer (II) or more times.
22, according to any one device of claim 17 to 19, wherein the doping density of the semiconductor layer of highly doped density (I) is 4 times or more times of semiconductor layer (II).
Applications Claiming Priority (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60247463A JPS62106670A (en) | 1985-11-05 | 1985-11-05 | Semiconductor device |
| JP247463/85 | 1985-11-05 | ||
| JP255681/85 | 1985-11-14 | ||
| JP60255681A JP2545066B2 (en) | 1985-11-14 | 1985-11-14 | Semiconductor device |
| JP61099939A JPS62256481A (en) | 1986-04-30 | 1986-04-30 | Semiconductor device |
| JP99939/86 | 1986-04-30 |
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|---|---|---|---|
| CN89104797A Division CN1018310B (en) | 1985-11-05 | 1989-07-14 | Semiconductor device |
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| CN86106353A true CN86106353A (en) | 1987-12-02 |
| CN1036817C CN1036817C (en) | 1997-12-24 |
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| US (1) | US5032884A (en) |
| EP (3) | EP0494090A3 (en) |
| KR (1) | KR870005477A (en) |
| CN (1) | CN1036817C (en) |
| AU (2) | AU600453B2 (en) |
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- 1986-11-01 EP EP19920104633 patent/EP0494090A3/en not_active Ceased
- 1986-11-01 EP EP92104628A patent/EP0494088B1/en not_active Expired - Lifetime
- 1986-11-01 DE DE3650712T patent/DE3650712T2/en not_active Expired - Lifetime
- 1986-11-01 EP EP86115170A patent/EP0221523B1/en not_active Revoked
- 1986-11-01 DE DE3650012T patent/DE3650012T2/en not_active Revoked
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| CN1097299C (en) * | 1997-03-10 | 2002-12-25 | 佳能株式会社 | Deposited film forming process, deposited film forming apparatus and process for manufacturing semiconductor element |
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| TWI668958B (en) * | 2017-03-31 | 2019-08-11 | 日商日本碍子股份有限公司 | Joint body and elastic wave device |
| CN110463038A (en) * | 2017-03-31 | 2019-11-15 | 日本碍子株式会社 | Conjugant and elastic wave device |
| CN110463038B (en) * | 2017-03-31 | 2020-05-22 | 日本碍子株式会社 | Bonded body and elastic wave element |
| CN111919385A (en) * | 2018-03-29 | 2020-11-10 | 日本碍子株式会社 | Bonded body and elastic wave element |
Also Published As
| Publication number | Publication date |
|---|---|
| AU6461986A (en) | 1987-05-07 |
| DE3650012T2 (en) | 1994-11-24 |
| EP0221523A2 (en) | 1987-05-13 |
| DE3650712D1 (en) | 1999-04-01 |
| DE3650712T2 (en) | 1999-09-30 |
| EP0494090A2 (en) | 1992-07-08 |
| AU600453B2 (en) | 1990-08-16 |
| AU6596690A (en) | 1991-01-24 |
| KR870005477A (en) | 1987-06-09 |
| EP0494088B1 (en) | 1999-02-24 |
| CA1321660C (en) | 1993-08-24 |
| EP0494090A3 (en) | 1992-08-05 |
| EP0221523B1 (en) | 1994-08-03 |
| EP0221523A3 (en) | 1989-07-26 |
| CN1036817C (en) | 1997-12-24 |
| EP0494088A1 (en) | 1992-07-08 |
| DE3650012D1 (en) | 1994-09-08 |
| AU636677B2 (en) | 1993-05-06 |
| US5032884A (en) | 1991-07-16 |
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